J784S4 Clock Identifiers

Clock for J784S4 Device

This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in J784S4 SoC.

TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.

Device wise clock ID list for J784S4 SoC

This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs

The following table describes functions implemented by clocks

Function	Description
Input clock	Clock input to the SoC subsystem
Output clock	Clock output from the SoC subsystem
Input muxed clock	Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source
Parent input clock option to XYZ	One of the parent clocks that can be used as a source clock to a input muxed clock

Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:

This device has no defined clocks.

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

Clocks for A72SS0 Device

Device: J784S4_DEV_A72SS0 (ID = 198)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS0_ARM0_CLK_CLK	Input clock
2	DEV_A72SS0_ARM0_DIVH_CLK8_OBSCLK_OUT_CLK	Output clock
3	DEV_A72SS0_ARM0_MSMC_CLK_CLK	Input clock
4	DEV_A72SS0_ARM0_PLL_CTRL_CLK_CLK	Input clock

Clocks for A72SS0_CORE0 Device

Device: J784S4_DEV_A72SS0_CORE0 (ID = 202)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS0_CORE0_ARM0_CLK_CLK	Input clock

Clocks for A72SS0_CORE1 Device

Device: J784S4_DEV_A72SS0_CORE1 (ID = 203)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS0_CORE1_ARM0_CLK_CLK	Input clock

Clocks for A72SS0_CORE2 Device

Device: J784S4_DEV_A72SS0_CORE2 (ID = 204)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS0_CORE2_ARM0_CLK_CLK	Input clock

Clocks for A72SS0_CORE3 Device

Device: J784S4_DEV_A72SS0_CORE3 (ID = 205)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS0_CORE3_ARM0_CLK_CLK	Input clock

Clocks for A72SS1 Device

Device: J784S4_DEV_A72SS1 (ID = 200)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS1_ARM1_CLK_CLK	Input clock
2	DEV_A72SS1_ARM1_DIVH_CLK8_OBSCLK_OUT_CLK	Output clock
6	DEV_A72SS1_ARM1_PLL_CTRL_CLK_CLK	Input clock

Clocks for A72SS1_CORE0 Device

Device: J784S4_DEV_A72SS1_CORE0 (ID = 206)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS1_CORE0_ARM1_CLK_CLK	Input clock

Clocks for A72SS1_CORE1 Device

Device: J784S4_DEV_A72SS1_CORE1 (ID = 207)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS1_CORE1_ARM1_CLK_CLK	Input clock

Clocks for A72SS1_CORE2 Device

Device: J784S4_DEV_A72SS1_CORE2 (ID = 208)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS1_CORE2_ARM1_CLK_CLK	Input clock

Clocks for A72SS1_CORE3 Device

Device: J784S4_DEV_A72SS1_CORE3 (ID = 209)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_A72SS1_CORE3_ARM1_CLK_CLK	Input clock

Clocks for ACSPCIE_BUFFER0 Device

Device: J784S4_DEV_ACSPCIE_BUFFER0 (ID = 415)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ACSPCIE_BUFFER0_CLKIN0	Input muxed clock
1	DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B8M4CT3_MAIN_0_REF_DER_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0
2	DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0
3	DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B8M4CT3_MAIN_0_REF_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0
4	DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B8M4CT3_MAIN_1_REF_DER_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0
5	DEV_ACSPCIE_BUFFER0_CLKIN1	Input muxed clock
6	DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B8M4CT3_MAIN_0_REF_DER_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1
7	DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1
8	DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B8M4CT3_MAIN_0_REF_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1
9	DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B8M4CT3_MAIN_1_REF_DER_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1
10	DEV_ACSPCIE_BUFFER0_PAD0_M	Output clock
11	DEV_ACSPCIE_BUFFER0_PAD0_P	Output clock
12	DEV_ACSPCIE_BUFFER0_PAD1_M	Output clock
13	DEV_ACSPCIE_BUFFER0_PAD1_P	Output clock

Clocks for ACSPCIE_BUFFER1 Device

Device: J784S4_DEV_ACSPCIE_BUFFER1 (ID = 416)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ACSPCIE_BUFFER1_CLKIN0	Input muxed clock
1	DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B8M4CT3_MAIN_1_REF_DER_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0
2	DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0
3	DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B8M4CT3_MAIN_1_REF_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0
5	DEV_ACSPCIE_BUFFER1_CLKIN1	Input muxed clock
6	DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B8M4CT3_MAIN_1_REF_DER_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1
7	DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1
8	DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B8M4CT3_MAIN_1_REF_OUT_CLK	Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1
10	DEV_ACSPCIE_BUFFER1_PAD0_M	Output clock
11	DEV_ACSPCIE_BUFFER1_PAD0_P	Output clock
12	DEV_ACSPCIE_BUFFER1_PAD1_M	Output clock
13	DEV_ACSPCIE_BUFFER1_PAD1_P	Output clock

Clocks for AGGR_ATB0 Device

Device: J784S4_DEV_AGGR_ATB0 (ID = 186)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_AGGR_ATB0_DBG_CLK	Input clock

Clocks for ATL0 Device

Device: J784S4_DEV_ATL0 (ID = 2)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ATL0_ATL_CLK	Input muxed clock
1	DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK	Parent input clock option to DEV_ATL0_ATL_CLK
2	DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_ATL0_ATL_CLK
5	DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK	Parent input clock option to DEV_ATL0_ATL_CLK
6	DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_CLK
7	DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_CLK
9	DEV_ATL0_ATL_IO_PORT_ATCLK_OUT	Output clock
10	DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1	Output clock
11	DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2	Output clock
12	DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3	Output clock
13	DEV_ATL0_ATL_IO_PORT_AWS	Input muxed clock
14	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
15	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
16	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
17	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
18	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
26	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
27	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
28	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
29	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
30	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
38	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
39	DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS
46	DEV_ATL0_ATL_IO_PORT_AWS_1	Input muxed clock
47	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
48	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
49	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
50	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
51	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
59	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
60	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
61	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
62	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
63	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
71	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
72	DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1
85	DEV_ATL0_ATL_IO_PORT_AWS_2	Input muxed clock
86	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
87	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
88	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
89	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
90	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
98	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
99	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
100	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
101	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
102	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
110	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
111	DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2
118	DEV_ATL0_ATL_IO_PORT_AWS_3	Input muxed clock
119	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
120	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
121	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
122	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
123	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
131	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
132	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
133	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
134	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
135	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
143	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
144	DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3
157	DEV_ATL0_ATL_IO_PORT_BWS	Input muxed clock
158	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
159	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
160	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
161	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
162	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
170	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
171	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
172	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
173	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
174	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
182	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
183	DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS
190	DEV_ATL0_ATL_IO_PORT_BWS_1	Input muxed clock
191	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
192	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
193	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
194	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
195	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
203	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
204	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
205	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
206	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
207	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
215	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
216	DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1
229	DEV_ATL0_ATL_IO_PORT_BWS_2	Input muxed clock
230	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
231	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
232	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
233	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
234	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
242	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
243	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
244	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
245	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
246	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
254	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
255	DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2
262	DEV_ATL0_ATL_IO_PORT_BWS_3	Input muxed clock
263	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
264	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
265	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
266	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
267	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
275	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
276	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
277	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
278	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
279	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
287	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
288	DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3
301	DEV_ATL0_VBUS_CLK	Input clock

Clocks for BOARD0 Device

Device: J784S4_DEV_BOARD0 (ID = 157)

Note

BOARD0 is a special device that represents the board on which the SoC is mounted.

Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.

Function documented here implies:

Function	Description
Input clock	Clock is supplied from SoC to the board (It is an output of the SoC)
Output clock	Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)

NOTE: Clocks which can be bi-directional are listed as Output clock

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN	Input muxed clock
1	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
2	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
3	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
4	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
5	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
13	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
14	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
15	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
16	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
17	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
25	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
26	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
27	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
28	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
29	DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
33	DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT	Output clock
34	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN	Input muxed clock
35	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
36	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
37	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
38	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
39	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
47	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
48	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
49	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
50	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
51	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
59	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
60	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
61	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
62	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
63	DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
67	DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT	Output clock
68	DEV_BOARD0_CPTS0_RFT_CLK_OUT	Output clock
69	DEV_BOARD0_CSI0_RXCLKN_OUT	Output clock
70	DEV_BOARD0_CSI0_RXCLKP_OUT	Output clock
71	DEV_BOARD0_CSI0_TXCLKN_IN	Input clock
72	DEV_BOARD0_CSI0_TXCLKP_IN	Input clock
73	DEV_BOARD0_CSI1_RXCLKN_OUT	Output clock
74	DEV_BOARD0_CSI1_RXCLKP_OUT	Output clock
75	DEV_BOARD0_CSI1_TXCLKN_IN	Input clock
76	DEV_BOARD0_CSI1_TXCLKP_IN	Input clock
77	DEV_BOARD0_CSI2_RXCLKN_OUT	Output clock
78	DEV_BOARD0_CSI2_RXCLKP_OUT	Output clock
95	DEV_BOARD0_DSI0_TXCLKN_IN	Input clock
96	DEV_BOARD0_DSI0_TXCLKP_IN	Input clock
97	DEV_BOARD0_DSI1_TXCLKN_IN	Input clock
98	DEV_BOARD0_DSI1_TXCLKP_IN	Input clock
99	DEV_BOARD0_EXT_REFCLK1_OUT	Output clock
100	DEV_BOARD0_GPMC0_CLKOUT_IN	Input clock
101	DEV_BOARD0_GPMC0_CLK_OUT	Output clock
102	DEV_BOARD0_GPMC0_FCLK_MUX_IN	Input clock
103	DEV_BOARD0_HYP0_RXFLCLK_IN	Input clock
104	DEV_BOARD0_HYP0_RXPMCLK_OUT	Output clock
105	DEV_BOARD0_HYP0_TXFLCLK_OUT	Output clock
106	DEV_BOARD0_HYP0_TXPMCLK_IN	Input clock
107	DEV_BOARD0_HYP1_RXFLCLK_IN	Input clock
108	DEV_BOARD0_HYP1_RXPMCLK_OUT	Output clock
109	DEV_BOARD0_HYP1_TXFLCLK_OUT	Output clock
110	DEV_BOARD0_HYP1_TXPMCLK_IN	Input clock
111	DEV_BOARD0_I2C0_SCL_IN	Input clock
112	DEV_BOARD0_I2C0_SCL_OUT	Output clock
113	DEV_BOARD0_I2C1_SCL_IN	Input clock
114	DEV_BOARD0_I2C1_SCL_OUT	Output clock
115	DEV_BOARD0_I2C2_SCL_IN	Input clock
116	DEV_BOARD0_I2C2_SCL_OUT	Output clock
117	DEV_BOARD0_I2C3_SCL_IN	Input clock
118	DEV_BOARD0_I2C3_SCL_OUT	Output clock
119	DEV_BOARD0_I2C4_SCL_IN	Input clock
120	DEV_BOARD0_I2C4_SCL_OUT	Output clock
121	DEV_BOARD0_I2C5_SCL_IN	Input clock
122	DEV_BOARD0_I2C5_SCL_OUT	Output clock
123	DEV_BOARD0_I2C6_SCL_IN	Input clock
124	DEV_BOARD0_I2C6_SCL_OUT	Output clock
125	DEV_BOARD0_LED_CLK_OUT	Output clock
126	DEV_BOARD0_MCAN0_RX_OUT	Output clock
127	DEV_BOARD0_MCAN10_RX_OUT	Output clock
128	DEV_BOARD0_MCAN11_RX_OUT	Output clock
129	DEV_BOARD0_MCAN12_RX_OUT	Output clock
130	DEV_BOARD0_MCAN13_RX_OUT	Output clock
131	DEV_BOARD0_MCAN14_RX_OUT	Output clock
132	DEV_BOARD0_MCAN15_RX_OUT	Output clock
133	DEV_BOARD0_MCAN16_RX_OUT	Output clock
134	DEV_BOARD0_MCAN17_RX_OUT	Output clock
135	DEV_BOARD0_MCAN1_RX_OUT	Output clock
136	DEV_BOARD0_MCAN2_RX_OUT	Output clock
137	DEV_BOARD0_MCAN3_RX_OUT	Output clock
138	DEV_BOARD0_MCAN4_RX_OUT	Output clock
139	DEV_BOARD0_MCAN5_RX_OUT	Output clock
140	DEV_BOARD0_MCAN6_RX_OUT	Output clock
141	DEV_BOARD0_MCAN7_RX_OUT	Output clock
142	DEV_BOARD0_MCAN8_RX_OUT	Output clock
143	DEV_BOARD0_MCAN9_RX_OUT	Output clock
144	DEV_BOARD0_MCASP0_ACLKR_IN	Input clock
145	DEV_BOARD0_MCASP0_ACLKR_OUT	Output clock
146	DEV_BOARD0_MCASP0_ACLKX_IN	Input clock
147	DEV_BOARD0_MCASP0_ACLKX_OUT	Output clock
148	DEV_BOARD0_MCASP0_AFSR_OUT	Output clock
149	DEV_BOARD0_MCASP0_AFSX_OUT	Output clock
150	DEV_BOARD0_MCASP1_ACLKR_IN	Input clock
151	DEV_BOARD0_MCASP1_ACLKR_OUT	Output clock
152	DEV_BOARD0_MCASP1_ACLKX_IN	Input clock
153	DEV_BOARD0_MCASP1_ACLKX_OUT	Output clock
154	DEV_BOARD0_MCASP1_AFSR_OUT	Output clock
155	DEV_BOARD0_MCASP1_AFSX_OUT	Output clock
156	DEV_BOARD0_MCASP2_ACLKR_IN	Input clock
157	DEV_BOARD0_MCASP2_ACLKR_OUT	Output clock
158	DEV_BOARD0_MCASP2_ACLKX_IN	Input clock
159	DEV_BOARD0_MCASP2_ACLKX_OUT	Output clock
160	DEV_BOARD0_MCASP2_AFSR_OUT	Output clock
161	DEV_BOARD0_MCASP2_AFSX_OUT	Output clock
162	DEV_BOARD0_MCASP3_ACLKR_IN	Input clock
163	DEV_BOARD0_MCASP3_ACLKR_OUT	Output clock
164	DEV_BOARD0_MCASP3_ACLKX_IN	Input clock
165	DEV_BOARD0_MCASP3_ACLKX_OUT	Output clock
166	DEV_BOARD0_MCASP3_AFSR_OUT	Output clock
167	DEV_BOARD0_MCASP3_AFSX_OUT	Output clock
168	DEV_BOARD0_MCASP4_ACLKR_IN	Input clock
169	DEV_BOARD0_MCASP4_ACLKR_OUT	Output clock
170	DEV_BOARD0_MCASP4_ACLKX_IN	Input clock
171	DEV_BOARD0_MCASP4_ACLKX_OUT	Output clock
172	DEV_BOARD0_MCASP4_AFSR_OUT	Output clock
173	DEV_BOARD0_MCASP4_AFSX_OUT	Output clock
174	DEV_BOARD0_MCU_CLKOUT0_IN	Input muxed clock
175	DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5	Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN
176	DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10	Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN
177	DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT	Output clock
178	DEV_BOARD0_MCU_EXT_REFCLK0_OUT	Output clock
179	DEV_BOARD0_MCU_HYPERBUS0_CK_IN	Input clock
180	DEV_BOARD0_MCU_HYPERBUS0_CKN_IN	Input clock
181	DEV_BOARD0_MCU_I2C0_SCL_IN	Input clock
182	DEV_BOARD0_MCU_I2C0_SCL_OUT	Output clock
183	DEV_BOARD0_MCU_I2C1_SCL_IN	Input clock
184	DEV_BOARD0_MCU_I2C1_SCL_OUT	Output clock
185	DEV_BOARD0_MCU_I3C0_SCL_IN	Input clock
186	DEV_BOARD0_MCU_I3C0_SCL_OUT	Output clock
187	DEV_BOARD0_MCU_I3C0_SDA_OUT	Output clock
188	DEV_BOARD0_MCU_MCAN0_RX_OUT	Output clock
189	DEV_BOARD0_MCU_MCAN1_RX_OUT	Output clock
190	DEV_BOARD0_MCU_MDIO0_MDC_IN	Input clock
191	DEV_BOARD0_MCU_OBSCLK0_IN	Input muxed clock
192	DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0	Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
193	DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
224	DEV_BOARD0_MCU_OSPI0_CLK_IN	Input clock
225	DEV_BOARD0_MCU_OSPI0_DQS_OUT	Output clock
226	DEV_BOARD0_MCU_OSPI0_LBCLKO_IN	Input clock
227	DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT	Output clock
228	DEV_BOARD0_MCU_OSPI1_CLK_IN	Input clock
229	DEV_BOARD0_MCU_OSPI1_DQS_OUT	Output clock
230	DEV_BOARD0_MCU_OSPI1_LBCLKO_IN	Input clock
231	DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT	Output clock
232	DEV_BOARD0_MCU_RGMII1_RXC_OUT	Output clock
233	DEV_BOARD0_MCU_RGMII1_TXC_IN	Input clock
234	DEV_BOARD0_MCU_RMII1_REF_CLK_OUT	Output clock
235	DEV_BOARD0_MCU_SPI0_CLK_IN	Input clock
236	DEV_BOARD0_MCU_SPI0_CLK_OUT	Output clock
237	DEV_BOARD0_MCU_SPI1_CLK_IN	Input clock
238	DEV_BOARD0_MCU_SPI1_CLK_OUT	Output clock
239	DEV_BOARD0_MCU_SYSCLKOUT0_IN	Input clock
240	DEV_BOARD0_MDIO0_MDC_IN	Input clock
241	DEV_BOARD0_MDIO1_MDC_IN	Input clock
243	DEV_BOARD0_MMC1_CLKLB_IN	Input clock
244	DEV_BOARD0_MMC1_CLKLB_OUT	Output clock
245	DEV_BOARD0_MMC1_CLK_IN	Input clock
246	DEV_BOARD0_MMC1_CLK_OUT	Output clock
247	DEV_BOARD0_OBSCLK0_IN	Input clock
248	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
249	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
250	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
251	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
252	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
253	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
254	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
255	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
256	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
257	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
260	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
261	DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
262	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
264	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
265	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
267	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
268	DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
269	DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
270	DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
273	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
274	DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
275	DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
276	DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
277	DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
278	DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
279	DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_BOARD0_OBSCLK0_IN
280	DEV_BOARD0_OBSCLK1_IN	Input clock
281	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
282	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
283	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
284	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
285	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
286	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
287	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
288	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
289	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
290	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
293	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
294	DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
295	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
297	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
298	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
300	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
301	DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
302	DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
303	DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
306	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
307	DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
308	DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
309	DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
310	DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
311	DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
312	DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_BOARD0_OBSCLK1_IN
313	DEV_BOARD0_PCIE_REFCLK0_N_OUT_IN	Input clock
314	DEV_BOARD0_PCIE_REFCLK0_P_OUT_IN	Input clock
315	DEV_BOARD0_PCIE_REFCLK1_N_OUT_IN	Input clock
316	DEV_BOARD0_PCIE_REFCLK1_P_OUT_IN	Input clock
317	DEV_BOARD0_PCIE_REFCLK2_N_OUT_IN	Input clock
318	DEV_BOARD0_PCIE_REFCLK2_P_OUT_IN	Input clock
319	DEV_BOARD0_PCIE_REFCLK3_N_OUT_IN	Input clock
320	DEV_BOARD0_PCIE_REFCLK3_P_OUT_IN	Input clock
321	DEV_BOARD0_RGMII1_RXC_OUT	Output clock
322	DEV_BOARD0_RGMII1_TXC_IN	Input clock
323	DEV_BOARD0_RMII_REF_CLK_OUT	Output clock
324	DEV_BOARD0_SERDES0_REFCLK_N_IN	Input clock
325	DEV_BOARD0_SERDES0_REFCLK_N_OUT	Output clock
326	DEV_BOARD0_SERDES0_REFCLK_P_IN	Input clock
327	DEV_BOARD0_SERDES0_REFCLK_P_OUT	Output clock
328	DEV_BOARD0_SERDES1_REFCLK_N_IN	Input clock
329	DEV_BOARD0_SERDES1_REFCLK_N_OUT	Output clock
330	DEV_BOARD0_SERDES1_REFCLK_P_IN	Input clock
331	DEV_BOARD0_SERDES1_REFCLK_P_OUT	Output clock
332	DEV_BOARD0_SERDES2_REFCLK_N_IN	Input clock
333	DEV_BOARD0_SERDES2_REFCLK_N_OUT	Output clock
334	DEV_BOARD0_SERDES2_REFCLK_P_IN	Input clock
335	DEV_BOARD0_SERDES2_REFCLK_P_OUT	Output clock
336	DEV_BOARD0_SERDES4_REFCLK_N_IN	Input clock
337	DEV_BOARD0_SERDES4_REFCLK_N_OUT	Output clock
338	DEV_BOARD0_SERDES4_REFCLK_P_IN	Input clock
339	DEV_BOARD0_SERDES4_REFCLK_P_OUT	Output clock
340	DEV_BOARD0_SPI0_CLK_IN	Input clock
341	DEV_BOARD0_SPI0_CLK_OUT	Output clock
342	DEV_BOARD0_SPI1_CLK_IN	Input clock
343	DEV_BOARD0_SPI1_CLK_OUT	Output clock
344	DEV_BOARD0_SPI2_CLK_IN	Input clock
345	DEV_BOARD0_SPI2_CLK_OUT	Output clock
346	DEV_BOARD0_SPI3_CLK_IN	Input clock
347	DEV_BOARD0_SPI3_CLK_OUT	Output clock
348	DEV_BOARD0_SPI5_CLK_IN	Input clock
349	DEV_BOARD0_SPI5_CLK_OUT	Output clock
350	DEV_BOARD0_SPI6_CLK_IN	Input clock
351	DEV_BOARD0_SPI6_CLK_OUT	Output clock
352	DEV_BOARD0_SPI7_CLK_IN	Input clock
353	DEV_BOARD0_SPI7_CLK_OUT	Output clock
354	DEV_BOARD0_SYSCLKOUT0_IN	Input clock
355	DEV_BOARD0_TCK_OUT	Output clock
356	DEV_BOARD0_TRC_CLK_IN	Input clock
357	DEV_BOARD0_UFS0_REF_CLK_IN	Input clock
358	DEV_BOARD0_VOUT0_EXTPCLKIN_OUT	Output clock
359	DEV_BOARD0_VOUT0_PCLK_IN	Input clock
360	DEV_BOARD0_WKUP_I2C0_SCL_IN	Input clock
361	DEV_BOARD0_WKUP_I2C0_SCL_OUT	Output clock
363	DEV_BOARD0_HFOSC1_CLK_OUT	Output clock

Clocks for C71X_0_PBIST_VD Device

This device has no defined clocks.

Clocks for C71X_1_PBIST_VD Device

This device has no defined clocks.

Clocks for CMPEVENT_INTRTR0 Device

Device: J784S4_DEV_CMPEVENT_INTRTR0 (ID = 11)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CMPEVENT_INTRTR0_INTR_CLK	Input clock

Clocks for CODEC0 Device

Device: J784S4_DEV_CODEC0 (ID = 241)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CODEC0_VPU_ACLK_CLK	Input clock
1	DEV_CODEC0_VPU_BCLK_CLK	Input clock
2	DEV_CODEC0_VPU_CCLK_CLK	Input clock
3	DEV_CODEC0_VPU_PCLK_CLK	Input clock

Clocks for CODEC1 Device

Device: J784S4_DEV_CODEC1 (ID = 242)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CODEC1_VPU_ACLK_CLK	Input clock
1	DEV_CODEC1_VPU_BCLK_CLK	Input clock
2	DEV_CODEC1_VPU_CCLK_CLK	Input clock
3	DEV_CODEC1_VPU_PCLK_CLK	Input clock

Clocks for COMPUTE_CLUSTER0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AC71_4_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AC71_5_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AC71_6_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AC71_7_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_1 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_1 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AW4_MSMC_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AW5_MSMC_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AW6_MSMC_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_AW7_MSMC_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_C71SS0 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS0 (ID = 30)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
3	DEV_COMPUTE_CLUSTER0_C71SS0_C7X_CLK	Input clock
4	DEV_COMPUTE_CLUSTER0_C71SS0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK	Output clock

Clocks for COMPUTE_CLUSTER0_C71SS0_CORE0 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS0_CORE0 (ID = 31)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_C7X_CLK	Input clock
2	DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_PLL_CTRL_CLK_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS0_MMA_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_C71SS1 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS1 (ID = 33)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
3	DEV_COMPUTE_CLUSTER0_C71SS1_C7X_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS1_CORE0 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS1_CORE0 (ID = 34)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_C7X_CLK	Input clock
2	DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_PLL_CTRL_CLK_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS1_MMA_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_C71SS2 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS2 (ID = 37)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
3	DEV_COMPUTE_CLUSTER0_C71SS2_C7X_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS2_CORE0 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS2_CORE0 (ID = 38)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER0_C71SS2_CORE0_C7X_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS2_MMA_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_C71SS3 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS3 (ID = 40)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
3	DEV_COMPUTE_CLUSTER0_C71SS3_C7X_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS3_CORE0 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_C71SS3_CORE0 (ID = 41)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER0_C71SS3_CORE0_C7X_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_C71SS3_MMA_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_CFG_WRAP_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_CLEC Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_CORE_CORE Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_CORE_CORE (ID = 45)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_1 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_2 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_3 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DEBUG_WRAP_0 Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0 (ID = 50)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK	Input clock
1	DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_DMSC_WRAP_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DRU0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DRU4 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DRU5 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DRU6 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DRU7 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_GIC500SS Device

Device: J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS (ID = 58)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK	Input clock

Clocks for COMPUTE_CLUSTER0_MSMC2_WRAP_0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_MSMC_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for CPSW1 Device

Device: J784S4_DEV_CPSW1 (ID = 62)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPSW1_CPPI_CLK_CLK	Input clock
1	DEV_CPSW1_CPTS_GENF0	Output clock
3	DEV_CPSW1_CPTS_RFT_CLK	Input muxed clock
4	DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
5	DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
6	DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
7	DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
8	DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
9	DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
10	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
11	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
12	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
13	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
14	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
15	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
16	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
17	DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
18	DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
19	DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK
20	DEV_CPSW1_GMII1_MR_CLK	Input clock
21	DEV_CPSW1_GMII1_MT_CLK	Input clock
22	DEV_CPSW1_GMII_RFT_CLK	Input clock
23	DEV_CPSW1_MDIO_MDCLK_O	Output clock
24	DEV_CPSW1_RGMII1_RXC_I	Input clock
26	DEV_CPSW1_RGMII1_TXC_O	Output clock
27	DEV_CPSW1_RGMII_MHZ_250_CLK	Input clock
28	DEV_CPSW1_RGMII_MHZ_50_CLK	Input clock
29	DEV_CPSW1_RGMII_MHZ_5_CLK	Input clock
30	DEV_CPSW1_RMII_MHZ_50_CLK	Input clock

Clocks for CPSW_9XUSS_J7AM0 Device

Device: J784S4_DEV_CPSW_9XUSS_J7AM0 (ID = 64)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPSW_9XUSS_J7AM0_CPPI_CLK_CLK	Input clock
1	DEV_CPSW_9XUSS_J7AM0_CPTS_GENF0	Output clock
3	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK	Input muxed clock
4	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
5	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
6	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
7	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
8	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
9	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
10	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
11	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
12	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
13	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
14	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
15	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
16	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
17	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
18	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
19	DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK
22	DEV_CPSW_9XUSS_J7AM0_GMII1_MR_CLK	Input clock
23	DEV_CPSW_9XUSS_J7AM0_GMII1_MT_CLK	Input clock
24	DEV_CPSW_9XUSS_J7AM0_GMII2_MR_CLK	Input clock
25	DEV_CPSW_9XUSS_J7AM0_GMII2_MT_CLK	Input clock
26	DEV_CPSW_9XUSS_J7AM0_GMII3_MR_CLK	Input clock
27	DEV_CPSW_9XUSS_J7AM0_GMII3_MT_CLK	Input clock
28	DEV_CPSW_9XUSS_J7AM0_GMII4_MR_CLK	Input clock
29	DEV_CPSW_9XUSS_J7AM0_GMII4_MT_CLK	Input clock
30	DEV_CPSW_9XUSS_J7AM0_GMII5_MR_CLK	Input clock
31	DEV_CPSW_9XUSS_J7AM0_GMII5_MT_CLK	Input clock
32	DEV_CPSW_9XUSS_J7AM0_GMII6_MR_CLK	Input clock
33	DEV_CPSW_9XUSS_J7AM0_GMII6_MT_CLK	Input clock
34	DEV_CPSW_9XUSS_J7AM0_GMII7_MR_CLK	Input clock
35	DEV_CPSW_9XUSS_J7AM0_GMII7_MT_CLK	Input clock
36	DEV_CPSW_9XUSS_J7AM0_GMII8_MR_CLK	Input clock
37	DEV_CPSW_9XUSS_J7AM0_GMII8_MT_CLK	Input clock
38	DEV_CPSW_9XUSS_J7AM0_GMII_RFT_CLK	Input clock
39	DEV_CPSW_9XUSS_J7AM0_MDIO_MDCLK_O	Output clock
56	DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK	Input clock
57	DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK	Input clock
58	DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK	Input clock
59	DEV_CPSW_9XUSS_J7AM0_RMII_MHZ_50_CLK	Input clock
60	DEV_CPSW_9XUSS_J7AM0_SERDES1_REFCLK	Input clock
61	DEV_CPSW_9XUSS_J7AM0_SERDES1_RXCLK	Input clock
62	DEV_CPSW_9XUSS_J7AM0_SERDES1_RXFCLK	Input clock
63	DEV_CPSW_9XUSS_J7AM0_SERDES1_TXCLK	Output clock
64	DEV_CPSW_9XUSS_J7AM0_SERDES1_TXFCLK	Input clock
65	DEV_CPSW_9XUSS_J7AM0_SERDES1_TXMCLK	Input clock
66	DEV_CPSW_9XUSS_J7AM0_SERDES2_REFCLK	Input clock
67	DEV_CPSW_9XUSS_J7AM0_SERDES2_RXCLK	Input clock
68	DEV_CPSW_9XUSS_J7AM0_SERDES2_RXFCLK	Input clock
69	DEV_CPSW_9XUSS_J7AM0_SERDES2_TXCLK	Output clock
70	DEV_CPSW_9XUSS_J7AM0_SERDES2_TXFCLK	Input clock
71	DEV_CPSW_9XUSS_J7AM0_SERDES2_TXMCLK	Input clock
72	DEV_CPSW_9XUSS_J7AM0_SERDES3_REFCLK	Input clock
73	DEV_CPSW_9XUSS_J7AM0_SERDES3_RXCLK	Input clock
74	DEV_CPSW_9XUSS_J7AM0_SERDES3_RXFCLK	Input clock
75	DEV_CPSW_9XUSS_J7AM0_SERDES3_TXCLK	Output clock
76	DEV_CPSW_9XUSS_J7AM0_SERDES3_TXFCLK	Input clock
77	DEV_CPSW_9XUSS_J7AM0_SERDES3_TXMCLK	Input clock
78	DEV_CPSW_9XUSS_J7AM0_SERDES4_REFCLK	Input clock
79	DEV_CPSW_9XUSS_J7AM0_SERDES4_RXCLK	Input clock
80	DEV_CPSW_9XUSS_J7AM0_SERDES4_RXFCLK	Input clock
81	DEV_CPSW_9XUSS_J7AM0_SERDES4_TXCLK	Output clock
82	DEV_CPSW_9XUSS_J7AM0_SERDES4_TXFCLK	Input clock
83	DEV_CPSW_9XUSS_J7AM0_SERDES4_TXMCLK	Input clock
84	DEV_CPSW_9XUSS_J7AM0_SERDES5_REFCLK	Input clock
85	DEV_CPSW_9XUSS_J7AM0_SERDES5_RXCLK	Input clock
86	DEV_CPSW_9XUSS_J7AM0_SERDES5_RXFCLK	Input clock
87	DEV_CPSW_9XUSS_J7AM0_SERDES5_TXCLK	Output clock
88	DEV_CPSW_9XUSS_J7AM0_SERDES5_TXFCLK	Input clock
89	DEV_CPSW_9XUSS_J7AM0_SERDES5_TXMCLK	Input clock
90	DEV_CPSW_9XUSS_J7AM0_SERDES6_REFCLK	Input clock
91	DEV_CPSW_9XUSS_J7AM0_SERDES6_RXCLK	Input clock
92	DEV_CPSW_9XUSS_J7AM0_SERDES6_RXFCLK	Input clock
93	DEV_CPSW_9XUSS_J7AM0_SERDES6_TXCLK	Output clock
94	DEV_CPSW_9XUSS_J7AM0_SERDES6_TXFCLK	Input clock
95	DEV_CPSW_9XUSS_J7AM0_SERDES6_TXMCLK	Input clock
96	DEV_CPSW_9XUSS_J7AM0_SERDES7_REFCLK	Input clock
97	DEV_CPSW_9XUSS_J7AM0_SERDES7_RXCLK	Input clock
98	DEV_CPSW_9XUSS_J7AM0_SERDES7_RXFCLK	Input clock
99	DEV_CPSW_9XUSS_J7AM0_SERDES7_TXCLK	Output clock
100	DEV_CPSW_9XUSS_J7AM0_SERDES7_TXFCLK	Input clock
101	DEV_CPSW_9XUSS_J7AM0_SERDES7_TXMCLK	Input clock
102	DEV_CPSW_9XUSS_J7AM0_SERDES8_REFCLK	Input clock
103	DEV_CPSW_9XUSS_J7AM0_SERDES8_RXCLK	Input clock
104	DEV_CPSW_9XUSS_J7AM0_SERDES8_RXFCLK	Input clock
105	DEV_CPSW_9XUSS_J7AM0_SERDES8_TXCLK	Output clock
106	DEV_CPSW_9XUSS_J7AM0_SERDES8_TXFCLK	Input clock
107	DEV_CPSW_9XUSS_J7AM0_SERDES8_TXMCLK	Input clock

Clocks for CPT2_AGGR0 Device

Device: J784S4_DEV_CPT2_AGGR0 (ID = 70)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR0_VCLK_CLK	Input clock

Clocks for CPT2_AGGR1 Device

Device: J784S4_DEV_CPT2_AGGR1 (ID = 65)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR1_VCLK_CLK	Input clock

Clocks for CPT2_AGGR2 Device

Device: J784S4_DEV_CPT2_AGGR2 (ID = 67)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR2_VCLK_CLK	Input clock

Clocks for CPT2_AGGR3 Device

Device: J784S4_DEV_CPT2_AGGR3 (ID = 69)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR3_VCLK_CLK	Input clock

Clocks for CPT2_AGGR4 Device

Device: J784S4_DEV_CPT2_AGGR4 (ID = 68)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR4_VCLK_CLK	Input clock

Clocks for CPT2_AGGR5 Device

Device: J784S4_DEV_CPT2_AGGR5 (ID = 66)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CPT2_AGGR5_VCLK_CLK	Input clock

Clocks for CSI_PSILSS0 Device

Device: J784S4_DEV_CSI_PSILSS0 (ID = 189)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CSI_PSILSS0_MAIN_CLK	Input clock

Clocks for CSI_RX_IF0 Device

Device: J784S4_DEV_CSI_RX_IF0 (ID = 72)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CSI_RX_IF0_MAIN_CLK_CLK	Input clock
1	DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC	Input clock
2	DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK	Input clock
3	DEV_CSI_RX_IF0_VBUS_CLK_CLK	Input clock
4	DEV_CSI_RX_IF0_VP_CLK_CLK	Input clock

Clocks for CSI_RX_IF1 Device

Device: J784S4_DEV_CSI_RX_IF1 (ID = 73)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CSI_RX_IF1_MAIN_CLK_CLK	Input clock
1	DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC	Input clock
2	DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK	Input clock
3	DEV_CSI_RX_IF1_VBUS_CLK_CLK	Input clock
4	DEV_CSI_RX_IF1_VP_CLK_CLK	Input clock

Clocks for CSI_RX_IF2 Device

Device: J784S4_DEV_CSI_RX_IF2 (ID = 74)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_CSI_RX_IF2_MAIN_CLK_CLK	Input clock
1	DEV_CSI_RX_IF2_PPI_D_RX_ULPS_ESC	Input clock
2	DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK	Input clock
3	DEV_CSI_RX_IF2_VBUS_CLK_CLK	Input clock
4	DEV_CSI_RX_IF2_VP_CLK_CLK	Input clock

Clocks for CSI_TX_IF0 Device

Device: J784S4_DEV_CSI_TX_IF0 (ID = 75)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK	Input clock
3	DEV_CSI_TX_IF0_ESC_CLK_CLK	Input clock
4	DEV_CSI_TX_IF0_MAIN_CLK_CLK	Input clock
5	DEV_CSI_TX_IF0_VBUS_CLK_CLK	Input clock

Clocks for CSI_TX_IF1 Device

Device: J784S4_DEV_CSI_TX_IF1 (ID = 76)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_CSI_TX_IF1_DPHY_TXBYTECLKHS_CL_CLK	Input clock
3	DEV_CSI_TX_IF1_ESC_CLK_CLK	Input clock
4	DEV_CSI_TX_IF1_MAIN_CLK_CLK	Input clock
5	DEV_CSI_TX_IF1_VBUS_CLK_CLK	Input clock

Clocks for DCC0 Device

Device: J784S4_DEV_DCC0 (ID = 78)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC0_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC0_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC0_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC0_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC0_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC0_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC0_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC0_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC0_DCC_INPUT00_CLK	Input clock
9	DEV_DCC0_DCC_INPUT01_CLK	Input clock
10	DEV_DCC0_DCC_INPUT02_CLK	Input clock
11	DEV_DCC0_DCC_INPUT10_CLK	Input clock
12	DEV_DCC0_VBUS_CLK	Input clock

Clocks for DCC1 Device

Device: J784S4_DEV_DCC1 (ID = 79)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC1_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC1_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC1_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC1_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC1_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC1_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC1_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC1_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC1_DCC_INPUT00_CLK	Input clock
9	DEV_DCC1_DCC_INPUT01_CLK	Input clock
10	DEV_DCC1_DCC_INPUT02_CLK	Input clock
11	DEV_DCC1_DCC_INPUT10_CLK	Input clock
12	DEV_DCC1_VBUS_CLK	Input clock

Clocks for DCC2 Device

Device: J784S4_DEV_DCC2 (ID = 80)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC2_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC2_DCC_CLKSRC1_CLK	Input clock
3	DEV_DCC2_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC2_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC2_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC2_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC2_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC2_DCC_INPUT00_CLK	Input clock
9	DEV_DCC2_DCC_INPUT01_CLK	Input clock
10	DEV_DCC2_DCC_INPUT02_CLK	Input clock
11	DEV_DCC2_DCC_INPUT10_CLK	Input clock
12	DEV_DCC2_VBUS_CLK	Input clock

Clocks for DCC3 Device

Device: J784S4_DEV_DCC3 (ID = 81)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC3_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC3_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC3_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC3_DCC_CLKSRC3_CLK	Input clock
5	DEV_DCC3_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC3_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC3_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC3_DCC_INPUT00_CLK	Input clock
9	DEV_DCC3_DCC_INPUT01_CLK	Input clock
10	DEV_DCC3_DCC_INPUT02_CLK	Input clock
11	DEV_DCC3_DCC_INPUT10_CLK	Input clock
12	DEV_DCC3_VBUS_CLK	Input clock

Clocks for DCC4 Device

Device: J784S4_DEV_DCC4 (ID = 82)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC4_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC4_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC4_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC4_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC4_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC4_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC4_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC4_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC4_DCC_INPUT00_CLK	Input clock
9	DEV_DCC4_DCC_INPUT01_CLK	Input clock
10	DEV_DCC4_DCC_INPUT02_CLK	Input clock
11	DEV_DCC4_DCC_INPUT10_CLK	Input clock
12	DEV_DCC4_VBUS_CLK	Input clock

Clocks for DCC5 Device

Device: J784S4_DEV_DCC5 (ID = 83)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_DCC5_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC5_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC5_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC5_DCC_CLKSRC4_CLK	Input clock
6	DEV_DCC5_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC5_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC5_DCC_INPUT00_CLK	Input clock
9	DEV_DCC5_DCC_INPUT01_CLK	Input clock
10	DEV_DCC5_DCC_INPUT02_CLK	Input clock
11	DEV_DCC5_DCC_INPUT10_CLK	Input clock
12	DEV_DCC5_VBUS_CLK	Input clock

Clocks for DCC6 Device

Device: J784S4_DEV_DCC6 (ID = 84)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC6_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC6_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC6_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC6_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC6_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC6_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC6_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC6_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC6_DCC_INPUT00_CLK	Input clock
9	DEV_DCC6_DCC_INPUT01_CLK	Input clock
10	DEV_DCC6_DCC_INPUT02_CLK	Input clock
11	DEV_DCC6_DCC_INPUT10_CLK	Input clock
12	DEV_DCC6_VBUS_CLK	Input clock

Clocks for DCC7 Device

Device: J784S4_DEV_DCC7 (ID = 85)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC7_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC7_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC7_DCC_CLKSRC2_CLK	Input clock
5	DEV_DCC7_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC7_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC7_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC7_DCC_INPUT00_CLK	Input clock
9	DEV_DCC7_DCC_INPUT01_CLK	Input clock
10	DEV_DCC7_DCC_INPUT02_CLK	Input clock
11	DEV_DCC7_DCC_INPUT10_CLK	Input clock
12	DEV_DCC7_VBUS_CLK	Input clock

Clocks for DCC8 Device

Device: J784S4_DEV_DCC8 (ID = 86)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC8_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC8_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC8_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC8_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC8_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC8_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC8_DCC_CLKSRC6_CLK	Input clock
7	DEV_DCC8_DCC_CLKSRC7_CLK	Input clock
8	DEV_DCC8_DCC_INPUT00_CLK	Input clock
9	DEV_DCC8_DCC_INPUT01_CLK	Input clock
10	DEV_DCC8_DCC_INPUT02_CLK	Input clock
11	DEV_DCC8_DCC_INPUT10_CLK	Input clock
12	DEV_DCC8_VBUS_CLK	Input clock

Clocks for DCC9 Device

Device: J784S4_DEV_DCC9 (ID = 87)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DCC9_DCC_CLKSRC0_CLK	Input clock
1	DEV_DCC9_DCC_CLKSRC1_CLK	Input clock
2	DEV_DCC9_DCC_CLKSRC2_CLK	Input clock
3	DEV_DCC9_DCC_CLKSRC3_CLK	Input clock
4	DEV_DCC9_DCC_CLKSRC4_CLK	Input clock
5	DEV_DCC9_DCC_CLKSRC5_CLK	Input clock
6	DEV_DCC9_DCC_CLKSRC6_CLK	Input clock
8	DEV_DCC9_DCC_INPUT00_CLK	Input clock
9	DEV_DCC9_DCC_INPUT01_CLK	Input clock
10	DEV_DCC9_DCC_INPUT02_CLK	Input clock
11	DEV_DCC9_DCC_INPUT10_CLK	Input clock
12	DEV_DCC9_VBUS_CLK	Input clock

Clocks for DDR0 Device

Device: J784S4_DEV_DDR0 (ID = 191)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DDR0_DDRSS_CFG_CLK	Input clock
1	DEV_DDR0_DDRSS_DDR_PLL_CLK	Input clock
4	DEV_DDR0_DDRSS_VBUS_CLK	Input clock
5	DEV_DDR0_PLL_CTRL_CLK	Input clock

Clocks for DDR1 Device

Device: J784S4_DEV_DDR1 (ID = 192)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DDR1_DDRSS_CFG_CLK	Input clock
1	DEV_DDR1_DDRSS_DDR_PLL_CLK	Input clock
4	DEV_DDR1_DDRSS_VBUS_CLK	Input clock
5	DEV_DDR1_PLL_CTRL_CLK	Input clock

Clocks for DDR2 Device

Device: J784S4_DEV_DDR2 (ID = 193)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DDR2_DDRSS_CFG_CLK	Input clock
1	DEV_DDR2_DDRSS_DDR_PLL_CLK	Input clock
4	DEV_DDR2_DDRSS_VBUS_CLK	Input clock
5	DEV_DDR2_PLL_CTRL_CLK	Input clock

Clocks for DDR3 Device

Device: J784S4_DEV_DDR3 (ID = 194)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DDR3_DDRSS_CFG_CLK	Input clock
1	DEV_DDR3_DDRSS_DDR_PLL_CLK	Input clock
4	DEV_DDR3_DDRSS_VBUS_CLK	Input clock
5	DEV_DDR3_PLL_CTRL_CLK	Input clock

Clocks for DEBUGSS_WRAP0 Device

Device: J784S4_DEV_DEBUGSS_WRAP0 (ID = 91)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DEBUGSS_WRAP0_ATB_CLK	Input clock
1	DEV_DEBUGSS_WRAP0_CORE_CLK	Input clock
2	DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK	Output clock
20	DEV_DEBUGSS_WRAP0_JTAG_TCK	Input clock
22	DEV_DEBUGSS_WRAP0_TREXPT_CLK	Input clock

Clocks for DEBUGSUSPENDRTR0 Device

Device: J784S4_DEV_DEBUGSUSPENDRTR0 (ID = 190)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DEBUGSUSPENDRTR0_INTR_CLK	Input clock

Clocks for DMPAC0 Device

Device: J784S4_DEV_DMPAC0 (ID = 92)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DMPAC0_CLK	Input clock

Clocks for DMPAC0_CTSET_0 Device

This device has no defined clocks.

Clocks for DMPAC0_INTD_0 Device

This device has no defined clocks.

Clocks for DMPAC0_SDE_0 Device

Device: J784S4_DEV_DMPAC0_SDE_0 (ID = 96)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DMPAC0_SDE_0_CLK	Input clock

Clocks for DMPAC0_UTC_0 Device

Device: J784S4_DEV_DMPAC0_UTC_0 (ID = 95)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK	Input clock

Clocks for DMPAC_VPAC_PSILSS0 Device

Device: J784S4_DEV_DMPAC_VPAC_PSILSS0 (ID = 195)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK	Input clock

Clocks for DPHY_RX0 Device

Device: J784S4_DEV_DPHY_RX0 (ID = 212)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_DPHY_RX0_IO_RX_CL_L_M	Input clock
3	DEV_DPHY_RX0_IO_RX_CL_L_P	Input clock
4	DEV_DPHY_RX0_JTAG_TCK	Input clock
5	DEV_DPHY_RX0_MAIN_CLK_CLK	Input clock
6	DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC	Output clock
7	DEV_DPHY_RX0_PPI_RX_BYTE_CLK	Output clock

Clocks for DPHY_RX1 Device

Device: J784S4_DEV_DPHY_RX1 (ID = 213)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_DPHY_RX1_IO_RX_CL_L_M	Input clock
3	DEV_DPHY_RX1_IO_RX_CL_L_P	Input clock
4	DEV_DPHY_RX1_JTAG_TCK	Input clock
5	DEV_DPHY_RX1_MAIN_CLK_CLK	Input clock
6	DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC	Output clock
7	DEV_DPHY_RX1_PPI_RX_BYTE_CLK	Output clock

Clocks for DPHY_RX2 Device

Device: J784S4_DEV_DPHY_RX2 (ID = 214)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_DPHY_RX2_IO_RX_CL_L_M	Input clock
3	DEV_DPHY_RX2_IO_RX_CL_L_P	Input clock
4	DEV_DPHY_RX2_JTAG_TCK	Input clock
5	DEV_DPHY_RX2_MAIN_CLK_CLK	Input clock
6	DEV_DPHY_RX2_PPI_D_RX_ULPS_ESC	Output clock
7	DEV_DPHY_RX2_PPI_RX_BYTE_CLK	Output clock

Clocks for DPHY_TX0 Device

Device: J784S4_DEV_DPHY_TX0 (ID = 402)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DPHY_TX0_CK_M	Output clock
1	DEV_DPHY_TX0_CK_P	Output clock
2	DEV_DPHY_TX0_CLK	Input clock
3	DEV_DPHY_TX0_DPHY_REF_CLK	Input muxed clock
4	DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK
5	DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK
6	DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK	Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK
7	DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK
8	DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK	Output clock
9	DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK	Input clock
10	DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK	Output clock
12	DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK	Input clock
13	DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK	Output clock
20	DEV_DPHY_TX0_PSM_CLK	Input clock
24	DEV_DPHY_TX0_TAP_TCK	Input clock

Clocks for DPHY_TX1 Device

Device: J784S4_DEV_DPHY_TX1 (ID = 403)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DPHY_TX1_CK_M	Output clock
1	DEV_DPHY_TX1_CK_P	Output clock
2	DEV_DPHY_TX1_CLK	Input clock
3	DEV_DPHY_TX1_DPHY_REF_CLK	Input muxed clock
4	DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK
5	DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK
6	DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK	Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK
7	DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK
8	DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK	Output clock
9	DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK	Input clock
10	DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK	Output clock
13	DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK	Output clock
20	DEV_DPHY_TX1_PSM_CLK	Input clock
24	DEV_DPHY_TX1_TAP_TCK	Input clock

Clocks for DSS0 Device

Device: J784S4_DEV_DSS0 (ID = 218)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DSS0_DSS_FUNC_CLK	Input clock
1	DEV_DSS0_DSS_INST0_DPI_0_IN_CLK	Input clock
2	DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK	Input muxed clock
3	DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK
4	DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK
5	DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK	Input muxed clock
6	DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK
7	DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK
8	DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK
9	DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK
10	DEV_DSS0_DSS_INST0_DPI_2_IN_CLK	Input muxed clock
11	DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK
12	DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK
13	DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK
14	DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK	Input muxed clock
15	DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK
16	DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK
17	DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK
18	DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK	Input muxed clock
19	DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK
20	DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK
21	DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK
22	DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK
23	DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0	Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK
24	DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK	Output clock
25	DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK	Output clock
26	DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK	Output clock
27	DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK	Output clock
28	DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK	Output clock
29	DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK	Output clock
30	DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK	Output clock

Clocks for DSS_DSI0 Device

Device: J784S4_DEV_DSS_DSI0 (ID = 215)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK	Input clock
1	DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK	Input clock
2	DEV_DSS_DSI0_DPI_0_CLK	Input clock
3	DEV_DSS_DSI0_PLL_CTRL_CLK	Input clock
4	DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK	Input clock
5	DEV_DSS_DSI0_SYS_CLK	Input clock

Clocks for DSS_DSI1 Device

Device: J784S4_DEV_DSS_DSI1 (ID = 216)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK	Input clock
1	DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK	Input clock
2	DEV_DSS_DSI1_DPI_0_CLK	Input clock
3	DEV_DSS_DSI1_PLL_CTRL_CLK	Input clock
4	DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK	Input clock
5	DEV_DSS_DSI1_SYS_CLK	Input clock

Clocks for DSS_EDP0 Device

Device: J784S4_DEV_DSS_EDP0 (ID = 217)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_DSS_EDP0_AIF_I2S_CLK	Input clock
6	DEV_DSS_EDP0_DPI_2_2X_CLK	Input clock
7	DEV_DSS_EDP0_DPI_2_CLK	Input clock
8	DEV_DSS_EDP0_DPI_3_CLK	Input clock
9	DEV_DSS_EDP0_DPI_4_CLK	Input clock
10	DEV_DSS_EDP0_DPI_5_CLK	Input clock
11	DEV_DSS_EDP0_DPTX_MOD_CLK	Input clock
12	DEV_DSS_EDP0_PHY_LN0_REFCLK	Input clock
13	DEV_DSS_EDP0_PHY_LN0_RXCLK	Input clock
14	DEV_DSS_EDP0_PHY_LN0_RXFCLK	Input clock
15	DEV_DSS_EDP0_PHY_LN0_TXCLK	Output clock
16	DEV_DSS_EDP0_PHY_LN0_TXFCLK	Input clock
17	DEV_DSS_EDP0_PHY_LN0_TXMCLK	Input clock
18	DEV_DSS_EDP0_PHY_LN1_REFCLK	Input clock
19	DEV_DSS_EDP0_PHY_LN1_RXCLK	Input clock
20	DEV_DSS_EDP0_PHY_LN1_RXFCLK	Input clock
21	DEV_DSS_EDP0_PHY_LN1_TXCLK	Output clock
22	DEV_DSS_EDP0_PHY_LN1_TXFCLK	Input clock
23	DEV_DSS_EDP0_PHY_LN1_TXMCLK	Input clock
24	DEV_DSS_EDP0_PHY_LN2_REFCLK	Input clock
25	DEV_DSS_EDP0_PHY_LN2_RXCLK	Input clock
26	DEV_DSS_EDP0_PHY_LN2_RXFCLK	Input clock
27	DEV_DSS_EDP0_PHY_LN2_TXCLK	Output clock
28	DEV_DSS_EDP0_PHY_LN2_TXFCLK	Input clock
29	DEV_DSS_EDP0_PHY_LN2_TXMCLK	Input clock
30	DEV_DSS_EDP0_PHY_LN3_REFCLK	Input clock
31	DEV_DSS_EDP0_PHY_LN3_RXCLK	Input clock
32	DEV_DSS_EDP0_PHY_LN3_RXFCLK	Input clock
33	DEV_DSS_EDP0_PHY_LN3_TXCLK	Output clock
34	DEV_DSS_EDP0_PHY_LN3_TXFCLK	Input clock
35	DEV_DSS_EDP0_PHY_LN3_TXMCLK	Input clock
36	DEV_DSS_EDP0_PLL_CTRL_CLK	Input clock

Clocks for ECAP0 Device

Device: J784S4_DEV_ECAP0 (ID = 126)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECAP0_VBUS_CLK	Input clock

Clocks for ECAP1 Device

Device: J784S4_DEV_ECAP1 (ID = 127)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECAP1_VBUS_CLK	Input clock

Clocks for ECAP2 Device

Device: J784S4_DEV_ECAP2 (ID = 128)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ECAP2_VBUS_CLK	Input clock

Clocks for ELM0 Device

Device: J784S4_DEV_ELM0 (ID = 130)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ELM0_VBUSP_CLK	Input clock

Clocks for EMIF_DATA_0_VD Device

This device has no defined clocks.

Clocks for EMIF_DATA_1_VD Device

This device has no defined clocks.

Clocks for EMIF_DATA_2_VD Device

This device has no defined clocks.

Clocks for EMIF_DATA_3_VD Device

This device has no defined clocks.

Clocks for EPWM0 Device

Device: J784S4_DEV_EPWM0 (ID = 219)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EPWM0_VBUSP_CLK	Input clock

Clocks for EPWM1 Device

Device: J784S4_DEV_EPWM1 (ID = 220)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EPWM1_VBUSP_CLK	Input clock

Clocks for EPWM2 Device

Device: J784S4_DEV_EPWM2 (ID = 221)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EPWM2_VBUSP_CLK	Input clock

Clocks for EPWM3 Device

Device: J784S4_DEV_EPWM3 (ID = 222)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EPWM3_VBUSP_CLK	Input clock

Clocks for EPWM4 Device

Device: J784S4_DEV_EPWM4 (ID = 223)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EPWM4_VBUSP_CLK	Input clock

Clocks for EPWM5 Device

Device: J784S4_DEV_EPWM5 (ID = 224)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EPWM5_VBUSP_CLK	Input clock

Clocks for EQEP0 Device

Device: J784S4_DEV_EQEP0 (ID = 142)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EQEP0_VBUS_CLK	Input clock

Clocks for EQEP1 Device

Device: J784S4_DEV_EQEP1 (ID = 143)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EQEP1_VBUS_CLK	Input clock

Clocks for EQEP2 Device

Device: J784S4_DEV_EQEP2 (ID = 144)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_EQEP2_VBUS_CLK	Input clock

Clocks for ESM0 Device

Device: J784S4_DEV_ESM0 (ID = 145)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_ESM0_CLK	Input clock

Clocks for FFI_MAIN_AC_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_AC_QM_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_HC_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_INFRA_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_IP_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_RC_CBASS_VD Device

This device has no defined clocks.

Clocks for GPIO0 Device

Device: J784S4_DEV_GPIO0 (ID = 163)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIO0_MMR_CLK	Input clock

Clocks for GPIO2 Device

Device: J784S4_DEV_GPIO2 (ID = 164)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIO2_MMR_CLK	Input clock

Clocks for GPIO4 Device

Device: J784S4_DEV_GPIO4 (ID = 165)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIO4_MMR_CLK	Input clock

Clocks for GPIO6 Device

Device: J784S4_DEV_GPIO6 (ID = 166)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIO6_MMR_CLK	Input clock

Clocks for GPIOMUX_INTRTR0 Device

Device: J784S4_DEV_GPIOMUX_INTRTR0 (ID = 10)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPIOMUX_INTRTR0_INTR_CLK	Input clock

Clocks for GPMC0 Device

Device: J784S4_DEV_GPMC0 (ID = 169)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GPMC0_FUNC_CLK	Input muxed clock
1	DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK	Parent input clock option to DEV_GPMC0_FUNC_CLK
2	DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6	Parent input clock option to DEV_GPMC0_FUNC_CLK
3	DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4	Parent input clock option to DEV_GPMC0_FUNC_CLK
4	DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4	Parent input clock option to DEV_GPMC0_FUNC_CLK
5	DEV_GPMC0_PI_GPMC_RET_CLK	Input clock
6	DEV_GPMC0_PO_GPMC_DEV_CLK	Output clock
7	DEV_GPMC0_VBUSM_CLK	Input clock

Clocks for GTC0 Device

Device: J784S4_DEV_GTC0 (ID = 61)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_GTC0_GTC_CLK	Input muxed clock
1	DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_GTC0_GTC_CLK
2	DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_GTC0_GTC_CLK
3	DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_GTC0_GTC_CLK
4	DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_GTC0_GTC_CLK
5	DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_GTC0_GTC_CLK
6	DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_GTC0_GTC_CLK
7	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
8	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
9	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
10	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
11	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
12	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
13	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
14	DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_GTC0_GTC_CLK
15	DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_GTC0_GTC_CLK
16	DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_GTC0_GTC_CLK
17	DEV_GTC0_VBUSP_CLK	Input clock

Clocks for I2C0 Device

Device: J784S4_DEV_I2C0 (ID = 270)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C0_CLK	Input clock
1	DEV_I2C0_PISCL	Input clock
2	DEV_I2C0_PISYS_CLK	Input clock
3	DEV_I2C0_PORSCL	Output clock

Clocks for I2C1 Device

Device: J784S4_DEV_I2C1 (ID = 271)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C1_CLK	Input clock
1	DEV_I2C1_PISCL	Input clock
2	DEV_I2C1_PISYS_CLK	Input clock
3	DEV_I2C1_PORSCL	Output clock

Clocks for I2C2 Device

Device: J784S4_DEV_I2C2 (ID = 272)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C2_CLK	Input clock
1	DEV_I2C2_PISCL	Input clock
2	DEV_I2C2_PISYS_CLK	Input clock
3	DEV_I2C2_PORSCL	Output clock

Clocks for I2C3 Device

Device: J784S4_DEV_I2C3 (ID = 273)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C3_CLK	Input clock
1	DEV_I2C3_PISCL	Input clock
2	DEV_I2C3_PISYS_CLK	Input clock
3	DEV_I2C3_PORSCL	Output clock

Clocks for I2C4 Device

Device: J784S4_DEV_I2C4 (ID = 274)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C4_CLK	Input clock
1	DEV_I2C4_PISCL	Input clock
2	DEV_I2C4_PISYS_CLK	Input clock
3	DEV_I2C4_PORSCL	Output clock

Clocks for I2C5 Device

Device: J784S4_DEV_I2C5 (ID = 275)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C5_CLK	Input clock
1	DEV_I2C5_PISCL	Input clock
2	DEV_I2C5_PISYS_CLK	Input clock
3	DEV_I2C5_PORSCL	Output clock

Clocks for I2C6 Device

Device: J784S4_DEV_I2C6 (ID = 276)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_I2C6_CLK	Input clock
1	DEV_I2C6_PISCL	Input clock
2	DEV_I2C6_PISYS_CLK	Input clock
3	DEV_I2C6_PORSCL	Output clock

Clocks for J7AEP_GPU_BXS464_WRAP0 Device

This device has no defined clocks.

Clocks for J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0 Device

This device has no defined clocks.

Clocks for J7AEP_GPU_BXS464_WRAP0_GPUCORE_0 Device

This device has no defined clocks.

Clocks for J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 Device

Device: J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 (ID = 181)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK	Input clock
4	DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK	Input clock

Clocks for J7AM_32_64_ATB_FUNNEL0 Device

Device: J784S4_DEV_J7AM_32_64_ATB_FUNNEL0 (ID = 183)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK	Input clock

Clocks for J7AM_32_64_ATB_FUNNEL1 Device

Device: J784S4_DEV_J7AM_32_64_ATB_FUNNEL1 (ID = 184)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK	Input clock

Clocks for J7AM_32_64_ATB_FUNNEL2 Device

Device: J784S4_DEV_J7AM_32_64_ATB_FUNNEL2 (ID = 185)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK	Input clock

Clocks for J7AM_BOLT_PGD0 Device

Device: J784S4_DEV_J7AM_BOLT_PGD0 (ID = 187)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK	Input clock

Clocks for J7AM_BOLT_PSC_WRAP0 Device

Device: J784S4_DEV_J7AM_BOLT_PSC_WRAP0 (ID = 188)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_BOLT_PSC_WRAP0_CLK	Input clock
1	DEV_J7AM_BOLT_PSC_WRAP0_SLOW_CLK	Input clock

Clocks for J7AM_HWA_ATB_FUNNEL0 Device

Device: J784S4_DEV_J7AM_HWA_ATB_FUNNEL0 (ID = 197)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK	Input clock

Clocks for J7AM_MAIN_16FF0 Device

Device: J784S4_DEV_J7AM_MAIN_16FF0 (ID = 199)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK	Input clock

Clocks for J7AM_PULSAR_ATB_FUNNEL0 Device

Device: J784S4_DEV_J7AM_PULSAR_ATB_FUNNEL0 (ID = 7)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK	Input clock

Clocks for LED0 Device

Device: J784S4_DEV_LED0 (ID = 172)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_LED0_LED_CLK	Input clock
1	DEV_LED0_VBUS_CLK	Input clock

Clocks for MAIN2MCU_LVL_INTRTR0 Device

Device: J784S4_DEV_MAIN2MCU_LVL_INTRTR0 (ID = 173)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK	Input clock

Clocks for MAIN2MCU_PLS_INTRTR0 Device

Device: J784S4_DEV_MAIN2MCU_PLS_INTRTR0 (ID = 174)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK	Input clock

Clocks for MAIN2WKUPMCU_VD Device

This device has no defined clocks.

Clocks for MAIN_PLL8_SEL_EXTWAVE_VD Device

Device: J784S4_DEV_MAIN_PLL8_SEL_EXTWAVE_VD (ID = 432)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK	Input muxed clock
1	DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_PLLFRACF2_SSMOD_16FFT_MAIN_8_FOUTVCOP_CLK	Parent input clock option to DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK
2	DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK	Parent input clock option to DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK

Clocks for MAIN_PLL9_SEL_EXTWAVE_VD Device

Device: J784S4_DEV_MAIN_PLL9_SEL_EXTWAVE_VD (ID = 433)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MAIN_PLL9_SEL_EXTWAVE_VD_CLK	Input muxed clock
1	DEV_MAIN_PLL9_SEL_EXTWAVE_VD_CLK_PARENT_PLLFRACF2_SSMOD_16FFT_MAIN_9_FOUTVCOP_CLK	Parent input clock option to DEV_MAIN_PLL9_SEL_EXTWAVE_VD_CLK
2	DEV_MAIN_PLL9_SEL_EXTWAVE_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_9_HSDIVOUT0_CLK	Parent input clock option to DEV_MAIN_PLL9_SEL_EXTWAVE_VD_CLK

Clocks for MCAN0 Device

Device: J784S4_DEV_MCAN0 (ID = 245)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN0_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN0_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
3	DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
4	DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
5	DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
6	DEV_MCAN0_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN1 Device

Device: J784S4_DEV_MCAN1 (ID = 246)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN1_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN1_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
3	DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
4	DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
5	DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
6	DEV_MCAN1_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN10 Device

Device: J784S4_DEV_MCAN10 (ID = 255)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN10_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN10_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
3	DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
4	DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
5	DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
6	DEV_MCAN10_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN11 Device

Device: J784S4_DEV_MCAN11 (ID = 256)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN11_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN11_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
3	DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
4	DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
5	DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
6	DEV_MCAN11_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN12 Device

Device: J784S4_DEV_MCAN12 (ID = 257)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN12_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN12_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
3	DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
4	DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
5	DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
6	DEV_MCAN12_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN13 Device

Device: J784S4_DEV_MCAN13 (ID = 258)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN13_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN13_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
3	DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
4	DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
5	DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
6	DEV_MCAN13_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN14 Device

Device: J784S4_DEV_MCAN14 (ID = 259)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN14_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN14_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
3	DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
4	DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
5	DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
6	DEV_MCAN14_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN15 Device

Device: J784S4_DEV_MCAN15 (ID = 260)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN15_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN15_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
3	DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
4	DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
5	DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
6	DEV_MCAN15_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN16 Device

Device: J784S4_DEV_MCAN16 (ID = 261)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN16_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN16_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
3	DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
4	DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
5	DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
6	DEV_MCAN16_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN17 Device

Device: J784S4_DEV_MCAN17 (ID = 262)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN17_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN17_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
3	DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
4	DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
5	DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
6	DEV_MCAN17_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN2 Device

Device: J784S4_DEV_MCAN2 (ID = 247)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN2_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN2_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
3	DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
4	DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
5	DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
6	DEV_MCAN2_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN3 Device

Device: J784S4_DEV_MCAN3 (ID = 248)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN3_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN3_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
3	DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
4	DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
5	DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
6	DEV_MCAN3_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN4 Device

Device: J784S4_DEV_MCAN4 (ID = 249)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN4_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN4_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
3	DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
4	DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
5	DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
6	DEV_MCAN4_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN5 Device

Device: J784S4_DEV_MCAN5 (ID = 250)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN5_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN5_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
3	DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
4	DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
5	DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
6	DEV_MCAN5_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN6 Device

Device: J784S4_DEV_MCAN6 (ID = 251)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN6_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN6_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
3	DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
4	DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
5	DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
6	DEV_MCAN6_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN7 Device

Device: J784S4_DEV_MCAN7 (ID = 252)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN7_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN7_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
3	DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
4	DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
5	DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
6	DEV_MCAN7_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN8 Device

Device: J784S4_DEV_MCAN8 (ID = 253)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN8_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN8_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
3	DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
4	DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
5	DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
6	DEV_MCAN8_MCANSS_HCLK_CLK	Input clock

Clocks for MCAN9 Device

Device: J784S4_DEV_MCAN9 (ID = 254)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCAN9_MCANSS_CAN_RXD	Input clock
1	DEV_MCAN9_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK	Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
3	DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
4	DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
5	DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
6	DEV_MCAN9_MCANSS_HCLK_CLK	Input clock

Clocks for MCASP0 Device

Device: J784S4_DEV_MCASP0 (ID = 265)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP0_AUX_CLK	Input muxed clock
1	DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_MCASP0_AUX_CLK
2	DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCASP0_AUX_CLK
5	DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP0_AUX_CLK
6	DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP0_AUX_CLK
7	DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP0_AUX_CLK
8	DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP0_AUX_CLK
9	DEV_MCASP0_MCASP_ACLKR_PIN	Input clock
10	DEV_MCASP0_MCASP_ACLKR_POUT	Output clock
11	DEV_MCASP0_MCASP_ACLKX_PIN	Input clock
12	DEV_MCASP0_MCASP_ACLKX_POUT	Output clock
13	DEV_MCASP0_MCASP_AFSR_POUT	Output clock
14	DEV_MCASP0_MCASP_AFSX_POUT	Output clock
15	DEV_MCASP0_MCASP_AHCLKR_PIN	Input muxed clock
16	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
17	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
18	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
19	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
24	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
25	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
26	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
27	DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
32	DEV_MCASP0_MCASP_AHCLKR_POUT	Output clock
33	DEV_MCASP0_MCASP_AHCLKX_PIN	Input muxed clock
34	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
35	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
36	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
37	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
42	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
43	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
44	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
45	DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
50	DEV_MCASP0_MCASP_AHCLKX_POUT	Output clock
51	DEV_MCASP0_VBUSP_CLK	Input clock

Clocks for MCASP1 Device

Device: J784S4_DEV_MCASP1 (ID = 266)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP1_AUX_CLK	Input muxed clock
1	DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_MCASP1_AUX_CLK
2	DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCASP1_AUX_CLK
5	DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP1_AUX_CLK
6	DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP1_AUX_CLK
7	DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP1_AUX_CLK
8	DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP1_AUX_CLK
9	DEV_MCASP1_MCASP_ACLKR_PIN	Input clock
10	DEV_MCASP1_MCASP_ACLKR_POUT	Output clock
11	DEV_MCASP1_MCASP_ACLKX_PIN	Input clock
12	DEV_MCASP1_MCASP_ACLKX_POUT	Output clock
13	DEV_MCASP1_MCASP_AFSR_POUT	Output clock
14	DEV_MCASP1_MCASP_AFSX_POUT	Output clock
15	DEV_MCASP1_MCASP_AHCLKR_PIN	Input muxed clock
16	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
17	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
18	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
19	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
24	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
25	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
26	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
27	DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
32	DEV_MCASP1_MCASP_AHCLKR_POUT	Output clock
33	DEV_MCASP1_MCASP_AHCLKX_PIN	Input muxed clock
34	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
35	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
36	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
37	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
42	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
43	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
44	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
45	DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
50	DEV_MCASP1_MCASP_AHCLKX_POUT	Output clock
51	DEV_MCASP1_VBUSP_CLK	Input clock

Clocks for MCASP2 Device

Device: J784S4_DEV_MCASP2 (ID = 267)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP2_AUX_CLK	Input muxed clock
1	DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_MCASP2_AUX_CLK
2	DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCASP2_AUX_CLK
5	DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP2_AUX_CLK
6	DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP2_AUX_CLK
7	DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP2_AUX_CLK
8	DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP2_AUX_CLK
9	DEV_MCASP2_MCASP_ACLKR_PIN	Input clock
10	DEV_MCASP2_MCASP_ACLKR_POUT	Output clock
11	DEV_MCASP2_MCASP_ACLKX_PIN	Input clock
12	DEV_MCASP2_MCASP_ACLKX_POUT	Output clock
13	DEV_MCASP2_MCASP_AFSR_POUT	Output clock
14	DEV_MCASP2_MCASP_AFSX_POUT	Output clock
15	DEV_MCASP2_MCASP_AHCLKR_PIN	Input muxed clock
16	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
17	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
18	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
19	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
24	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
25	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
26	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
27	DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
32	DEV_MCASP2_MCASP_AHCLKR_POUT	Output clock
33	DEV_MCASP2_MCASP_AHCLKX_PIN	Input muxed clock
34	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
35	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
36	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
37	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
42	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
43	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
44	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
45	DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
50	DEV_MCASP2_MCASP_AHCLKX_POUT	Output clock
51	DEV_MCASP2_VBUSP_CLK	Input clock

Clocks for MCASP3 Device

Device: J784S4_DEV_MCASP3 (ID = 268)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP3_AUX_CLK	Input muxed clock
1	DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_MCASP3_AUX_CLK
2	DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCASP3_AUX_CLK
5	DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP3_AUX_CLK
6	DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP3_AUX_CLK
7	DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP3_AUX_CLK
8	DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP3_AUX_CLK
9	DEV_MCASP3_MCASP_ACLKR_PIN	Input clock
10	DEV_MCASP3_MCASP_ACLKR_POUT	Output clock
11	DEV_MCASP3_MCASP_ACLKX_PIN	Input clock
12	DEV_MCASP3_MCASP_ACLKX_POUT	Output clock
13	DEV_MCASP3_MCASP_AFSR_POUT	Output clock
14	DEV_MCASP3_MCASP_AFSX_POUT	Output clock
15	DEV_MCASP3_MCASP_AHCLKR_PIN	Input muxed clock
16	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
17	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
18	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
19	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
24	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
25	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
26	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
27	DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN
32	DEV_MCASP3_MCASP_AHCLKR_POUT	Output clock
33	DEV_MCASP3_MCASP_AHCLKX_PIN	Input muxed clock
34	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
35	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
36	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
37	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
42	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
43	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
44	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
45	DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN
50	DEV_MCASP3_MCASP_AHCLKX_POUT	Output clock
51	DEV_MCASP3_VBUSP_CLK	Input clock

Clocks for MCASP4 Device

Device: J784S4_DEV_MCASP4 (ID = 269)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCASP4_AUX_CLK	Input muxed clock
1	DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK	Parent input clock option to DEV_MCASP4_AUX_CLK
2	DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCASP4_AUX_CLK
5	DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP4_AUX_CLK
6	DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP4_AUX_CLK
7	DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP4_AUX_CLK
8	DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP4_AUX_CLK
9	DEV_MCASP4_MCASP_ACLKR_PIN	Input clock
10	DEV_MCASP4_MCASP_ACLKR_POUT	Output clock
11	DEV_MCASP4_MCASP_ACLKX_PIN	Input clock
12	DEV_MCASP4_MCASP_ACLKX_POUT	Output clock
13	DEV_MCASP4_MCASP_AFSR_POUT	Output clock
14	DEV_MCASP4_MCASP_AFSX_POUT	Output clock
15	DEV_MCASP4_MCASP_AHCLKR_PIN	Input muxed clock
16	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
17	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
18	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
19	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
24	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
25	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
26	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
27	DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN
32	DEV_MCASP4_MCASP_AHCLKR_POUT	Output clock
33	DEV_MCASP4_MCASP_AHCLKX_PIN	Input muxed clock
34	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
35	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
36	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
37	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
42	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
43	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
44	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
45	DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3	Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN
50	DEV_MCASP4_MCASP_AHCLKX_POUT	Output clock
51	DEV_MCASP4_VBUSP_CLK	Input clock

Clocks for MCSPI0 Device

Device: J784S4_DEV_MCSPI0 (ID = 376)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI0_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI0_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT	Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK
3	DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK
4	DEV_MCSPI0_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI0_VBUSP_CLK	Input clock

Clocks for MCSPI1 Device

Device: J784S4_DEV_MCSPI1 (ID = 377)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI1_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI1_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT	Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK
3	DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK
4	DEV_MCSPI1_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI1_VBUSP_CLK	Input clock

Clocks for MCSPI2 Device

Device: J784S4_DEV_MCSPI2 (ID = 378)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI2_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI2_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT	Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK
3	DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK
4	DEV_MCSPI2_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI2_VBUSP_CLK	Input clock

Clocks for MCSPI3 Device

Device: J784S4_DEV_MCSPI3 (ID = 379)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI3_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI3_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK
3	DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0	Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK
4	DEV_MCSPI3_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI3_VBUSP_CLK	Input clock

Clocks for MCSPI4 Device

Device: J784S4_DEV_MCSPI4 (ID = 380)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI4_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI4_IO_CLKSPII_CLK	Input clock
2	DEV_MCSPI4_IO_CLKSPIO_CLK	Output clock
3	DEV_MCSPI4_VBUSP_CLK	Input clock

Clocks for MCSPI5 Device

Device: J784S4_DEV_MCSPI5 (ID = 381)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI5_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI5_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT	Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK
3	DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK
4	DEV_MCSPI5_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI5_VBUSP_CLK	Input clock

Clocks for MCSPI6 Device

Device: J784S4_DEV_MCSPI6 (ID = 382)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI6_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI6_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT	Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK
3	DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK
4	DEV_MCSPI6_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI6_VBUSP_CLK	Input clock

Clocks for MCSPI7 Device

Device: J784S4_DEV_MCSPI7 (ID = 383)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCSPI7_CLKSPIREF_CLK	Input clock
1	DEV_MCSPI7_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT	Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK
3	DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK
4	DEV_MCSPI7_IO_CLKSPIO_CLK	Output clock
5	DEV_MCSPI7_VBUSP_CLK	Input clock

Clocks for MCU_ADC12FC_16FFC0 Device

Device: J784S4_DEV_MCU_ADC12FC_16FFC0 (ID = 0)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ADC12FC_16FFC0_ADC_CLK	Input muxed clock
1	DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK
2	DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK	Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK
3	DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK	Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK
4	DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK
5	DEV_MCU_ADC12FC_16FFC0_SYS_CLK	Input clock
6	DEV_MCU_ADC12FC_16FFC0_VBUS_CLK	Input clock

Clocks for MCU_ADC12FC_16FFC1 Device

Device: J784S4_DEV_MCU_ADC12FC_16FFC1 (ID = 1)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ADC12FC_16FFC1_ADC_CLK	Input muxed clock
1	DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK
2	DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK	Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK
3	DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK	Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK
4	DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK
5	DEV_MCU_ADC12FC_16FFC1_SYS_CLK	Input clock
6	DEV_MCU_ADC12FC_16FFC1_VBUS_CLK	Input clock

Clocks for MCU_CPSW0 Device

Device: J784S4_DEV_MCU_CPSW0 (ID = 63)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CPSW0_CPPI_CLK_CLK	Input clock
1	DEV_MCU_CPSW0_CPTS_GENF0	Output clock
3	DEV_MCU_CPSW0_CPTS_RFT_CLK	Input muxed clock
4	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
5	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
6	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
7	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
8	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
9	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
10	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
11	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
12	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
13	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
14	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
15	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
16	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
17	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
18	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
19	DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2	Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
20	DEV_MCU_CPSW0_GMII1_MR_CLK	Input clock
21	DEV_MCU_CPSW0_GMII1_MT_CLK	Input clock
22	DEV_MCU_CPSW0_GMII_RFT_CLK	Input clock
23	DEV_MCU_CPSW0_MDIO_MDCLK_O	Output clock
24	DEV_MCU_CPSW0_RGMII1_RXC_I	Input clock
26	DEV_MCU_CPSW0_RGMII1_TXC_O	Output clock
27	DEV_MCU_CPSW0_RGMII_MHZ_250_CLK	Input clock
28	DEV_MCU_CPSW0_RGMII_MHZ_50_CLK	Input clock
29	DEV_MCU_CPSW0_RGMII_MHZ_5_CLK	Input clock
30	DEV_MCU_CPSW0_RMII_MHZ_50_CLK	Input clock

Clocks for MCU_CPT2_AGGR0 Device

Device: J784S4_DEV_MCU_CPT2_AGGR0 (ID = 71)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_CPT2_AGGR0_VCLK_CLK	Input clock

Clocks for MCU_DCC0 Device

Device: J784S4_DEV_MCU_DCC0 (ID = 88)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DCC0_DCC_CLKSRC0_CLK	Input clock
1	DEV_MCU_DCC0_DCC_CLKSRC1_CLK	Input clock
2	DEV_MCU_DCC0_DCC_CLKSRC2_CLK	Input clock
3	DEV_MCU_DCC0_DCC_CLKSRC3_CLK	Input clock
4	DEV_MCU_DCC0_DCC_CLKSRC4_CLK	Input clock
5	DEV_MCU_DCC0_DCC_CLKSRC5_CLK	Input clock
6	DEV_MCU_DCC0_DCC_CLKSRC6_CLK	Input clock
7	DEV_MCU_DCC0_DCC_CLKSRC7_CLK	Input clock
8	DEV_MCU_DCC0_DCC_INPUT00_CLK	Input clock
9	DEV_MCU_DCC0_DCC_INPUT01_CLK	Input clock
10	DEV_MCU_DCC0_DCC_INPUT02_CLK	Input clock
11	DEV_MCU_DCC0_DCC_INPUT10_CLK	Input clock
12	DEV_MCU_DCC0_VBUS_CLK	Input clock

Clocks for MCU_DCC1 Device

Device: J784S4_DEV_MCU_DCC1 (ID = 89)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DCC1_DCC_CLKSRC0_CLK	Input clock
1	DEV_MCU_DCC1_DCC_CLKSRC1_CLK	Input clock
2	DEV_MCU_DCC1_DCC_CLKSRC2_CLK	Input clock
3	DEV_MCU_DCC1_DCC_CLKSRC3_CLK	Input clock
4	DEV_MCU_DCC1_DCC_CLKSRC4_CLK	Input clock
5	DEV_MCU_DCC1_DCC_CLKSRC5_CLK	Input clock
6	DEV_MCU_DCC1_DCC_CLKSRC6_CLK	Input clock
7	DEV_MCU_DCC1_DCC_CLKSRC7_CLK	Input clock
8	DEV_MCU_DCC1_DCC_INPUT00_CLK	Input clock
9	DEV_MCU_DCC1_DCC_INPUT01_CLK	Input clock
10	DEV_MCU_DCC1_DCC_INPUT02_CLK	Input clock
11	DEV_MCU_DCC1_DCC_INPUT10_CLK	Input clock
12	DEV_MCU_DCC1_VBUS_CLK	Input clock

Clocks for MCU_DCC2 Device

Device: J784S4_DEV_MCU_DCC2 (ID = 90)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_DCC2_DCC_CLKSRC0_CLK	Input clock
1	DEV_MCU_DCC2_DCC_CLKSRC1_CLK	Input clock
2	DEV_MCU_DCC2_DCC_CLKSRC2_CLK	Input clock
3	DEV_MCU_DCC2_DCC_CLKSRC3_CLK	Input clock
4	DEV_MCU_DCC2_DCC_CLKSRC4_CLK	Input clock
6	DEV_MCU_DCC2_DCC_CLKSRC6_CLK	Input clock
7	DEV_MCU_DCC2_DCC_CLKSRC7_CLK	Input clock
8	DEV_MCU_DCC2_DCC_INPUT00_CLK	Input clock
9	DEV_MCU_DCC2_DCC_INPUT01_CLK	Input clock
10	DEV_MCU_DCC2_DCC_INPUT02_CLK	Input clock
11	DEV_MCU_DCC2_DCC_INPUT10_CLK	Input clock
12	DEV_MCU_DCC2_VBUS_CLK	Input clock

Clocks for MCU_ESM0 Device

Device: J784S4_DEV_MCU_ESM0 (ID = 148)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_ESM0_CLK	Input clock

Clocks for MCU_FSS0 Device

This device has no defined clocks.

Clocks for MCU_FSS0_FSAS_0 Device

Device: J784S4_DEV_MCU_FSS0_FSAS_0 (ID = 158)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_FSAS_0_GCLK	Input clock

Clocks for MCU_FSS0_HYPERBUS1P0_0 Device

Device: J784S4_DEV_MCU_FSS0_HYPERBUS1P0_0 (ID = 160)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK	Input clock
2	DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK	Input clock
4	DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK	Input clock
6	DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK	Input clock
8	DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK	Input clock
10	DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N	Output clock
11	DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P	Output clock

Clocks for MCU_FSS0_OSPI_0 Device

Device: J784S4_DEV_MCU_FSS0_OSPI_0 (ID = 161)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK	Input clock
1	DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK	Input clock
2	DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK	Input muxed clock
3	DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT	Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK
4	DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK
5	DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK	Output clock
6	DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK	Input clock
7	DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK	Input muxed clock
8	DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK
9	DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK

Clocks for MCU_FSS0_OSPI_1 Device

Device: J784S4_DEV_MCU_FSS0_OSPI_1 (ID = 162)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK	Input clock
1	DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK	Input clock
2	DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK	Input muxed clock
3	DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT	Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK
4	DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK
5	DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK	Output clock
6	DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK	Input clock
7	DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK	Input muxed clock
8	DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK
9	DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK	Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK

Clocks for MCU_I2C0 Device

Device: J784S4_DEV_MCU_I2C0 (ID = 277)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_I2C0_CLK	Input clock
1	DEV_MCU_I2C0_PISCL	Input clock
2	DEV_MCU_I2C0_PISYS_CLK	Input clock
3	DEV_MCU_I2C0_PORSCL	Output clock

Clocks for MCU_I2C1 Device

Device: J784S4_DEV_MCU_I2C1 (ID = 278)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_I2C1_CLK	Input clock
1	DEV_MCU_I2C1_PISCL	Input clock
2	DEV_MCU_I2C1_PISYS_CLK	Input clock
3	DEV_MCU_I2C1_PORSCL	Output clock

Clocks for MCU_I3C0 Device

Device: J784S4_DEV_MCU_I3C0 (ID = 170)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_I3C0_I3C_PCLK_CLK	Input clock
1	DEV_MCU_I3C0_I3C_SCL_DI	Input clock
2	DEV_MCU_I3C0_I3C_SCL_DO	Output clock
3	DEV_MCU_I3C0_I3C_SCLK_CLK	Input clock
4	DEV_MCU_I3C0_I3C_SDA_DI	Input clock

Clocks for MCU_I3C1 Device

Device: J784S4_DEV_MCU_I3C1 (ID = 171)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_I3C1_I3C_PCLK_CLK	Input clock
3	DEV_MCU_I3C1_I3C_SCLK_CLK	Input clock

Clocks for MCU_MCAN0 Device

Device: J784S4_DEV_MCU_MCAN0 (ID = 263)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCAN0_MCANSS_CAN_RXD	Input clock
1	DEV_MCU_MCAN0_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK	Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
3	DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
4	DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
5	DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
6	DEV_MCU_MCAN0_MCANSS_HCLK_CLK	Input clock

Clocks for MCU_MCAN1 Device

Device: J784S4_DEV_MCU_MCAN1 (ID = 264)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCAN1_MCANSS_CAN_RXD	Input clock
1	DEV_MCU_MCAN1_MCANSS_CCLK_CLK	Input muxed clock
2	DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK	Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
3	DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
4	DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
5	DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
6	DEV_MCU_MCAN1_MCANSS_HCLK_CLK	Input clock

Clocks for MCU_MCSPI0 Device

Device: J784S4_DEV_MCU_MCSPI0 (ID = 384)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCSPI0_CLKSPIREF_CLK	Input clock
1	DEV_MCU_MCSPI0_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT	Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK
3	DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK
4	DEV_MCU_MCSPI0_IO_CLKSPIO_CLK	Output clock
5	DEV_MCU_MCSPI0_VBUSP_CLK	Input clock

Clocks for MCU_MCSPI1 Device

Device: J784S4_DEV_MCU_MCSPI1 (ID = 385)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCSPI1_CLKSPIREF_CLK	Input clock
1	DEV_MCU_MCSPI1_IO_CLKSPII_CLK	Input muxed clock
2	DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK	Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK
3	DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0	Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK
4	DEV_MCU_MCSPI1_IO_CLKSPIO_CLK	Output clock
5	DEV_MCU_MCSPI1_VBUSP_CLK	Input clock

Clocks for MCU_MCSPI2 Device

Device: J784S4_DEV_MCU_MCSPI2 (ID = 386)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_MCSPI2_CLKSPIREF_CLK	Input clock
1	DEV_MCU_MCSPI2_IO_CLKSPII_CLK	Input clock
2	DEV_MCU_MCSPI2_IO_CLKSPIO_CLK	Output clock
3	DEV_MCU_MCSPI2_VBUSP_CLK	Input clock

Clocks for MCU_NAVSS0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_INTR_ROUTER_0 Device

Device: J784S4_DEV_MCU_NAVSS0_INTR_ROUTER_0 (ID = 324)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK	Input clock

Clocks for MCU_NAVSS0_MCRC_0 Device

Device: J784S4_DEV_MCU_NAVSS0_MCRC_0 (ID = 325)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_MCRC_0_CLK	Input clock

Clocks for MCU_NAVSS0_MODSS Device

Device: J784S4_DEV_MCU_NAVSS0_MODSS (ID = 326)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_MODSS_VD2CLK	Input clock

Clocks for MCU_NAVSS0_PROXY0 Device

Device: J784S4_DEV_MCU_NAVSS0_PROXY0 (ID = 327)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_PROXY0_CLK_CLK	Input clock

Clocks for MCU_NAVSS0_RINGACC0 Device

Device: J784S4_DEV_MCU_NAVSS0_RINGACC0 (ID = 328)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_RINGACC0_SYS_CLK	Input clock

Clocks for MCU_NAVSS0_UDMAP_0 Device

Device: J784S4_DEV_MCU_NAVSS0_UDMAP_0 (ID = 329)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK	Input clock

Clocks for MCU_NAVSS0_UDMASS Device

Device: J784S4_DEV_MCU_NAVSS0_UDMASS (ID = 330)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_UDMASS_VD2CLK	Input clock

Clocks for MCU_NAVSS0_UDMASS_INTA_0 Device

Device: J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 (ID = 331)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK	Input clock

Clocks for MCU_PBIST0 Device

Device: J784S4_DEV_MCU_PBIST0 (ID = 238)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PBIST0_CLK1_CLK	Input clock
1	DEV_MCU_PBIST0_CLK2_CLK	Input clock
2	DEV_MCU_PBIST0_CLK3_CLK	Input clock
3	DEV_MCU_PBIST0_CLK4_CLK	Input clock
4	DEV_MCU_PBIST0_CLK5_CLK	Input clock
5	DEV_MCU_PBIST0_CLK6_CLK	Input clock
6	DEV_MCU_PBIST0_CLK7_CLK	Input clock
7	DEV_MCU_PBIST0_CLK8_CLK	Input clock

Clocks for MCU_PBIST1 Device

Device: J784S4_DEV_MCU_PBIST1 (ID = 239)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_PBIST1_CLK1_CLK	Input clock
1	DEV_MCU_PBIST1_CLK2_CLK	Input clock
2	DEV_MCU_PBIST1_CLK3_CLK	Input clock
3	DEV_MCU_PBIST1_CLK4_CLK	Input clock
4	DEV_MCU_PBIST1_CLK5_CLK	Input clock
5	DEV_MCU_PBIST1_CLK6_CLK	Input clock
6	DEV_MCU_PBIST1_CLK7_CLK	Input clock
7	DEV_MCU_PBIST1_CLK8_CLK	Input clock

Clocks for MCU_PBIST2 Device

Device: J784S4_DEV_MCU_PBIST2 (ID = 240)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_MCU_PBIST2_CLK8_CLK	Input clock

Clocks for MCU_R5FSS0 Device

This device has no defined clocks.

Clocks for MCU_R5FSS0_CORE0 Device

Device: J784S4_DEV_MCU_R5FSS0_CORE0 (ID = 346)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_R5FSS0_CORE0_CPU_CLK	Input muxed clock
1	DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK
2	DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3	Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK
3	DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK	Input clock
4	DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE	Input clock

Clocks for MCU_R5FSS0_CORE1 Device

Device: J784S4_DEV_MCU_R5FSS0_CORE1 (ID = 347)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_R5FSS0_CORE1_CPU_CLK	Input muxed clock
1	DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK
2	DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3	Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK
3	DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK	Input clock
4	DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE	Input clock

Clocks for MCU_RTI0 Device

Device: J784S4_DEV_MCU_RTI0 (ID = 367)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_RTI0_RTI_CLK	Input muxed clock
1	DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_RTI0_RTI_CLK
2	DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_RTI0_RTI_CLK
3	DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_RTI0_RTI_CLK
4	DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_RTI0_RTI_CLK
9	DEV_MCU_RTI0_VBUSP_CLK	Input clock

Clocks for MCU_RTI1 Device

Device: J784S4_DEV_MCU_RTI1 (ID = 368)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_RTI1_RTI_CLK	Input muxed clock
1	DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_RTI1_RTI_CLK
2	DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_RTI1_RTI_CLK
3	DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_RTI1_RTI_CLK
4	DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_RTI1_RTI_CLK
9	DEV_MCU_RTI1_VBUSP_CLK	Input clock

Clocks for MCU_TIMER0 Device

Device: J784S4_DEV_MCU_TIMER0 (ID = 35)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER0_TIMER_HCLK_CLK	Input clock
1	DEV_MCU_TIMER0_TIMER_PWM	Output clock
2	DEV_MCU_TIMER0_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
4	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
5	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
6	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
7	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
8	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
9	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
10	DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK

Clocks for MCU_TIMER1 Device

Device: J784S4_DEV_MCU_TIMER1 (ID = 117)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER1_TIMER_HCLK_CLK	Input clock
2	DEV_MCU_TIMER1_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1	Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
4	DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM	Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK

Clocks for MCU_TIMER1_CLKSEL_VD Device

Device: J784S4_DEV_MCU_TIMER1_CLKSEL_VD (ID = 417)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER1_CLKSEL_VD_CLK	Input muxed clock
1	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
2	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
3	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
4	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
5	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
6	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
7	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
8	DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK

Clocks for MCU_TIMER2 Device

Device: J784S4_DEV_MCU_TIMER2 (ID = 118)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER2_TIMER_HCLK_CLK	Input clock
1	DEV_MCU_TIMER2_TIMER_PWM	Output clock
2	DEV_MCU_TIMER2_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
4	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
5	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
6	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
7	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
8	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
9	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
10	DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK

Clocks for MCU_TIMER3 Device

Device: J784S4_DEV_MCU_TIMER3 (ID = 119)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER3_TIMER_HCLK_CLK	Input clock
2	DEV_MCU_TIMER3_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3	Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
4	DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM	Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK

Clocks for MCU_TIMER3_CLKSEL_VD Device

Device: J784S4_DEV_MCU_TIMER3_CLKSEL_VD (ID = 418)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER3_CLKSEL_VD_CLK	Input muxed clock
1	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
2	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
3	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
4	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
5	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
6	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
7	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
8	DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK

Clocks for MCU_TIMER4 Device

Device: J784S4_DEV_MCU_TIMER4 (ID = 120)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER4_TIMER_HCLK_CLK	Input clock
1	DEV_MCU_TIMER4_TIMER_PWM	Output clock
2	DEV_MCU_TIMER4_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
4	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
5	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
6	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
7	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
8	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
9	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
10	DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK

Clocks for MCU_TIMER5 Device

Device: J784S4_DEV_MCU_TIMER5 (ID = 121)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER5_TIMER_HCLK_CLK	Input clock
2	DEV_MCU_TIMER5_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5	Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK
4	DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM	Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK

Clocks for MCU_TIMER5_CLKSEL_VD Device

Device: J784S4_DEV_MCU_TIMER5_CLKSEL_VD (ID = 419)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER5_CLKSEL_VD_CLK	Input muxed clock
1	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
2	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
3	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
4	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
5	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
6	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
7	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
8	DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK

Clocks for MCU_TIMER6 Device

Device: J784S4_DEV_MCU_TIMER6 (ID = 122)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER6_TIMER_HCLK_CLK	Input clock
1	DEV_MCU_TIMER6_TIMER_PWM	Output clock
2	DEV_MCU_TIMER6_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
4	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
5	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
6	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
7	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
8	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
9	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
10	DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK

Clocks for MCU_TIMER7 Device

Device: J784S4_DEV_MCU_TIMER7 (ID = 123)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER7_TIMER_HCLK_CLK	Input clock
2	DEV_MCU_TIMER7_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7	Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK
4	DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM	Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK

Clocks for MCU_TIMER7_CLKSEL_VD Device

Device: J784S4_DEV_MCU_TIMER7_CLKSEL_VD (ID = 420)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER7_CLKSEL_VD_CLK	Input muxed clock
1	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
2	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
3	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
4	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
5	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
6	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
7	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
8	DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK

Clocks for MCU_TIMER8 Device

Device: J784S4_DEV_MCU_TIMER8 (ID = 124)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER8_TIMER_HCLK_CLK	Input clock
1	DEV_MCU_TIMER8_TIMER_PWM	Output clock
2	DEV_MCU_TIMER8_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
4	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
5	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
6	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
7	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
8	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
9	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
10	DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK

Clocks for MCU_TIMER9 Device

Device: J784S4_DEV_MCU_TIMER9 (ID = 125)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER9_TIMER_HCLK_CLK	Input clock
2	DEV_MCU_TIMER9_TIMER_TCLK_CLK	Input muxed clock
3	DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9	Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK
4	DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM	Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK

Clocks for MCU_TIMER9_CLKSEL_VD Device

Device: J784S4_DEV_MCU_TIMER9_CLKSEL_VD (ID = 421)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_TIMER9_CLKSEL_VD_CLK	Input muxed clock
1	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
2	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
3	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
4	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
5	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
6	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
7	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
8	DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK

Clocks for MCU_UART0 Device

Device: J784S4_DEV_MCU_UART0 (ID = 149)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MCU_UART0_FCLK_CLK	Input muxed clock
1	DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK	Parent input clock option to DEV_MCU_UART0_FCLK_CLK
2	DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK	Parent input clock option to DEV_MCU_UART0_FCLK_CLK
5	DEV_MCU_UART0_VBUSP_CLK	Input clock

Clocks for MMCSD0 Device

Device: J784S4_DEV_MMCSD0 (ID = 140)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_MMCSD0_EMMCSS_VBUS_CLK	Input clock
2	DEV_MMCSD0_EMMCSS_XIN_CLK	Input muxed clock
3	DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
4	DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
5	DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
6	DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK

Clocks for MMCSD1 Device

Device: J784S4_DEV_MMCSD1 (ID = 141)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_MMCSD1_EMMCSDSS_IO_CLK_I	Input clock
1	DEV_MMCSD1_EMMCSDSS_IO_CLK_O	Output clock
3	DEV_MMCSD1_EMMCSDSS_VBUS_CLK	Input clock
4	DEV_MMCSD1_EMMCSDSS_XIN_CLK	Input muxed clock
5	DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
6	DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
7	DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
8	DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK	Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK

Clocks for NAVSS0 Device

Device: J784S4_DEV_NAVSS0 (ID = 280)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_CPTS0_GENF2	Output clock
1	DEV_NAVSS0_CPTS0_GENF3	Output clock

Clocks for NAVSS0_BCDMA_0 Device

Device: J784S4_DEV_NAVSS0_BCDMA_0 (ID = 281)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_BCDMA_0_CLK	Input clock

Clocks for NAVSS0_CPTS_0 Device

Device: J784S4_DEV_NAVSS0_CPTS_0 (ID = 282)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_CPTS_0_RCLK	Input muxed clock
1	DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
2	DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
3	DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
4	DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
5	DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
6	DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
7	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
8	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
9	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
10	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
11	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
12	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
13	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
14	DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
15	DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
16	DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
17	DEV_NAVSS0_CPTS_0_TS_GENF0	Output clock
18	DEV_NAVSS0_CPTS_0_TS_GENF1	Output clock
21	DEV_NAVSS0_CPTS_0_VBUSP_GCLK	Input clock

Clocks for NAVSS0_INTR_0 Device

Device: J784S4_DEV_NAVSS0_INTR_0 (ID = 283)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_INTR_0_INTR_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_0 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_0 (ID = 284)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_0_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_1 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_1 (ID = 285)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_1_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_10 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_10 (ID = 294)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_10_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_11 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_11 (ID = 295)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_11_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_2 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_2 (ID = 286)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_2_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_3 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_3 (ID = 287)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_3_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_4 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_4 (ID = 288)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_4_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_5 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_5 (ID = 289)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_5_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_6 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_6 (ID = 290)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_6_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_7 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_7 (ID = 291)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_7_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_8 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_8 (ID = 292)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_8_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX1_9 Device

Device: J784S4_DEV_NAVSS0_MAILBOX1_9 (ID = 293)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX1_9_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_0 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_0 (ID = 296)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_0_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_1 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_1 (ID = 297)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_1_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_10 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_10 (ID = 306)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_10_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_11 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_11 (ID = 307)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_11_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_2 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_2 (ID = 298)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_2_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_3 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_3 (ID = 299)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_3_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_4 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_4 (ID = 300)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_4_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_5 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_5 (ID = 301)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_5_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_6 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_6 (ID = 302)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_6_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_7 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_7 (ID = 303)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_7_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_8 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_8 (ID = 304)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_8_VCLK_CLK	Input clock

Clocks for NAVSS0_MAILBOX_9 Device

Device: J784S4_DEV_NAVSS0_MAILBOX_9 (ID = 305)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MAILBOX_9_VCLK_CLK	Input clock

Clocks for NAVSS0_MCRC_0 Device

Device: J784S4_DEV_NAVSS0_MCRC_0 (ID = 308)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MCRC_0_CLK	Input clock

Clocks for NAVSS0_MODSS Device

Device: J784S4_DEV_NAVSS0_MODSS (ID = 309)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MODSS_VD2CLK	Input clock

Clocks for NAVSS0_MODSS_INTA_0 Device

Device: J784S4_DEV_NAVSS0_MODSS_INTA_0 (ID = 310)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MODSS_INTA_0_SYS_CLK	Input clock

Clocks for NAVSS0_MODSS_INTA_1 Device

Device: J784S4_DEV_NAVSS0_MODSS_INTA_1 (ID = 311)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_MODSS_INTA_1_SYS_CLK	Input clock

Clocks for NAVSS0_PROXY_0 Device

Device: J784S4_DEV_NAVSS0_PROXY_0 (ID = 312)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_PROXY_0_CLK_CLK	Input clock

Clocks for NAVSS0_PVU_0 Device

Device: J784S4_DEV_NAVSS0_PVU_0 (ID = 313)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_PVU_0_CLK_CLK	Input clock

Clocks for NAVSS0_PVU_1 Device

Device: J784S4_DEV_NAVSS0_PVU_1 (ID = 314)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_PVU_1_CLK_CLK	Input clock

Clocks for NAVSS0_RINGACC_0 Device

Device: J784S4_DEV_NAVSS0_RINGACC_0 (ID = 315)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_RINGACC_0_SYS_CLK	Input clock

Clocks for NAVSS0_SPINLOCK_0 Device

Device: J784S4_DEV_NAVSS0_SPINLOCK_0 (ID = 316)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_SPINLOCK_0_CLK	Input clock

Clocks for NAVSS0_TIMERMGR_0 Device

Device: J784S4_DEV_NAVSS0_TIMERMGR_0 (ID = 317)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT	Input clock
1	DEV_NAVSS0_TIMERMGR_0_VCLK_CLK	Input clock

Clocks for NAVSS0_TIMERMGR_1 Device

Device: J784S4_DEV_NAVSS0_TIMERMGR_1 (ID = 318)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT	Input clock
1	DEV_NAVSS0_TIMERMGR_1_VCLK_CLK	Input clock

Clocks for NAVSS0_UDMAP_0 Device

Device: J784S4_DEV_NAVSS0_UDMAP_0 (ID = 319)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_UDMAP_0_SYS_CLK	Input clock

Clocks for NAVSS0_UDMASS Device

Device: J784S4_DEV_NAVSS0_UDMASS (ID = 320)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_UDMASS_VD2CLK	Input clock

Clocks for NAVSS0_UDMASS_INTA_0 Device

Device: J784S4_DEV_NAVSS0_UDMASS_INTA_0 (ID = 321)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK	Input clock

Clocks for NAVSS0_VIRTSS Device

Device: J784S4_DEV_NAVSS0_VIRTSS (ID = 322)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_NAVSS0_VIRTSS_VD2CLK	Input clock

Clocks for PBIST0 Device

Device: J784S4_DEV_PBIST0 (ID = 232)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST0_CLK8_CLK	Input clock

Clocks for PBIST1 Device

Device: J784S4_DEV_PBIST1 (ID = 233)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST1_CLK8_CLK	Input clock

Clocks for PBIST10 Device

Device: J784S4_DEV_PBIST10 (ID = 236)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST10_CLK8_CLK	Input clock

Clocks for PBIST11 Device

Device: J784S4_DEV_PBIST11 (ID = 227)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
6	DEV_PBIST11_CLK7_CLK	Input clock

Clocks for PBIST13 Device

This device has no defined clocks.

Clocks for PBIST14 Device

Device: J784S4_DEV_PBIST14 (ID = 237)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST14_CLK8_CLK	Input clock

Clocks for PBIST15 Device

This device has no defined clocks.

Clocks for PBIST2 Device

Device: J784S4_DEV_PBIST2 (ID = 235)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST2_CLK8_CLK	Input clock

Clocks for PBIST3 Device

Device: J784S4_DEV_PBIST3 (ID = 231)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST3_CLK8_CLK	Input clock

Clocks for PBIST4 Device

Device: J784S4_DEV_PBIST4 (ID = 234)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST4_CLK8_CLK	Input clock

Clocks for PBIST5 Device

Device: J784S4_DEV_PBIST5 (ID = 226)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
7	DEV_PBIST5_CLK8_CLK	Input clock

Clocks for PBIST7 Device

This device has no defined clocks.

Clocks for PBIST8 Device

This device has no defined clocks.

Clocks for PCIE0 Device

Device: J784S4_DEV_PCIE0 (ID = 332)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PCIE0_PCIE_CBA_CLK	Input clock
2	DEV_PCIE0_PCIE_CPTS_RCLK_CLK	Input muxed clock
3	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
4	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
5	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
6	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
7	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
8	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
9	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
10	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
11	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
12	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
13	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
14	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
15	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
16	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
17	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
18	DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
19	DEV_PCIE0_PCIE_LANE0_REFCLK	Input clock
20	DEV_PCIE0_PCIE_LANE0_RXCLK	Input clock
21	DEV_PCIE0_PCIE_LANE0_RXFCLK	Input clock
22	DEV_PCIE0_PCIE_LANE0_TXCLK	Output clock
23	DEV_PCIE0_PCIE_LANE0_TXFCLK	Input clock
24	DEV_PCIE0_PCIE_LANE0_TXMCLK	Input clock
25	DEV_PCIE0_PCIE_LANE1_REFCLK	Input clock
26	DEV_PCIE0_PCIE_LANE1_RXCLK	Input clock
27	DEV_PCIE0_PCIE_LANE1_RXFCLK	Input clock
28	DEV_PCIE0_PCIE_LANE1_TXCLK	Output clock
29	DEV_PCIE0_PCIE_LANE1_TXFCLK	Input clock
30	DEV_PCIE0_PCIE_LANE1_TXMCLK	Input clock
31	DEV_PCIE0_PCIE_LANE2_REFCLK	Input clock
32	DEV_PCIE0_PCIE_LANE2_RXCLK	Input clock
33	DEV_PCIE0_PCIE_LANE2_RXFCLK	Input clock
34	DEV_PCIE0_PCIE_LANE2_TXCLK	Output clock
35	DEV_PCIE0_PCIE_LANE2_TXFCLK	Input clock
36	DEV_PCIE0_PCIE_LANE2_TXMCLK	Input clock
37	DEV_PCIE0_PCIE_LANE3_REFCLK	Input clock
38	DEV_PCIE0_PCIE_LANE3_RXCLK	Input clock
39	DEV_PCIE0_PCIE_LANE3_RXFCLK	Input clock
40	DEV_PCIE0_PCIE_LANE3_TXCLK	Output clock
41	DEV_PCIE0_PCIE_LANE3_TXFCLK	Input clock
42	DEV_PCIE0_PCIE_LANE3_TXMCLK	Input clock
43	DEV_PCIE0_PCIE_PM_CLK	Input clock

Clocks for PCIE1 Device

Device: J784S4_DEV_PCIE1 (ID = 333)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PCIE1_PCIE_CBA_CLK	Input clock
2	DEV_PCIE1_PCIE_CPTS_RCLK_CLK	Input muxed clock
3	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
4	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
5	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
6	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
7	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
8	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
9	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
10	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
11	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
12	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
13	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
14	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
15	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
16	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
17	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
18	DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
19	DEV_PCIE1_PCIE_LANE0_REFCLK	Input clock
20	DEV_PCIE1_PCIE_LANE0_RXCLK	Input clock
21	DEV_PCIE1_PCIE_LANE0_RXFCLK	Input clock
22	DEV_PCIE1_PCIE_LANE0_TXCLK	Output clock
23	DEV_PCIE1_PCIE_LANE0_TXFCLK	Input clock
24	DEV_PCIE1_PCIE_LANE0_TXMCLK	Input clock
25	DEV_PCIE1_PCIE_LANE1_REFCLK	Input clock
26	DEV_PCIE1_PCIE_LANE1_RXCLK	Input clock
27	DEV_PCIE1_PCIE_LANE1_RXFCLK	Input clock
28	DEV_PCIE1_PCIE_LANE1_TXCLK	Output clock
29	DEV_PCIE1_PCIE_LANE1_TXFCLK	Input clock
30	DEV_PCIE1_PCIE_LANE1_TXMCLK	Input clock
31	DEV_PCIE1_PCIE_LANE2_REFCLK	Input clock
32	DEV_PCIE1_PCIE_LANE2_RXCLK	Input clock
33	DEV_PCIE1_PCIE_LANE2_RXFCLK	Input clock
34	DEV_PCIE1_PCIE_LANE2_TXCLK	Output clock
35	DEV_PCIE1_PCIE_LANE2_TXFCLK	Input clock
36	DEV_PCIE1_PCIE_LANE2_TXMCLK	Input clock
37	DEV_PCIE1_PCIE_LANE3_REFCLK	Input clock
38	DEV_PCIE1_PCIE_LANE3_RXCLK	Input clock
39	DEV_PCIE1_PCIE_LANE3_RXFCLK	Input clock
40	DEV_PCIE1_PCIE_LANE3_TXCLK	Output clock
41	DEV_PCIE1_PCIE_LANE3_TXFCLK	Input clock
42	DEV_PCIE1_PCIE_LANE3_TXMCLK	Input clock
43	DEV_PCIE1_PCIE_PM_CLK	Input clock

Clocks for PCIE2 Device

Device: J784S4_DEV_PCIE2 (ID = 334)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PCIE2_PCIE_CBA_CLK	Input clock
2	DEV_PCIE2_PCIE_CPTS_RCLK_CLK	Input muxed clock
3	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
4	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
5	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
6	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
7	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
8	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
9	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
10	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
11	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
12	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
13	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
14	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
15	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
16	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
17	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
18	DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK
19	DEV_PCIE2_PCIE_LANE0_REFCLK	Input clock
20	DEV_PCIE2_PCIE_LANE0_RXCLK	Input clock
21	DEV_PCIE2_PCIE_LANE0_RXFCLK	Input clock
22	DEV_PCIE2_PCIE_LANE0_TXCLK	Output clock
23	DEV_PCIE2_PCIE_LANE0_TXFCLK	Input clock
24	DEV_PCIE2_PCIE_LANE0_TXMCLK	Input clock
25	DEV_PCIE2_PCIE_LANE1_REFCLK	Input clock
26	DEV_PCIE2_PCIE_LANE1_RXCLK	Input clock
27	DEV_PCIE2_PCIE_LANE1_RXFCLK	Input clock
28	DEV_PCIE2_PCIE_LANE1_TXCLK	Output clock
29	DEV_PCIE2_PCIE_LANE1_TXFCLK	Input clock
30	DEV_PCIE2_PCIE_LANE1_TXMCLK	Input clock
43	DEV_PCIE2_PCIE_PM_CLK	Input clock

Clocks for PCIE3 Device

Device: J784S4_DEV_PCIE3 (ID = 335)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PCIE3_PCIE_CBA_CLK	Input clock
2	DEV_PCIE3_PCIE_CPTS_RCLK_CLK	Input muxed clock
3	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
4	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
5	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
6	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
7	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
8	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
9	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
10	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
11	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
12	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
13	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
14	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
15	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
16	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
17	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
18	DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK	Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK
19	DEV_PCIE3_PCIE_LANE0_REFCLK	Input clock
20	DEV_PCIE3_PCIE_LANE0_RXCLK	Input clock
21	DEV_PCIE3_PCIE_LANE0_RXFCLK	Input clock
22	DEV_PCIE3_PCIE_LANE0_TXCLK	Output clock
23	DEV_PCIE3_PCIE_LANE0_TXFCLK	Input clock
24	DEV_PCIE3_PCIE_LANE0_TXMCLK	Input clock
25	DEV_PCIE3_PCIE_LANE1_REFCLK	Input clock
26	DEV_PCIE3_PCIE_LANE1_RXCLK	Input clock
27	DEV_PCIE3_PCIE_LANE1_RXFCLK	Input clock
28	DEV_PCIE3_PCIE_LANE1_TXCLK	Output clock
29	DEV_PCIE3_PCIE_LANE1_TXFCLK	Input clock
30	DEV_PCIE3_PCIE_LANE1_TXMCLK	Input clock
43	DEV_PCIE3_PCIE_PM_CLK	Input clock

Clocks for PSC0 Device

Device: J784S4_DEV_PSC0 (ID = 201)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_PSC0_CLK	Input clock
1	DEV_PSC0_SLOW_CLK	Input clock

Clocks for R5FSS0 Device

This device has no defined clocks.

Clocks for R5FSS0_CORE0 Device

Device: J784S4_DEV_R5FSS0_CORE0 (ID = 339)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_R5FSS0_CORE0_CPU_CLK	Input clock
1	DEV_R5FSS0_CORE0_INTERFACE_CLK	Input clock

Clocks for R5FSS0_CORE1 Device

Device: J784S4_DEV_R5FSS0_CORE1 (ID = 340)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_R5FSS0_CORE1_CPU_CLK	Input clock
1	DEV_R5FSS0_CORE1_INTERFACE_CLK	Input clock

Clocks for R5FSS1 Device

This device has no defined clocks.

Clocks for R5FSS1_CORE0 Device

Device: J784S4_DEV_R5FSS1_CORE0 (ID = 341)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_R5FSS1_CORE0_CPU_CLK	Input clock
1	DEV_R5FSS1_CORE0_INTERFACE_CLK	Input clock

Clocks for R5FSS1_CORE1 Device

Device: J784S4_DEV_R5FSS1_CORE1 (ID = 342)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_R5FSS1_CORE1_CPU_CLK	Input clock
1	DEV_R5FSS1_CORE1_INTERFACE_CLK	Input clock

Clocks for R5FSS2 Device

This device has no defined clocks.

Clocks for R5FSS2_CORE0 Device

Device: J784S4_DEV_R5FSS2_CORE0 (ID = 343)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_R5FSS2_CORE0_CPU_CLK	Input clock
1	DEV_R5FSS2_CORE0_INTERFACE_CLK	Input clock

Clocks for R5FSS2_CORE1 Device

Device: J784S4_DEV_R5FSS2_CORE1 (ID = 344)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_R5FSS2_CORE1_CPU_CLK	Input clock
1	DEV_R5FSS2_CORE1_INTERFACE_CLK	Input clock

Clocks for RTI0 Device

Device: J784S4_DEV_RTI0 (ID = 348)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI0_RTI_CLK	Input muxed clock
1	DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI0_RTI_CLK
2	DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI0_RTI_CLK
3	DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI0_RTI_CLK
4	DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI0_RTI_CLK
5	DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI0_RTI_CLK
6	DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI0_RTI_CLK
7	DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI0_RTI_CLK
8	DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI0_RTI_CLK
9	DEV_RTI0_VBUSP_CLK	Input clock

Clocks for RTI1 Device

Device: J784S4_DEV_RTI1 (ID = 349)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI1_RTI_CLK	Input muxed clock
1	DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI1_RTI_CLK
2	DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI1_RTI_CLK
3	DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI1_RTI_CLK
4	DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI1_RTI_CLK
5	DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI1_RTI_CLK
6	DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI1_RTI_CLK
7	DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI1_RTI_CLK
8	DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI1_RTI_CLK
9	DEV_RTI1_VBUSP_CLK	Input clock

Clocks for RTI15 Device

Device: J784S4_DEV_RTI15 (ID = 360)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI15_RTI_CLK	Input muxed clock
1	DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI15_RTI_CLK
2	DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI15_RTI_CLK
3	DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI15_RTI_CLK
4	DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI15_RTI_CLK
5	DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI15_RTI_CLK
6	DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI15_RTI_CLK
7	DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI15_RTI_CLK
8	DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI15_RTI_CLK
9	DEV_RTI15_VBUSP_CLK	Input clock

Clocks for RTI16 Device

Device: J784S4_DEV_RTI16 (ID = 356)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI16_RTI_CLK	Input muxed clock
1	DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI16_RTI_CLK
2	DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI16_RTI_CLK
3	DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI16_RTI_CLK
4	DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI16_RTI_CLK
5	DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI16_RTI_CLK
6	DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI16_RTI_CLK
7	DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI16_RTI_CLK
8	DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI16_RTI_CLK
9	DEV_RTI16_VBUSP_CLK	Input clock

Clocks for RTI17 Device

Device: J784S4_DEV_RTI17 (ID = 357)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI17_RTI_CLK	Input muxed clock
1	DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI17_RTI_CLK
2	DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI17_RTI_CLK
3	DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI17_RTI_CLK
4	DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI17_RTI_CLK
5	DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI17_RTI_CLK
6	DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI17_RTI_CLK
7	DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI17_RTI_CLK
8	DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI17_RTI_CLK
9	DEV_RTI17_VBUSP_CLK	Input clock

Clocks for RTI18 Device

Device: J784S4_DEV_RTI18 (ID = 358)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI18_RTI_CLK	Input muxed clock
1	DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI18_RTI_CLK
2	DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI18_RTI_CLK
3	DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI18_RTI_CLK
4	DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI18_RTI_CLK
5	DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI18_RTI_CLK
6	DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI18_RTI_CLK
7	DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI18_RTI_CLK
8	DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI18_RTI_CLK
9	DEV_RTI18_VBUSP_CLK	Input clock

Clocks for RTI19 Device

Device: J784S4_DEV_RTI19 (ID = 359)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI19_RTI_CLK	Input muxed clock
1	DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI19_RTI_CLK
2	DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI19_RTI_CLK
3	DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI19_RTI_CLK
4	DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI19_RTI_CLK
5	DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI19_RTI_CLK
6	DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI19_RTI_CLK
7	DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI19_RTI_CLK
8	DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI19_RTI_CLK
9	DEV_RTI19_VBUSP_CLK	Input clock

Clocks for RTI2 Device

Device: J784S4_DEV_RTI2 (ID = 350)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI2_RTI_CLK	Input muxed clock
1	DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI2_RTI_CLK
2	DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI2_RTI_CLK
3	DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI2_RTI_CLK
4	DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI2_RTI_CLK
5	DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI2_RTI_CLK
6	DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI2_RTI_CLK
7	DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI2_RTI_CLK
8	DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI2_RTI_CLK
9	DEV_RTI2_VBUSP_CLK	Input clock

Clocks for RTI28 Device

Device: J784S4_DEV_RTI28 (ID = 361)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI28_RTI_CLK	Input muxed clock
1	DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI28_RTI_CLK
2	DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI28_RTI_CLK
3	DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI28_RTI_CLK
4	DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI28_RTI_CLK
5	DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI28_RTI_CLK
6	DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI28_RTI_CLK
7	DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI28_RTI_CLK
8	DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI28_RTI_CLK
9	DEV_RTI28_VBUSP_CLK	Input clock

Clocks for RTI29 Device

Device: J784S4_DEV_RTI29 (ID = 362)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI29_RTI_CLK	Input muxed clock
1	DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI29_RTI_CLK
2	DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI29_RTI_CLK
3	DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI29_RTI_CLK
4	DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI29_RTI_CLK
5	DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI29_RTI_CLK
6	DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI29_RTI_CLK
7	DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI29_RTI_CLK
8	DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI29_RTI_CLK
9	DEV_RTI29_VBUSP_CLK	Input clock

Clocks for RTI3 Device

Device: J784S4_DEV_RTI3 (ID = 351)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI3_RTI_CLK	Input muxed clock
1	DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI3_RTI_CLK
2	DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI3_RTI_CLK
3	DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI3_RTI_CLK
4	DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI3_RTI_CLK
5	DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI3_RTI_CLK
6	DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI3_RTI_CLK
7	DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI3_RTI_CLK
8	DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI3_RTI_CLK
9	DEV_RTI3_VBUSP_CLK	Input clock

Clocks for RTI30 Device

Device: J784S4_DEV_RTI30 (ID = 363)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI30_RTI_CLK	Input muxed clock
1	DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI30_RTI_CLK
2	DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI30_RTI_CLK
3	DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI30_RTI_CLK
4	DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI30_RTI_CLK
5	DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI30_RTI_CLK
6	DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI30_RTI_CLK
7	DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI30_RTI_CLK
8	DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI30_RTI_CLK
9	DEV_RTI30_VBUSP_CLK	Input clock

Clocks for RTI31 Device

Device: J784S4_DEV_RTI31 (ID = 364)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI31_RTI_CLK	Input muxed clock
1	DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI31_RTI_CLK
2	DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI31_RTI_CLK
3	DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI31_RTI_CLK
4	DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI31_RTI_CLK
5	DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI31_RTI_CLK
6	DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI31_RTI_CLK
7	DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI31_RTI_CLK
8	DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI31_RTI_CLK
9	DEV_RTI31_VBUSP_CLK	Input clock

Clocks for RTI32 Device

Device: J784S4_DEV_RTI32 (ID = 365)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI32_RTI_CLK	Input muxed clock
1	DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI32_RTI_CLK
2	DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI32_RTI_CLK
3	DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI32_RTI_CLK
4	DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI32_RTI_CLK
5	DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI32_RTI_CLK
6	DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI32_RTI_CLK
7	DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI32_RTI_CLK
8	DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI32_RTI_CLK
9	DEV_RTI32_VBUSP_CLK	Input clock

Clocks for RTI33 Device

Device: J784S4_DEV_RTI33 (ID = 366)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI33_RTI_CLK	Input muxed clock
1	DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI33_RTI_CLK
2	DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI33_RTI_CLK
3	DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI33_RTI_CLK
4	DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI33_RTI_CLK
5	DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI33_RTI_CLK
6	DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI33_RTI_CLK
7	DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI33_RTI_CLK
8	DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI33_RTI_CLK
9	DEV_RTI33_VBUSP_CLK	Input clock

Clocks for RTI4 Device

Device: J784S4_DEV_RTI4 (ID = 352)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI4_RTI_CLK	Input muxed clock
1	DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI4_RTI_CLK
2	DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI4_RTI_CLK
3	DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI4_RTI_CLK
4	DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI4_RTI_CLK
5	DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI4_RTI_CLK
6	DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI4_RTI_CLK
7	DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI4_RTI_CLK
8	DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI4_RTI_CLK
9	DEV_RTI4_VBUSP_CLK	Input clock

Clocks for RTI5 Device

Device: J784S4_DEV_RTI5 (ID = 353)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI5_RTI_CLK	Input muxed clock
1	DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI5_RTI_CLK
2	DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI5_RTI_CLK
3	DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI5_RTI_CLK
4	DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI5_RTI_CLK
5	DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI5_RTI_CLK
6	DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI5_RTI_CLK
7	DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI5_RTI_CLK
8	DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI5_RTI_CLK
9	DEV_RTI5_VBUSP_CLK	Input clock

Clocks for RTI6 Device

Device: J784S4_DEV_RTI6 (ID = 354)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI6_RTI_CLK	Input muxed clock
1	DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI6_RTI_CLK
2	DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI6_RTI_CLK
3	DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI6_RTI_CLK
4	DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI6_RTI_CLK
5	DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI6_RTI_CLK
6	DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI6_RTI_CLK
7	DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI6_RTI_CLK
8	DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI6_RTI_CLK
9	DEV_RTI6_VBUSP_CLK	Input clock

Clocks for RTI7 Device

Device: J784S4_DEV_RTI7 (ID = 355)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_RTI7_RTI_CLK	Input muxed clock
1	DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_RTI7_RTI_CLK
2	DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_RTI7_RTI_CLK
3	DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_RTI7_RTI_CLK
4	DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK	Parent input clock option to DEV_RTI7_RTI_CLK
5	DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_RTI7_RTI_CLK
6	DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0	Parent input clock option to DEV_RTI7_RTI_CLK
7	DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1	Parent input clock option to DEV_RTI7_RTI_CLK
8	DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2	Parent input clock option to DEV_RTI7_RTI_CLK
9	DEV_RTI7_VBUSP_CLK	Input clock

Clocks for SA2_CPSW_PSILSS0 Device

Device: J784S4_DEV_SA2_CPSW_PSILSS0 (ID = 8)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK	Input clock
1	DEV_SA2_CPSW_PSILSS0_MAIN_CLK	Input clock

Clocks for SA2_UL0 Device

Device: J784S4_DEV_SA2_UL0 (ID = 369)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_SA2_UL0_PKA_IN_CLK	Input clock
1	DEV_SA2_UL0_X1_CLK	Input clock
2	DEV_SA2_UL0_X2_CLK	Input clock

Clocks for SERDES_10G0 Device

Device: J784S4_DEV_SERDES_10G0 (ID = 404)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_SERDES_10G0_CLK	Input clock
3	DEV_SERDES_10G0_CMN_REFCLK_M	Input clock
3	DEV_SERDES_10G0_CMN_REFCLK_M	Output clock
4	DEV_SERDES_10G0_CMN_REFCLK_P	Input clock
4	DEV_SERDES_10G0_CMN_REFCLK_P	Output clock
5	DEV_SERDES_10G0_CORE_REF1_CLK	Input clock
6	DEV_SERDES_10G0_CORE_REF_CLK	Input muxed clock
7	DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
8	DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
9	DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
10	DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
15	DEV_SERDES_10G0_IP1_LN0_TXCLK	Input clock
21	DEV_SERDES_10G0_IP1_LN1_TXCLK	Input clock
24	DEV_SERDES_10G0_IP1_LN2_REFCLK	Output clock
25	DEV_SERDES_10G0_IP1_LN2_RXCLK	Output clock
26	DEV_SERDES_10G0_IP1_LN2_RXFCLK	Output clock
27	DEV_SERDES_10G0_IP1_LN2_TXCLK	Input clock
28	DEV_SERDES_10G0_IP1_LN2_TXFCLK	Output clock
29	DEV_SERDES_10G0_IP1_LN2_TXMCLK	Output clock
30	DEV_SERDES_10G0_IP1_LN3_REFCLK	Output clock
31	DEV_SERDES_10G0_IP1_LN3_RXCLK	Output clock
32	DEV_SERDES_10G0_IP1_LN3_RXFCLK	Output clock
33	DEV_SERDES_10G0_IP1_LN3_TXCLK	Input clock
34	DEV_SERDES_10G0_IP1_LN3_TXFCLK	Output clock
35	DEV_SERDES_10G0_IP1_LN3_TXMCLK	Output clock
36	DEV_SERDES_10G0_IP2_LN0_REFCLK	Output clock
37	DEV_SERDES_10G0_IP2_LN0_RXCLK	Output clock
38	DEV_SERDES_10G0_IP2_LN0_RXFCLK	Output clock
39	DEV_SERDES_10G0_IP2_LN0_TXCLK	Input clock
40	DEV_SERDES_10G0_IP2_LN0_TXFCLK	Output clock
41	DEV_SERDES_10G0_IP2_LN0_TXMCLK	Output clock
42	DEV_SERDES_10G0_IP2_LN1_REFCLK	Output clock
43	DEV_SERDES_10G0_IP2_LN1_RXCLK	Output clock
44	DEV_SERDES_10G0_IP2_LN1_RXFCLK	Output clock
45	DEV_SERDES_10G0_IP2_LN1_TXCLK	Input clock
46	DEV_SERDES_10G0_IP2_LN1_TXFCLK	Output clock
47	DEV_SERDES_10G0_IP2_LN1_TXMCLK	Output clock
48	DEV_SERDES_10G0_IP2_LN2_REFCLK	Output clock
49	DEV_SERDES_10G0_IP2_LN2_RXCLK	Output clock
50	DEV_SERDES_10G0_IP2_LN2_RXFCLK	Output clock
51	DEV_SERDES_10G0_IP2_LN2_TXCLK	Input clock
52	DEV_SERDES_10G0_IP2_LN2_TXFCLK	Output clock
53	DEV_SERDES_10G0_IP2_LN2_TXMCLK	Output clock
54	DEV_SERDES_10G0_IP2_LN3_REFCLK	Output clock
55	DEV_SERDES_10G0_IP2_LN3_RXCLK	Output clock
56	DEV_SERDES_10G0_IP2_LN3_RXFCLK	Output clock
57	DEV_SERDES_10G0_IP2_LN3_TXCLK	Input clock
58	DEV_SERDES_10G0_IP2_LN3_TXFCLK	Output clock
59	DEV_SERDES_10G0_IP2_LN3_TXMCLK	Output clock
78	DEV_SERDES_10G0_IP3_LN3_REFCLK	Output clock
79	DEV_SERDES_10G0_IP3_LN3_RXCLK	Output clock
80	DEV_SERDES_10G0_IP3_LN3_RXFCLK	Output clock
81	DEV_SERDES_10G0_IP3_LN3_TXCLK	Input clock
82	DEV_SERDES_10G0_IP3_LN3_TXFCLK	Output clock
83	DEV_SERDES_10G0_IP3_LN3_TXMCLK	Output clock
84	DEV_SERDES_10G0_IP4_LN0_REFCLK	Output clock
85	DEV_SERDES_10G0_IP4_LN0_RXCLK	Output clock
86	DEV_SERDES_10G0_IP4_LN0_RXFCLK	Output clock
87	DEV_SERDES_10G0_IP4_LN0_TXCLK	Input clock
88	DEV_SERDES_10G0_IP4_LN0_TXFCLK	Output clock
89	DEV_SERDES_10G0_IP4_LN0_TXMCLK	Output clock
90	DEV_SERDES_10G0_IP4_LN1_REFCLK	Output clock
91	DEV_SERDES_10G0_IP4_LN1_RXCLK	Output clock
92	DEV_SERDES_10G0_IP4_LN1_RXFCLK	Output clock
93	DEV_SERDES_10G0_IP4_LN1_TXCLK	Input clock
94	DEV_SERDES_10G0_IP4_LN1_TXFCLK	Output clock
95	DEV_SERDES_10G0_IP4_LN1_TXMCLK	Output clock
96	DEV_SERDES_10G0_IP4_LN2_REFCLK	Output clock
97	DEV_SERDES_10G0_IP4_LN2_RXCLK	Output clock
98	DEV_SERDES_10G0_IP4_LN2_RXFCLK	Output clock
99	DEV_SERDES_10G0_IP4_LN2_TXCLK	Input clock
100	DEV_SERDES_10G0_IP4_LN2_TXFCLK	Output clock
101	DEV_SERDES_10G0_IP4_LN2_TXMCLK	Output clock
102	DEV_SERDES_10G0_IP4_LN3_REFCLK	Output clock
103	DEV_SERDES_10G0_IP4_LN3_RXCLK	Output clock
104	DEV_SERDES_10G0_IP4_LN3_RXFCLK	Output clock
105	DEV_SERDES_10G0_IP4_LN3_TXCLK	Input clock
106	DEV_SERDES_10G0_IP4_LN3_TXFCLK	Output clock
107	DEV_SERDES_10G0_IP4_LN3_TXMCLK	Output clock
124	DEV_SERDES_10G0_REF_DER_OUT_CLK	Output clock
125	DEV_SERDES_10G0_REF_OUT_CLK	Output clock
129	DEV_SERDES_10G0_TAP_TCK	Input clock

Clocks for SERDES_10G1 Device

Device: J784S4_DEV_SERDES_10G1 (ID = 405)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_SERDES_10G1_CLK	Input clock
3	DEV_SERDES_10G1_CMN_REFCLK_M	Input clock
3	DEV_SERDES_10G1_CMN_REFCLK_M	Output clock
4	DEV_SERDES_10G1_CMN_REFCLK_P	Input clock
4	DEV_SERDES_10G1_CMN_REFCLK_P	Output clock
5	DEV_SERDES_10G1_CORE_REF1_CLK	Input clock
6	DEV_SERDES_10G1_CORE_REF_CLK	Input muxed clock
7	DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
8	DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
9	DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
10	DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
12	DEV_SERDES_10G1_IP1_LN0_REFCLK	Output clock
13	DEV_SERDES_10G1_IP1_LN0_RXCLK	Output clock
14	DEV_SERDES_10G1_IP1_LN0_RXFCLK	Output clock
15	DEV_SERDES_10G1_IP1_LN0_TXCLK	Input clock
16	DEV_SERDES_10G1_IP1_LN0_TXFCLK	Output clock
17	DEV_SERDES_10G1_IP1_LN0_TXMCLK	Output clock
18	DEV_SERDES_10G1_IP1_LN1_REFCLK	Output clock
19	DEV_SERDES_10G1_IP1_LN1_RXCLK	Output clock
20	DEV_SERDES_10G1_IP1_LN1_RXFCLK	Output clock
21	DEV_SERDES_10G1_IP1_LN1_TXCLK	Input clock
22	DEV_SERDES_10G1_IP1_LN1_TXFCLK	Output clock
23	DEV_SERDES_10G1_IP1_LN1_TXMCLK	Output clock
24	DEV_SERDES_10G1_IP1_LN2_REFCLK	Output clock
25	DEV_SERDES_10G1_IP1_LN2_RXCLK	Output clock
26	DEV_SERDES_10G1_IP1_LN2_RXFCLK	Output clock
27	DEV_SERDES_10G1_IP1_LN2_TXCLK	Input clock
28	DEV_SERDES_10G1_IP1_LN2_TXFCLK	Output clock
29	DEV_SERDES_10G1_IP1_LN2_TXMCLK	Output clock
30	DEV_SERDES_10G1_IP1_LN3_REFCLK	Output clock
31	DEV_SERDES_10G1_IP1_LN3_RXCLK	Output clock
32	DEV_SERDES_10G1_IP1_LN3_RXFCLK	Output clock
33	DEV_SERDES_10G1_IP1_LN3_TXCLK	Input clock
34	DEV_SERDES_10G1_IP1_LN3_TXFCLK	Output clock
35	DEV_SERDES_10G1_IP1_LN3_TXMCLK	Output clock
36	DEV_SERDES_10G1_IP2_LN0_REFCLK	Output clock
37	DEV_SERDES_10G1_IP2_LN0_RXCLK	Output clock
38	DEV_SERDES_10G1_IP2_LN0_RXFCLK	Output clock
39	DEV_SERDES_10G1_IP2_LN0_TXCLK	Input clock
40	DEV_SERDES_10G1_IP2_LN0_TXFCLK	Output clock
41	DEV_SERDES_10G1_IP2_LN0_TXMCLK	Output clock
42	DEV_SERDES_10G1_IP2_LN1_REFCLK	Output clock
43	DEV_SERDES_10G1_IP2_LN1_RXCLK	Output clock
44	DEV_SERDES_10G1_IP2_LN1_RXFCLK	Output clock
45	DEV_SERDES_10G1_IP2_LN1_TXCLK	Input clock
46	DEV_SERDES_10G1_IP2_LN1_TXFCLK	Output clock
47	DEV_SERDES_10G1_IP2_LN1_TXMCLK	Output clock
48	DEV_SERDES_10G1_IP2_LN2_REFCLK	Output clock
49	DEV_SERDES_10G1_IP2_LN2_RXCLK	Output clock
50	DEV_SERDES_10G1_IP2_LN2_RXFCLK	Output clock
51	DEV_SERDES_10G1_IP2_LN2_TXCLK	Input clock
52	DEV_SERDES_10G1_IP2_LN2_TXFCLK	Output clock
53	DEV_SERDES_10G1_IP2_LN2_TXMCLK	Output clock
54	DEV_SERDES_10G1_IP2_LN3_REFCLK	Output clock
55	DEV_SERDES_10G1_IP2_LN3_RXCLK	Output clock
56	DEV_SERDES_10G1_IP2_LN3_RXFCLK	Output clock
57	DEV_SERDES_10G1_IP2_LN3_TXCLK	Input clock
58	DEV_SERDES_10G1_IP2_LN3_TXFCLK	Output clock
59	DEV_SERDES_10G1_IP2_LN3_TXMCLK	Output clock
72	DEV_SERDES_10G1_IP3_LN2_REFCLK	Output clock
73	DEV_SERDES_10G1_IP3_LN2_RXCLK	Output clock
74	DEV_SERDES_10G1_IP3_LN2_RXFCLK	Output clock
75	DEV_SERDES_10G1_IP3_LN2_TXCLK	Input clock
76	DEV_SERDES_10G1_IP3_LN2_TXFCLK	Output clock
77	DEV_SERDES_10G1_IP3_LN2_TXMCLK	Output clock
78	DEV_SERDES_10G1_IP3_LN3_REFCLK	Output clock
79	DEV_SERDES_10G1_IP3_LN3_RXCLK	Output clock
80	DEV_SERDES_10G1_IP3_LN3_RXFCLK	Output clock
81	DEV_SERDES_10G1_IP3_LN3_TXCLK	Input clock
82	DEV_SERDES_10G1_IP3_LN3_TXFCLK	Output clock
83	DEV_SERDES_10G1_IP3_LN3_TXMCLK	Output clock
124	DEV_SERDES_10G1_REF_DER_OUT_CLK	Output clock
125	DEV_SERDES_10G1_REF_OUT_CLK	Output clock
129	DEV_SERDES_10G1_TAP_TCK	Input clock

Clocks for SERDES_10G2 Device

Device: J784S4_DEV_SERDES_10G2 (ID = 406)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_SERDES_10G2_CLK	Input clock
3	DEV_SERDES_10G2_CMN_REFCLK_M	Input clock
3	DEV_SERDES_10G2_CMN_REFCLK_M	Output clock
4	DEV_SERDES_10G2_CMN_REFCLK_P	Input clock
5	DEV_SERDES_10G2_CORE_REF1_CLK	Input clock
6	DEV_SERDES_10G2_CORE_REF_CLK	Input muxed clock
7	DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK
8	DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK
9	DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK
10	DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK
12	DEV_SERDES_10G2_IP1_LN0_REFCLK	Output clock
13	DEV_SERDES_10G2_IP1_LN0_RXCLK	Output clock
14	DEV_SERDES_10G2_IP1_LN0_RXFCLK	Output clock
15	DEV_SERDES_10G2_IP1_LN0_TXCLK	Input clock
16	DEV_SERDES_10G2_IP1_LN0_TXFCLK	Output clock
17	DEV_SERDES_10G2_IP1_LN0_TXMCLK	Output clock
18	DEV_SERDES_10G2_IP1_LN1_REFCLK	Output clock
19	DEV_SERDES_10G2_IP1_LN1_RXCLK	Output clock
20	DEV_SERDES_10G2_IP1_LN1_RXFCLK	Output clock
21	DEV_SERDES_10G2_IP1_LN1_TXCLK	Input clock
22	DEV_SERDES_10G2_IP1_LN1_TXFCLK	Output clock
23	DEV_SERDES_10G2_IP1_LN1_TXMCLK	Output clock
24	DEV_SERDES_10G2_IP1_LN2_REFCLK	Output clock
25	DEV_SERDES_10G2_IP1_LN2_RXCLK	Output clock
26	DEV_SERDES_10G2_IP1_LN2_RXFCLK	Output clock
27	DEV_SERDES_10G2_IP1_LN2_TXCLK	Input clock
28	DEV_SERDES_10G2_IP1_LN2_TXFCLK	Output clock
29	DEV_SERDES_10G2_IP1_LN2_TXMCLK	Output clock
30	DEV_SERDES_10G2_IP1_LN3_REFCLK	Output clock
31	DEV_SERDES_10G2_IP1_LN3_RXCLK	Output clock
32	DEV_SERDES_10G2_IP1_LN3_RXFCLK	Output clock
33	DEV_SERDES_10G2_IP1_LN3_TXCLK	Input clock
34	DEV_SERDES_10G2_IP1_LN3_TXFCLK	Output clock
35	DEV_SERDES_10G2_IP1_LN3_TXMCLK	Output clock
48	DEV_SERDES_10G2_IP2_LN2_REFCLK	Output clock
49	DEV_SERDES_10G2_IP2_LN2_RXCLK	Output clock
50	DEV_SERDES_10G2_IP2_LN2_RXFCLK	Output clock
51	DEV_SERDES_10G2_IP2_LN2_TXCLK	Input clock
52	DEV_SERDES_10G2_IP2_LN2_TXFCLK	Output clock
53	DEV_SERDES_10G2_IP2_LN2_TXMCLK	Output clock
54	DEV_SERDES_10G2_IP2_LN3_REFCLK	Output clock
55	DEV_SERDES_10G2_IP2_LN3_RXCLK	Output clock
56	DEV_SERDES_10G2_IP2_LN3_RXFCLK	Output clock
57	DEV_SERDES_10G2_IP2_LN3_TXCLK	Input clock
58	DEV_SERDES_10G2_IP2_LN3_TXFCLK	Output clock
59	DEV_SERDES_10G2_IP2_LN3_TXMCLK	Output clock
129	DEV_SERDES_10G2_TAP_TCK	Input clock

Clocks for SERDES_10G4 Device

Device: J784S4_DEV_SERDES_10G4 (ID = 407)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
2	DEV_SERDES_10G4_CLK	Input clock
3	DEV_SERDES_10G4_CMN_REFCLK_M	Input clock
3	DEV_SERDES_10G4_CMN_REFCLK_M	Output clock
4	DEV_SERDES_10G4_CMN_REFCLK_P	Input clock
4	DEV_SERDES_10G4_CMN_REFCLK_P	Output clock
5	DEV_SERDES_10G4_CORE_REF1_CLK	Input clock
6	DEV_SERDES_10G4_CORE_REF_CLK	Input muxed clock
7	DEV_SERDES_10G4_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK
8	DEV_SERDES_10G4_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK
9	DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK
10	DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK	Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK
12	DEV_SERDES_10G4_IP1_LN0_REFCLK	Output clock
13	DEV_SERDES_10G4_IP1_LN0_RXCLK	Output clock
14	DEV_SERDES_10G4_IP1_LN0_RXFCLK	Output clock
15	DEV_SERDES_10G4_IP1_LN0_TXCLK	Input clock
16	DEV_SERDES_10G4_IP1_LN0_TXFCLK	Output clock
17	DEV_SERDES_10G4_IP1_LN0_TXMCLK	Output clock
18	DEV_SERDES_10G4_IP1_LN1_REFCLK	Output clock
19	DEV_SERDES_10G4_IP1_LN1_RXCLK	Output clock
20	DEV_SERDES_10G4_IP1_LN1_RXFCLK	Output clock
21	DEV_SERDES_10G4_IP1_LN1_TXCLK	Input clock
22	DEV_SERDES_10G4_IP1_LN1_TXFCLK	Output clock
23	DEV_SERDES_10G4_IP1_LN1_TXMCLK	Output clock
24	DEV_SERDES_10G4_IP1_LN2_REFCLK	Output clock
25	DEV_SERDES_10G4_IP1_LN2_RXCLK	Output clock
26	DEV_SERDES_10G4_IP1_LN2_RXFCLK	Output clock
27	DEV_SERDES_10G4_IP1_LN2_TXCLK	Input clock
28	DEV_SERDES_10G4_IP1_LN2_TXFCLK	Output clock
29	DEV_SERDES_10G4_IP1_LN2_TXMCLK	Output clock
30	DEV_SERDES_10G4_IP1_LN3_REFCLK	Output clock
31	DEV_SERDES_10G4_IP1_LN3_RXCLK	Output clock
32	DEV_SERDES_10G4_IP1_LN3_RXFCLK	Output clock
33	DEV_SERDES_10G4_IP1_LN3_TXCLK	Input clock
34	DEV_SERDES_10G4_IP1_LN3_TXFCLK	Output clock
35	DEV_SERDES_10G4_IP1_LN3_TXMCLK	Output clock
36	DEV_SERDES_10G4_IP2_LN0_REFCLK	Output clock
37	DEV_SERDES_10G4_IP2_LN0_RXCLK	Output clock
38	DEV_SERDES_10G4_IP2_LN0_RXFCLK	Output clock
39	DEV_SERDES_10G4_IP2_LN0_TXCLK	Input clock
40	DEV_SERDES_10G4_IP2_LN0_TXFCLK	Output clock
41	DEV_SERDES_10G4_IP2_LN0_TXMCLK	Output clock
42	DEV_SERDES_10G4_IP2_LN1_REFCLK	Output clock
43	DEV_SERDES_10G4_IP2_LN1_RXCLK	Output clock
44	DEV_SERDES_10G4_IP2_LN1_RXFCLK	Output clock
45	DEV_SERDES_10G4_IP2_LN1_TXCLK	Input clock
46	DEV_SERDES_10G4_IP2_LN1_TXFCLK	Output clock
47	DEV_SERDES_10G4_IP2_LN1_TXMCLK	Output clock
48	DEV_SERDES_10G4_IP2_LN2_REFCLK	Output clock
49	DEV_SERDES_10G4_IP2_LN2_RXCLK	Output clock
50	DEV_SERDES_10G4_IP2_LN2_RXFCLK	Output clock
51	DEV_SERDES_10G4_IP2_LN2_TXCLK	Input clock
52	DEV_SERDES_10G4_IP2_LN2_TXFCLK	Output clock
53	DEV_SERDES_10G4_IP2_LN2_TXMCLK	Output clock
54	DEV_SERDES_10G4_IP2_LN3_REFCLK	Output clock
55	DEV_SERDES_10G4_IP2_LN3_RXCLK	Output clock
56	DEV_SERDES_10G4_IP2_LN3_RXFCLK	Output clock
57	DEV_SERDES_10G4_IP2_LN3_TXCLK	Input clock
58	DEV_SERDES_10G4_IP2_LN3_TXFCLK	Output clock
59	DEV_SERDES_10G4_IP2_LN3_TXMCLK	Output clock
78	DEV_SERDES_10G4_IP3_LN3_REFCLK	Output clock
79	DEV_SERDES_10G4_IP3_LN3_RXCLK	Output clock
80	DEV_SERDES_10G4_IP3_LN3_RXFCLK	Output clock
81	DEV_SERDES_10G4_IP3_LN3_TXCLK	Input clock
82	DEV_SERDES_10G4_IP3_LN3_TXFCLK	Output clock
83	DEV_SERDES_10G4_IP3_LN3_TXMCLK	Output clock
84	DEV_SERDES_10G4_IP4_LN0_REFCLK	Output clock
85	DEV_SERDES_10G4_IP4_LN0_RXCLK	Output clock
86	DEV_SERDES_10G4_IP4_LN0_RXFCLK	Output clock
87	DEV_SERDES_10G4_IP4_LN0_TXCLK	Input clock
88	DEV_SERDES_10G4_IP4_LN0_TXFCLK	Output clock
89	DEV_SERDES_10G4_IP4_LN0_TXMCLK	Output clock
90	DEV_SERDES_10G4_IP4_LN1_REFCLK	Output clock
91	DEV_SERDES_10G4_IP4_LN1_RXCLK	Output clock
92	DEV_SERDES_10G4_IP4_LN1_RXFCLK	Output clock
93	DEV_SERDES_10G4_IP4_LN1_TXCLK	Input clock
94	DEV_SERDES_10G4_IP4_LN1_TXFCLK	Output clock
95	DEV_SERDES_10G4_IP4_LN1_TXMCLK	Output clock
96	DEV_SERDES_10G4_IP4_LN2_REFCLK	Output clock
97	DEV_SERDES_10G4_IP4_LN2_RXCLK	Output clock
98	DEV_SERDES_10G4_IP4_LN2_RXFCLK	Output clock
99	DEV_SERDES_10G4_IP4_LN2_TXCLK	Input clock
100	DEV_SERDES_10G4_IP4_LN2_TXFCLK	Output clock
101	DEV_SERDES_10G4_IP4_LN2_TXMCLK	Output clock
102	DEV_SERDES_10G4_IP4_LN3_REFCLK	Output clock
103	DEV_SERDES_10G4_IP4_LN3_RXCLK	Output clock
104	DEV_SERDES_10G4_IP4_LN3_RXFCLK	Output clock
105	DEV_SERDES_10G4_IP4_LN3_TXCLK	Input clock
106	DEV_SERDES_10G4_IP4_LN3_TXFCLK	Output clock
107	DEV_SERDES_10G4_IP4_LN3_TXMCLK	Output clock

Clocks for STM0 Device

Device: J784S4_DEV_STM0 (ID = 77)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_STM0_ATB_CLK	Input clock
1	DEV_STM0_CORE_CLK	Input clock
2	DEV_STM0_VBUSP_CLK	Input clock

Clocks for TIMER0 Device

Device: J784S4_DEV_TIMER0 (ID = 97)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER0_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER0_TIMER_PWM	Output clock
2	DEV_TIMER0_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
4	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
5	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
6	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
7	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
8	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
9	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
10	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
11	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
12	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
13	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
14	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
15	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
16	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
17	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
18	DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK

Clocks for TIMER1 Device

Device: J784S4_DEV_TIMER1 (ID = 98)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER1_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER1_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1	Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
4	DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM	Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK

Clocks for TIMER10 Device

Device: J784S4_DEV_TIMER10 (ID = 107)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER10_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER10_TIMER_PWM	Output clock
2	DEV_TIMER10_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
4	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
5	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
6	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
7	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
8	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
9	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
10	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
11	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
12	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
13	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
14	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
15	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
16	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
17	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
18	DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK

Clocks for TIMER11 Device

Device: J784S4_DEV_TIMER11 (ID = 108)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER11_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER11_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11	Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
4	DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM	Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK

Clocks for TIMER11_CLKSEL_VD Device

Device: J784S4_DEV_TIMER11_CLKSEL_VD (ID = 427)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER11_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
2	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
3	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
4	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
5	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
6	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
7	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
8	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
9	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
10	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
11	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
12	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
13	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
14	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
15	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
16	DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK

Clocks for TIMER12 Device

Device: J784S4_DEV_TIMER12 (ID = 109)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER12_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER12_TIMER_PWM	Output clock
2	DEV_TIMER12_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
4	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
5	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
6	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
7	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
8	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
9	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
10	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
11	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
12	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
13	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
14	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
15	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
16	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
17	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
18	DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK

Clocks for TIMER13 Device

Device: J784S4_DEV_TIMER13 (ID = 110)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER13_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER13_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13	Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK
4	DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM	Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK

Clocks for TIMER13_CLKSEL_VD Device

Device: J784S4_DEV_TIMER13_CLKSEL_VD (ID = 428)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER13_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
2	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
3	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
4	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
5	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
6	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
7	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
8	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
9	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
10	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
11	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
12	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
13	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
14	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
15	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
16	DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK

Clocks for TIMER14 Device

Device: J784S4_DEV_TIMER14 (ID = 111)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER14_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER14_TIMER_PWM	Output clock
2	DEV_TIMER14_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
4	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
5	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
6	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
7	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
8	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
9	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
10	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
11	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
12	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
13	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
14	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
15	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
16	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
17	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
18	DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK

Clocks for TIMER15 Device

Device: J784S4_DEV_TIMER15 (ID = 112)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER15_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER15_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15	Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK
4	DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM	Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK

Clocks for TIMER15_CLKSEL_VD Device

Device: J784S4_DEV_TIMER15_CLKSEL_VD (ID = 429)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER15_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
2	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
3	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
4	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
5	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
6	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
7	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
8	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
9	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
10	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
11	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
12	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
13	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
14	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
15	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
16	DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK

Clocks for TIMER16 Device

Device: J784S4_DEV_TIMER16 (ID = 113)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER16_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER16_TIMER_PWM	Output clock
2	DEV_TIMER16_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16	Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
4	DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0	Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK

Clocks for TIMER17 Device

Device: J784S4_DEV_TIMER17 (ID = 114)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER17_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER17_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0	Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK
4	DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM	Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK

Clocks for TIMER17_CLKSEL_VD Device

Device: J784S4_DEV_TIMER17_CLKSEL_VD (ID = 430)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER17_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
2	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
3	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
4	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
5	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
6	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
7	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
8	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
9	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
10	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
11	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
12	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
13	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
14	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
15	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
16	DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK

Clocks for TIMER18 Device

Device: J784S4_DEV_TIMER18 (ID = 115)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER18_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER18_TIMER_PWM	Output clock
2	DEV_TIMER18_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18	Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
4	DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0	Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK

Clocks for TIMER19 Device

Device: J784S4_DEV_TIMER19 (ID = 116)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER19_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER19_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0	Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK
4	DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM	Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK

Clocks for TIMER19_CLKSEL_VD Device

Device: J784S4_DEV_TIMER19_CLKSEL_VD (ID = 431)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER19_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
2	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
3	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
4	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
5	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
6	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
7	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
8	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
9	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
10	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
11	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
12	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
13	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
14	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
15	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
16	DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK

Clocks for TIMER1_CLKSEL_VD Device

Device: J784S4_DEV_TIMER1_CLKSEL_VD (ID = 422)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER1_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
2	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
3	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
4	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
5	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
6	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
7	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
8	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
9	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
10	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
11	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
12	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
13	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
14	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
15	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
16	DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK

Clocks for TIMER2 Device

Device: J784S4_DEV_TIMER2 (ID = 99)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER2_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER2_TIMER_PWM	Output clock
2	DEV_TIMER2_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
4	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
5	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
6	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
7	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
8	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
9	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
10	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
11	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
12	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
13	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
14	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
15	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
16	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
17	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
18	DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK

Clocks for TIMER3 Device

Device: J784S4_DEV_TIMER3 (ID = 100)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER3_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER3_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3	Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
4	DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM	Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK

Clocks for TIMER3_CLKSEL_VD Device

Device: J784S4_DEV_TIMER3_CLKSEL_VD (ID = 423)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER3_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
2	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
3	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
4	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
5	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
6	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
7	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
8	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
9	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
10	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
11	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
12	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
13	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
14	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
15	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
16	DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK

Clocks for TIMER4 Device

Device: J784S4_DEV_TIMER4 (ID = 101)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER4_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER4_TIMER_PWM	Output clock
2	DEV_TIMER4_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
4	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
5	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
6	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
7	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
8	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
9	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
10	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
11	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
12	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
13	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
14	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
15	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
16	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
17	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
18	DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK

Clocks for TIMER5 Device

Device: J784S4_DEV_TIMER5 (ID = 102)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER5_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER5_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5	Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
4	DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM	Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK

Clocks for TIMER5_CLKSEL_VD Device

Device: J784S4_DEV_TIMER5_CLKSEL_VD (ID = 424)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER5_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
2	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
3	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
4	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
5	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
6	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
7	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
8	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
9	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
10	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
11	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
12	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
13	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
14	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
15	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
16	DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK

Clocks for TIMER6 Device

Device: J784S4_DEV_TIMER6 (ID = 103)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER6_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER6_TIMER_PWM	Output clock
2	DEV_TIMER6_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
4	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
5	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
6	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
7	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
8	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
9	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
10	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
11	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
12	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
13	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
14	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
15	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
16	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
17	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
18	DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK

Clocks for TIMER7 Device

Device: J784S4_DEV_TIMER7 (ID = 104)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER7_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER7_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7	Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
4	DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM	Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK

Clocks for TIMER7_CLKSEL_VD Device

Device: J784S4_DEV_TIMER7_CLKSEL_VD (ID = 425)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER7_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
2	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
3	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
4	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
5	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
6	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
7	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
8	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
9	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
10	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
11	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
12	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
13	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
14	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
15	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
16	DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK

Clocks for TIMER8 Device

Device: J784S4_DEV_TIMER8 (ID = 105)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER8_TIMER_HCLK_CLK	Input clock
1	DEV_TIMER8_TIMER_PWM	Output clock
2	DEV_TIMER8_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
4	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
5	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
6	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
7	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
8	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
9	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
10	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
11	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
12	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
13	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
14	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
15	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
16	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
17	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
18	DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK

Clocks for TIMER9 Device

Device: J784S4_DEV_TIMER9 (ID = 106)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER9_TIMER_HCLK_CLK	Input clock
2	DEV_TIMER9_TIMER_TCLK_CLK	Input muxed clock
3	DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9	Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
4	DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM	Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK

Clocks for TIMER9_CLKSEL_VD Device

Device: J784S4_DEV_TIMER9_CLKSEL_VD (ID = 426)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMER9_CLKSEL_VD_CLK	Input muxed clock
1	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
2	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
3	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
4	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
5	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
6	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
7	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
8	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
9	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
10	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
11	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
12	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
13	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
14	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
15	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
16	DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK	Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK

Clocks for TIMESYNC_INTRTR0 Device

Device: J784S4_DEV_TIMESYNC_INTRTR0 (ID = 176)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_TIMESYNC_INTRTR0_INTR_CLK	Input clock

Clocks for UART0 Device

Device: J784S4_DEV_UART0 (ID = 146)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART0_FCLK_CLK	Input clock
3	DEV_UART0_VBUSP_CLK	Input clock

Clocks for UART1 Device

Device: J784S4_DEV_UART1 (ID = 388)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART1_FCLK_CLK	Input clock
3	DEV_UART1_VBUSP_CLK	Input clock

Clocks for UART2 Device

Device: J784S4_DEV_UART2 (ID = 389)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART2_FCLK_CLK	Input clock
3	DEV_UART2_VBUSP_CLK	Input clock

Clocks for UART3 Device

Device: J784S4_DEV_UART3 (ID = 390)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART3_FCLK_CLK	Input clock
3	DEV_UART3_VBUSP_CLK	Input clock

Clocks for UART4 Device

Device: J784S4_DEV_UART4 (ID = 391)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART4_FCLK_CLK	Input clock
3	DEV_UART4_VBUSP_CLK	Input clock

Clocks for UART5 Device

Device: J784S4_DEV_UART5 (ID = 392)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART5_FCLK_CLK	Input clock
3	DEV_UART5_VBUSP_CLK	Input clock

Clocks for UART6 Device

Device: J784S4_DEV_UART6 (ID = 393)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART6_FCLK_CLK	Input clock
3	DEV_UART6_VBUSP_CLK	Input clock

Clocks for UART7 Device

Device: J784S4_DEV_UART7 (ID = 394)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART7_FCLK_CLK	Input clock
3	DEV_UART7_VBUSP_CLK	Input clock

Clocks for UART8 Device

Device: J784S4_DEV_UART8 (ID = 395)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART8_FCLK_CLK	Input clock
3	DEV_UART8_VBUSP_CLK	Input clock

Clocks for UART9 Device

Device: J784S4_DEV_UART9 (ID = 396)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_UART9_FCLK_CLK	Input clock
3	DEV_UART9_VBUSP_CLK	Input clock

Clocks for UFS0 Device

Device: J784S4_DEV_UFS0 (ID = 387)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
1	DEV_UFS0_UFSHCI_HCLK_CLK	Input clock
3	DEV_UFS0_UFSHCI_MCLK_CLK	Input muxed clock
4	DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK
5	DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK
6	DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK	Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK
7	DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT	Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK
8	DEV_UFS0_UFSHCI_MPHY_REFCLK	Output clock
23	DEV_UFS0_UFSHCI_MPHY_TX_REF_SYMBOLCLK	Output clock
24	DEV_UFS0_UFSHCI_MPHY_M31_VCO_19P2M_CLK	Output clock
25	DEV_UFS0_UFSHCI_MPHY_M31_VCO_26M_CLK	Output clock

Clocks for USB0 Device

Device: J784S4_DEV_USB0 (ID = 398)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_USB0_ACLK_CLK	Input clock
1	DEV_USB0_BUF_CLK	Input clock
2	DEV_USB0_CLK_LPM_CLK	Input clock
3	DEV_USB0_PCLK_CLK	Input clock
4	DEV_USB0_PIPE_REFCLK	Input muxed clock
5	DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_REFCLK	Parent input clock option to DEV_USB0_PIPE_REFCLK
6	DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_REFCLK	Parent input clock option to DEV_USB0_PIPE_REFCLK
7	DEV_USB0_PIPE_RXCLK	Input muxed clock
8	DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXCLK	Parent input clock option to DEV_USB0_PIPE_RXCLK
9	DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXCLK	Parent input clock option to DEV_USB0_PIPE_RXCLK
10	DEV_USB0_PIPE_RXFCLK	Input muxed clock
11	DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXFCLK	Parent input clock option to DEV_USB0_PIPE_RXFCLK
12	DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXFCLK	Parent input clock option to DEV_USB0_PIPE_RXFCLK
13	DEV_USB0_PIPE_TXCLK	Output clock
14	DEV_USB0_PIPE_TXFCLK	Input muxed clock
15	DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXFCLK	Parent input clock option to DEV_USB0_PIPE_TXFCLK
16	DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXFCLK	Parent input clock option to DEV_USB0_PIPE_TXFCLK
17	DEV_USB0_PIPE_TXMCLK	Input muxed clock
18	DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXMCLK	Parent input clock option to DEV_USB0_PIPE_TXMCLK
19	DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXMCLK	Parent input clock option to DEV_USB0_PIPE_TXMCLK
20	DEV_USB0_USB2_APB_PCLK_CLK	Input clock
21	DEV_USB0_USB2_REFCLOCK_CLK	Input muxed clock
22	DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
23	DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT	Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
28	DEV_USB0_USB2_TAP_TCK	Input clock

Clocks for VPAC0 Device

Device: J784S4_DEV_VPAC0 (ID = 399)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_VPAC0_LDC0_CLK_CLK	Input clock
1	DEV_VPAC0_MAIN_CLK	Input muxed clock
2	DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK	Parent input clock option to DEV_VPAC0_MAIN_CLK
3	DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK	Parent input clock option to DEV_VPAC0_MAIN_CLK
4	DEV_VPAC0_MSC_CLK	Input clock
5	DEV_VPAC0_NF_CLK_CLK	Input clock
6	DEV_VPAC0_PSIL_LEAF_CLK	Input clock
7	DEV_VPAC0_VISS0_CLK_CLK	Input clock

Clocks for VPAC1 Device

Device: J784S4_DEV_VPAC1 (ID = 400)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_VPAC1_LDC0_CLK_CLK	Input clock
1	DEV_VPAC1_MAIN_CLK	Input muxed clock
2	DEV_VPAC1_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK	Parent input clock option to DEV_VPAC1_MAIN_CLK
3	DEV_VPAC1_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK	Parent input clock option to DEV_VPAC1_MAIN_CLK
4	DEV_VPAC1_MSC_CLK	Input clock
5	DEV_VPAC1_NF_CLK_CLK	Input clock
6	DEV_VPAC1_PSIL_LEAF_CLK	Input clock
7	DEV_VPAC1_VISS0_CLK_CLK	Input clock

Clocks for VUSR_DUAL0 Device

Device: J784S4_DEV_VUSR_DUAL0 (ID = 401)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_VUSR_DUAL0_V0_CLK	Input clock
1	DEV_VUSR_DUAL0_V0_RXFL_CLK	Output clock
2	DEV_VUSR_DUAL0_V0_RXPM_CLK	Input clock
3	DEV_VUSR_DUAL0_V0_TXFL_CLK	Input clock
4	DEV_VUSR_DUAL0_V0_TXPM_CLK	Output clock
5	DEV_VUSR_DUAL0_V1_CLK	Input clock
6	DEV_VUSR_DUAL0_V1_RXFL_CLK	Output clock
7	DEV_VUSR_DUAL0_V1_RXPM_CLK	Input clock
8	DEV_VUSR_DUAL0_V1_TXFL_CLK	Input clock
9	DEV_VUSR_DUAL0_V1_TXPM_CLK	Output clock
10	DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK	Input clock
11	DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK	Input clock
12	DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK	Input clock
13	DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK	Output clock
14	DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK	Input clock
15	DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK	Input clock
16	DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK	Input clock
17	DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK	Input clock
18	DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK	Input clock
19	DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK	Output clock
20	DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK	Input clock
21	DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK	Input clock
22	DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK	Input clock
23	DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK	Input clock
24	DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK	Input clock
25	DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK	Output clock
26	DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK	Input clock
27	DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK	Input clock
28	DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK	Input clock
29	DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK	Input clock
30	DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK	Input clock
31	DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK	Output clock
32	DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK	Input clock
33	DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK	Input clock

Clocks for WKUPMCU2MAIN_VD Device

This device has no defined clocks.

Clocks for WKUP_DDPA0 Device

Device: J784S4_DEV_WKUP_DDPA0 (ID = 211)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_DDPA0_DDPA_CLK	Input clock

Clocks for WKUP_ESM0 Device

Device: J784S4_DEV_WKUP_ESM0 (ID = 147)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_ESM0_CLK	Input clock

Clocks for WKUP_GPIO0 Device

Device: J784S4_DEV_WKUP_GPIO0 (ID = 167)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_GPIO0_MMR_CLK	Input clock

Clocks for WKUP_GPIO1 Device

Device: J784S4_DEV_WKUP_GPIO1 (ID = 168)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_GPIO1_MMR_CLK	Input clock

Clocks for WKUP_GPIOMUX_INTRTR0 Device

Device: J784S4_DEV_WKUP_GPIOMUX_INTRTR0 (ID = 177)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK	Input clock

Clocks for WKUP_HSM0 Device

Device: J784S4_DEV_WKUP_HSM0 (ID = 371)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_HSM0_DAP_CLK	Input clock

Clocks for WKUP_I2C0 Device

Device: J784S4_DEV_WKUP_I2C0 (ID = 279)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_I2C0_CLK	Input clock
1	DEV_WKUP_I2C0_PISCL	Input clock
2	DEV_WKUP_I2C0_PISYS_CLK	Input muxed clock
3	DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK	Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK
4	DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK
5	DEV_WKUP_I2C0_PORSCL	Output clock

Clocks for WKUP_J7AM_WAKEUP_16FF0 Device

Device: J784S4_DEV_WKUP_J7AM_WAKEUP_16FF0 (ID = 9)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK	Input clock
1	DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK	Output clock
2	DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK	Output clock

Clocks for WKUP_PORZ_SYNC0 Device

Device: J784S4_DEV_WKUP_PORZ_SYNC0 (ID = 175)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK	Input clock

Clocks for WKUP_PSC0 Device

Device: J784S4_DEV_WKUP_PSC0 (ID = 178)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_PSC0_CLK	Input clock
1	DEV_WKUP_PSC0_SLOW_CLK	Input clock

Clocks for WKUP_SMS0 Device

This device has no defined clocks.

Clocks for WKUP_UART0 Device

Device: J784S4_DEV_WKUP_UART0 (ID = 397)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_UART0_FCLK_CLK	Input muxed clock
1	DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0	Parent input clock option to DEV_WKUP_UART0_FCLK_CLK
2	DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT	Parent input clock option to DEV_WKUP_UART0_FCLK_CLK
7	DEV_WKUP_UART0_VBUSP_CLK	Input clock

Clocks for WKUP_VTM0 Device

Device: J784S4_DEV_WKUP_VTM0 (ID = 243)

Following is a mapping of Clocks IDs to function:

Clock ID	Name	Function
0	DEV_WKUP_VTM0_FIX_REF2_CLK	Input clock
1	DEV_WKUP_VTM0_FIX_REF_CLK	Input clock
2	DEV_WKUP_VTM0_VBUSP_CLK	Input clock