Instance: CCFG
Component: CCFG
Base address: 0x50000000
Customer configuration area (CCFG)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xFFFF FFFF |
0x0000 0000 |
0x5000 0000 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0004 |
0x5000 0004 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0008 |
0x5000 0008 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 000C |
0x5000 000C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0010 |
0x5000 0010 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0014 |
0x5000 0014 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0018 |
0x5000 0018 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 001C |
0x5000 001C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0020 |
0x5000 0020 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0024 |
0x5000 0024 |
|
RO |
32 |
0xC5FF FFFF |
0x0000 0028 |
0x5000 0028 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 002C |
0x5000 002C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0030 |
0x5000 0030 |
|
RO |
32 |
0xFFC5 C5C5 |
0x0000 0034 |
0x5000 0034 |
|
RO |
32 |
0xFFC5 C5C5 |
0x0000 0038 |
0x5000 0038 |
|
RO |
32 |
0xFFC5 C5C5 |
0x0000 003C |
0x5000 003C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0040 |
0x5000 0040 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0044 |
0x5000 0044 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0048 |
0x5000 0048 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 004C |
0x5000 004C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0050 |
0x5000 0050 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0054 |
0x5000 0054 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0058 |
0x5000 0058 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 005C |
0x5000 005C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0064 |
0x5000 0064 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0068 |
0x5000 0068 |
|
RO |
32 |
0x0FFF FFFF |
0x0000 006C |
0x5000 006C |
|
RO |
32 |
0x0FFF FFFF |
0x0000 0070 |
0x5000 0070 |
|
RO |
32 |
0x0FFF FFFF |
0x0000 0074 |
0x5000 0074 |
|
RO |
32 |
0x0FFF FFFF |
0x0000 0078 |
0x5000 0078 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x5000 0000 | Instance | 0x5000 0000 |
Description | CCFG Size and Disable Flags | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | SIZE_OF_CCFG | Total size of CCFG in bytes. | RO | 0xFFFF | ||
15:4 | DISABLE_FLAGS | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFFF | ||
3 | DIS_TCXO | Deprecated. Must be set to 1. | RO | 1 | ||
2 | DIS_GPRAM | Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 0: GPRAM is enabled and hence CACHE disabled. 1: GPRAM is disabled and instead CACHE is enabled (default). Notes: - Disabling CACHE will reduce CPU execution speed (up to 60%). - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled. See: VIMS:CTL.MODE |
RO | 1 | ||
1 | DIS_ALT_DCDC_SETTING | Disable alternate DC/DC settings. 0: Enable alternate DC/DC settings. 1: Disable alternate DC/DC settings. See: MODE_CONF_1.ALT_DCDC_VMIN MODE_CONF_1.ALT_DCDC_DITHER_EN MODE_CONF_1.ALT_DCDC_IPEAK NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 1 | ||
0 | DIS_XOSC_OVR | Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START |
RO | 1 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x5000 0004 | Instance | 0x5000 0004 |
Description | Mode Configuration 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:28 | VDDR_TRIM_SLEEP_DELTA | Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. 0x8 (-8) : Delta = -7 ... 0xF (-1) : Delta = 0 0x0 (0) : Delta = +1 ... 0x7 (7) : Delta = +8 |
RO | 0xF | |||||||||||||||||
27 | DCDC_RECHARGE | DC/DC during recharge in powerdown. 0: Use the DC/DC during recharge in powerdown. 1: Do not use the DC/DC during recharge in powerdown (default). NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 1 | |||||||||||||||||
26 | DCDC_ACTIVE | DC/DC in active mode. 0: Use the DC/DC during active mode. 1: Do not use the DC/DC during active mode (default). NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 1 | |||||||||||||||||
25 | VDDR_EXT_LOAD | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 1 | |||||||||||||||||
24 | VDDS_BOD_LEVEL | VDDS BOD level. 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum PA output power on CC13xx). 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). |
RO | 1 | |||||||||||||||||
23:22 | SCLK_LF_OPTION | Select source for SCLK_LF.
|
RO | 0b11 | |||||||||||||||||
21 | VDDR_TRIM_SLEEP_TC | 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time standby mode is entered. This improves low-temperature RCOSC_LF frequency stability in standby mode. When temperature compensation is performed, the delta is calculates this way: Delta = max (delta, min(8, floor(62-temp)/8)) Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C. |
RO | 1 | |||||||||||||||||
20 | RTC_COMP | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 1 | |||||||||||||||||
19:18 | XOSC_FREQ | Selects which high frequency oscillator is used (required for radio usage).
|
RO | 0b11 | |||||||||||||||||
17 | XOSC_CAP_MOD | Enable modification (delta) to XOSC cap-array. Value specified in XOSC_CAPARRAY_DELTA. 0: Apply cap-array delta 1: Do not apply cap-array delta (default) |
RO | 1 | |||||||||||||||||
16 | HF_COMP | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 1 | |||||||||||||||||
15:8 | XOSC_CAPARRAY_DELTA | Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. Enabled by XOSC_CAP_MOD. | RO | 0xFF | |||||||||||||||||
7:0 | VDDR_CAP | Unsigned 8-bit integer, representing the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby. NOTE! If using the following functions this field must be configured (used by TI RTOS): SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() |
RO | 0xFF |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x5000 0008 | Instance | 0x5000 0008 |
Description | Mode Configuration 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | TCXO_TYPE | Selects the TCXO type. 0: CMOS type. Internal common-mode bias will not be enabled. 1: Clipped-sine type. Internal common-mode bias will be enabled when TCXO is used. Bit field value is only valid if MODE_CONF.XOSC_FREQ=0. |
RO | 1 | ||
30:24 | TCXO_MAX_START | Maximum TCXO startup time in units of 100us. Bit field value is only valid if MODE_CONF.XOSC_FREQ=0. |
RO | 0b111 1111 | ||
23:20 | ALT_DCDC_VMIN | Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Voltage = (28 + ALT_DCDC_VMIN) / 16. 0: 1.75V 1: 1.8125V ... 14: 2.625V 15: 2.6875V NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 0xF | ||
19 | ALT_DCDC_DITHER_EN | Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 0: Dither disable 1: Dither enable |
RO | 1 | ||
18:16 | ALT_DCDC_IPEAK | Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external inductor! 0: 46mA (min) ... 4: 70mA ... 7: 87mA (max) |
RO | 0b111 | ||
15:12 | DELTA_IBIAS_INIT | Signed delta value for IBIAS_INIT. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT |
RO | 0xF | ||
11:8 | DELTA_IBIAS_OFFSET | Signed delta value for IBIAS_OFFSET. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET |
RO | 0xF | ||
7:0 | XOSC_MAX_START | Unsigned value of maximum XOSC startup time (worst case) in units of 100us. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. | RO | 0xFF |
Address Offset | 0x0000 000C | ||
Physical Address | 0x5000 000C | Instance | 0x5000 000C |
Description | Voltage Load 0 Enabled by MODE_CONF.VDDR_EXT_LOAD. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | VDDR_EXT_TP45 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
23:16 | VDDR_EXT_TP25 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
15:8 | VDDR_EXT_TP5 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
7:0 | VDDR_EXT_TM15 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x5000 0010 | Instance | 0x5000 0010 |
Description | Voltage Load 1 Enabled by MODE_CONF.VDDR_EXT_LOAD. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | VDDR_EXT_TP125 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
23:16 | VDDR_EXT_TP105 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
15:8 | VDDR_EXT_TP85 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
7:0 | VDDR_EXT_TP65 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x5000 0014 | Instance | 0x5000 0014 |
Description | Extern LF clock configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DIO | Unsigned integer, selecting the DIO to supply external 32 kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO will be marked as reserved by the pin driver (TI-RTOS environment) and hence not selectable for other usage. | RO | 0xFF | ||
23:0 | RTC_INCREMENT | Unsigned integer, defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) | RO | 0xFF FFFF |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x5000 0018 | Instance | 0x5000 0018 |
Description | IEEE MAC Address 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[31:0] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 001C | ||
Physical Address | 0x5000 001C | Instance | 0x5000 001C |
Description | IEEE MAC Address 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[63:32] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x5000 0020 | Instance | 0x5000 0020 |
Description | IEEE BLE Address 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[31:0] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x5000 0024 | Instance | 0x5000 0024 |
Description | IEEE BLE Address 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[63:32] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x5000 0028 | Instance | 0x5000 0028 |
Description | Bootloader Configuration Configures the functionality of the ROM boot loader. If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image is present in flash. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | BOOTLOADER_ENABLE | Bootloader enable. Boot loader can be accessed if IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and conditions for boot loader backdoor are met). 0xC5: Boot loader is enabled. Any other value: Boot loader is disabled. |
RO | 0xC5 | ||
23:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
16 | BL_LEVEL | Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field. 0: Active low. 1: Active high. |
RO | 1 | ||
15:8 | BL_PIN_NUMBER | DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field. | RO | 0xFF | ||
7:0 | BL_ENABLE | Enables the boot loader backdoor. 0xC5: Boot loader backdoor is enabled. Any other value: Boot loader backdoor is disabled. NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader backdoor is enabled. |
RO | 0xFF |
Address Offset | 0x0000 002C | ||
Physical Address | 0x5000 002C | Instance | 0x5000 002C |
Description | Erase Configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:9 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 1111 1111 | ||
8 | CHIP_ERASE_DIS_N | Chip erase. This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD. A successful chip erase operation will force the content of the flash main bank back to the state as it was when delivered by TI. 0: Disable. Any chip erase request detected during boot will be ignored. 1: Enable. Any chip erase request detected during boot will be performed by the boot FW. |
RO | 1 | ||
7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
0 | BANK_ERASE_DIS_N | Bank erase. This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE). A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration bits in CCFG. 0: Disable the boot loader bank erase function. 1: Enable the boot loader bank erase function. |
RO | 1 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x5000 0030 | Instance | 0x5000 0030 |
Description | Erase Configuration 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 1111 1111 1111 1111 | ||
0 | WEPROT_CCFG_N | WriteErase protect the CCFG sector Setting this bit = 0 will set FLASH:WEPROT_AUX_BY1.WEPROT_B0_CCFG_BY1 = 1 during boot and hence WriteErase protect the CCFG |
RO | 1 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x5000 0034 | Instance | 0x5000 0034 |
Description | TI Options | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:16 | C_FA_DIS | Option to disable failure analysis without customer password. If C_FA_DIS != 0xC5, CKEY must be provided to TI for failure analysis to be possible. 0xC5: Failure analysis without customer password is enabled All other values: Failure analysis without customer password is disabled |
RO | 0xC5 | ||
15:8 | IDAU_CFG_ENABLE | IDAU configuration. 0xC5: Disable IDAU configuration controlled by TRUSTZONE_FLASH_CFG and TRUSTZONE_SRAM_CFG. All other values: Enable IDAU configuration controlled by TRUSTZONE_FLASH_CFG and TRUSTZONE_SRAM_CFG. |
RO | 0xC5 | ||
7:0 | TI_FA_ENABLE | TI Failure Analysis. 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) option with the unlock code. All other values: Disable the functionality of unlocking the TI FA option with the unlock code. |
RO | 0xC5 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x5000 0038 | Instance | 0x5000 0038 |
Description | Test Access Points Enable 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:16 | CPU_DAP_ENABLE | Enable CPU DAP. 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM boot FW. Any other value: Main CPU DAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
15:8 | PWRPROF_TAP_ENABLE | Enable PWRPROF TAP. 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PWRPROF TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
7:0 | TEST_TAP_ENABLE | Enable Test TAP. 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: TEST TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x5000 003C | Instance | 0x5000 003C |
Description | Test Access Points Enable 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:16 | PBIST2_TAP_ENABLE | Enable PBIST2 TAP. 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST2 TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
15:8 | PBIST1_TAP_ENABLE | Enable PBIST1 TAP. 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST1 TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
7:0 | AON_TAP_ENABLE | Enable AON TAP 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: AON TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x5000 0040 | Instance | 0x5000 0040 |
Description | Image Valid | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | IMAGE_VALID | This field must have the address value of the start of the flash vector table in order to enable the boot FW in ROM to transfer control to a flash image. Any illegal vector table start address value will force the boot FW in ROM to transfer control to the serial boot loader in ROM. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x5000 0044 | Instance | 0x5000 0044 |
Description | Protect Sectors 0-31 Each bit write protects one 2KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector WriteErase protect. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | WEPROT_SEC_31_N | 0: Sector protected | RO | 1 | ||
30 | WEPROT_SEC_30_N | 0: Sector protected | RO | 1 | ||
29 | WEPROT_SEC_29_N | 0: Sector protected | RO | 1 | ||
28 | WEPROT_SEC_28_N | 0: Sector protected | RO | 1 | ||
27 | WEPROT_SEC_27_N | 0: Sector protected | RO | 1 | ||
26 | WEPROT_SEC_26_N | 0: Sector protected | RO | 1 | ||
25 | WEPROT_SEC_25_N | 0: Sector protected | RO | 1 | ||
24 | WEPROT_SEC_24_N | 0: Sector protected | RO | 1 | ||
23 | WEPROT_SEC_23_N | 0: Sector protected | RO | 1 | ||
22 | WEPROT_SEC_22_N | 0: Sector protected | RO | 1 | ||
21 | WEPROT_SEC_21_N | 0: Sector protected | RO | 1 | ||
20 | WEPROT_SEC_20_N | 0: Sector protected | RO | 1 | ||
19 | WEPROT_SEC_19_N | 0: Sector protected | RO | 1 | ||
18 | WEPROT_SEC_18_N | 0: Sector protected | RO | 1 | ||
17 | WEPROT_SEC_17_N | 0: Sector protected | RO | 1 | ||
16 | WEPROT_SEC_16_N | 0: Sector protected | RO | 1 | ||
15 | WEPROT_SEC_15_N | 0: Sector protected | RO | 1 | ||
14 | WEPROT_SEC_14_N | 0: Sector protected | RO | 1 | ||
13 | WEPROT_SEC_13_N | 0: Sector protected | RO | 1 | ||
12 | WEPROT_SEC_12_N | 0: Sector protected | RO | 1 | ||
11 | WEPROT_SEC_11_N | 0: Sector protected | RO | 1 | ||
10 | WEPROT_SEC_10_N | 0: Sector protected | RO | 1 | ||
9 | WEPROT_SEC_9_N | 0: Sector protected | RO | 1 | ||
8 | WEPROT_SEC_8_N | 0: Sector protected | RO | 1 | ||
7 | WEPROT_SEC_7_N | 0: Sector protected | RO | 1 | ||
6 | WEPROT_SEC_6_N | 0: Sector protected | RO | 1 | ||
5 | WEPROT_SEC_5_N | 0: Sector protected | RO | 1 | ||
4 | WEPROT_SEC_4_N | 0: Sector protected | RO | 1 | ||
3 | WEPROT_SEC_3_N | 0: Sector protected | RO | 1 | ||
2 | WEPROT_SEC_2_N | 0: Sector protected | RO | 1 | ||
1 | WEPROT_SEC_1_N | 0: Sector protected | RO | 1 | ||
0 | WEPROT_SEC_0_N | 0: Sector protected | RO | 1 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x5000 0048 | Instance | 0x5000 0048 |
Description | Spare register for WriteErase configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED | Reserved | RO | 0xFFFF FFFF |
Address Offset | 0x0000 004C | ||
Physical Address | 0x5000 004C | Instance | 0x5000 004C |
Description | Spare register for WriteErase configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED | Reserved | RO | 0xFFFF FFFF |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x5000 0050 | Instance | 0x5000 0050 |
Description | Spare register for WriteErase configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED | Reserved | RO | 0xFFFF FFFF |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x5000 0054 | Instance | 0x5000 0054 |
Description | Trustzone configuration register for flash | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:10 | NSADDR_BOUNDARY | Value will be written to PRCM:NVMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5. | RO | 0b111 1111 | ||
9:0 | NSCADDR_BOUNDARY | Value will be written to PRCM:NVMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5. | RO | 0b11 1111 1111 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x5000 0058 | Instance | 0x5000 0058 |
Description | Trustzone configuration register for MCU SRAM | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 1111 1111 1111 | ||
17:9 | NSADDR_BOUNDARY | Value will be written to PRCM:SRAMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5. | RO | 0b1 1111 1111 | ||
8:0 | NSCADDR_BOUNDARY | Value will be written to PRCM:SRAMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5. | RO | 0b1 1111 1111 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x5000 005C | Instance | 0x5000 005C |
Description | Configuration register for MCU SRAM | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | MEM_SEL | Value will be written to SRAM_MMR:MEM_CTL.MEM_SEL by ROM boot FW | RO | 0xFF FFFF | ||
7:1 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
0 | PARITY_DIS | Value will be inverted and then written to PRCM:MCUSRAMCFG.PARITY_EN by ROM boot FW | RO | 1 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x5000 0064 | Instance | 0x5000 0064 |
Description | Configuration register for MCU CPU lock options | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:5 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 1111 1111 1111 | ||
4 | LOCKNSVTOR_N | Value will be inverted and written to PRCM:CPULOCK.LOCKNSVTOR by ROM boot FW | RO | 1 | ||
3 | LOCKSVTAIRCR_N | Value will be inverted and written to PRCM:CPULOCK.LOCKSVTAIRCR by ROM boot FW | RO | 1 | ||
2 | LOCKSAU_N | Value will be inverted and written to PRCM:CPULOCK.LOCKSAU by ROM boot FW | RO | 1 | ||
1 | LOCKNSMPU_N | Value will be inverted and written to PRCM:CPULOCK.LOCKNSMPU by ROM boot FW | RO | 1 | ||
0 | LOCKSMPU_N | Value will be inverted and written to PRCM:CPULOCK.LOCKSMPU by ROM boot FW | RO | 1 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x5000 0068 | Instance | 0x5000 0068 |
Description | Configuration register for debug authentication | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFFF FFFF | ||
3 | INTSPNIDEN | Value will be written to CPU_DCB:DAUTHCTRL.INTSPNIDEN by ROM boot FW | RO | 1 | ||
2 | SPNIDENSEL | Value will be written to CPU_DCB:DAUTHCTRL.SPNIDENSEL by ROM boot FW | RO | 1 | ||
1 | INTSPIDEN | Value will be written to CPU_DCB:DAUTHCTRL.INTSPIDEN by ROM boot FW | RO | 1 | ||
0 | SPIDENSEL | Value will be written to CPU_DCB:DAUTHCTRL.SPIDENSEL by ROM boot FW | RO | 1 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x5000 006C | Instance | 0x5000 006C |
Description | Customer key | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | KEY | Bit[31:0] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5. | RO | 0x0FFF FFFF |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x5000 0070 | Instance | 0x5000 0070 |
Description | Customer key | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | KEY | Bit[63:32] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5. | RO | 0x0FFF FFFF |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x5000 0074 | Instance | 0x5000 0074 |
Description | Customer key | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | KEY | Bit[95:64] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5. | RO | 0x0FFF FFFF |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x5000 0078 | Instance | 0x5000 0078 |
Description | Customer key | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | KEY | Bit[127:96] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5. | RO | 0x0FFF FFFF |
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