Instance: CPU_DCB
Component: CPU_DCB
Base address: 0xE000EDE0
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0b0000 0000 0000 00X0 0000 0000 0000 0000 |
0x0000 0010 |
0xE000 EDF0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 EDF4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 EDF8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0xE000 EDFC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 EE04 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 EE08 |
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 EDF0 | Instance | 0xE000 EDF0 |
| Description | Controls halting debug | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:27 | RESERVED27 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | ||
| 26 | S_RESTART_ST | Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request | RO | 0 | ||
| 25 | S_RESET_ST | Indicates whether the PE has been reset since the last read of the DHCSR | RO | 0 | ||
| 24 | S_RETIRE_ST | Set to 1 every time the PE retires one of more instructions | RO | 0 | ||
| 23:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 20 | S_SDE | Indicates whether Secure invasive debug is allowed | RO | 0 | ||
| 19 | S_LOCKUP | Indicates whether the PE is in Lockup state | RO | 0 | ||
| 18 | S_SLEEP | Indicates whether the PE is sleeping | RO | 0 | ||
| 17 | S_HALT | Indicates whether the PE is in Debug state | RO | 0 | ||
| 31:16 | DBGKEY | A debugger must write 0xA05F to this field to enable write access to the remaining bits, otherwise the PE ignores the write access | WO | 0x0000 | ||
| 15:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 | ||
| 5 | C_SNAPSTALL | Allow imprecise entry to Debug state | RO | 0 | ||
| 4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 3 | C_MASKINTS | When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts | RW | 0 | ||
| 2 | C_STEP | Enable single instruction step | RW | 0 | ||
| 1 | C_HALT | PE enter Debug state halt request | RW | 0 | ||
| 0 | C_DEBUGEN | Enable Halting debug | RW | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 EDF4 | Instance | 0xE000 EDF4 |
| Description | With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
| 16 | REGWnR | Specifies the access type for the transfer | WO | 0 | ||
| 15:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| 6:0 | REGSEL | Specifies the general-purpose register, special-purpose register, or FP register to transfer | WO | 0b000 0000 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 EDF8 | Instance | 0xE000 EDF8 |
| Description | With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | DBGTMP | Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 EDFC | Instance | 0xE000 EDFC |
| Description | Manages vector catch behavior and DebugMonitor handling when debugging | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 24 | TRCENA | Global enable for all DWT and ITM features | RW | 0 | ||
| 23:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 20 | SDME | Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state | RO | 0 | ||
| 19 | MON_REQ | DebugMonitor semaphore bit | RO | 0 | ||
| 18 | MON_STEP | Enable DebugMonitor stepping | RO | 0 | ||
| 17 | MON_PEND | Sets or clears the pending state of the DebugMonitor exception | RO | 0 | ||
| 16 | MON_EN | Enable the DebugMonitor exception | RO | 0 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11 | VC_SFERR | SecureFault exception halting debug vector catch enable | RO | 0 | ||
| 10 | VC_HARDERR | HardFault exception halting debug vector catch enable | RW | 0 | ||
| 9 | VC_INTERR | Enable halting debug vector catch for faults during exception entry and return | RO | 0 | ||
| 8 | VC_BUSERR | BusFault exception halting debug vector catch enable | RO | 0 | ||
| 7 | VC_STATERR | Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception | RO | 0 | ||
| 6 | VC_CHKERR | Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error | RO | 0 | ||
| 5 | VC_NOCPERR | Enable halting debug trap on a UsageFault caused by an access to a coprocessor | RO | 0 | ||
| 4 | VC_MMERR | Enable halting debug trap on a MemManage exception | RO | 0 | ||
| 3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 0 | VC_CORERESET | Enable Reset Vector Catch. This causes a warm reset to halt a running system | RW | 0 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 EE04 | Instance | 0xE000 EE04 |
| Description | This register allows the external authentication interface to be overridden from software. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3 | INTSPNIDEN | Internal Secure non-invasive debug enable. Overrides the external Secure non-invasive debug authentication interface | RW | 0 | ||
| 2 | SPNIDENSEL | Secure non-invasive debug enable select. Selects between DAUTHCTRL and the external authentication interface for control of Secure non-invasive debug | RW | 0 | ||
| 1 | INTSPIDEN | Internal Secure invasive debug enable. Overrides the external Secure invasive debug authentication Interfaces. | RW | 0 | ||
| 0 | SPIDENSEL | Secure invasive debug enable select. Selects between DAUTHCTRL and the external authentication interface for control of Secure invasive debug. | RW | 0 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 EE08 | Instance | 0xE000 EE08 |
| Description | Provides control and status information for Secure debug | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
| 17 | CDSKEY | Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero | RW | 0 | ||
| 16 | CDS | This field indicates the current Security state of the processor | RW | 0 | ||
| 15:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
| 1 | SBRSEL | If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger | RW | 0 | ||
| 0 | SBRSELEN | Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger | RW | 0 | ||
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