AUX_SYSIF

Instance: AUX_SYSIF
Component: AUX_SYSIF
Base address: 0x400C6000

AUX System Interface (AUX_SYSIF) is responsible for:
- system resource requests, such as power supply and clock requests.
- configuration of AUX peripheral operational rates for AUX_ANAIF DAC state machine and AUX_TIMER01.
- configuration of event synchronization rate for AUX_EVCTL:EVSTAT2 and AUX_EVCTL:EVSTAT3.

Peripheral operational rate for AUX modules mentioned above can either be:
- SCE rate, which is configured in AON_PMCTL:AUXSCECLK.
- AUX bus rate, which equals SCE rate or SCLK_HF divided by two when MCU domain is active or AUX operational mode is active.

AUX_SYSIF also interfaces AON_RTC to enable read access to data and sub-second increment control of AON_RTC.

TOP:AUX_SYSIF Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
OPMODEREQ	RW	32	0x0000 0000	0x0000 0000	0x400C 6000
OPMODEACK	RO	32	0x0000 0000	0x0000 0004	0x400C 6004
EVSYNCRATE	RW	32	0x0000 0000	0x0000 0048	0x400C 6048
PEROPRATE	RW	32	0x0000 0000	0x0000 004C	0x400C 604C
ADCCLKCTL	RW	32	0x0000 0000	0x0000 0050	0x400C 6050
TDCCLKCTL	RW	32	0x0000 0000	0x0000 0054	0x400C 6054
TDCREFCLKCTL	RW	32	0x0000 0000	0x0000 0058	0x400C 6058
RTCSUBSECINC0	RW	32	0x0000 0000	0x0000 007C	0x400C 607C
RTCSUBSECINC1	RW	32	0x0000 0000	0x0000 0080	0x400C 6080
RTCSUBSECINCCTL	RW	32	0x0000 0000	0x0000 0084	0x400C 6084
RTCEVCLR	RW	32	0x0000 0000	0x0000 0090	0x400C 6090
TIMERHALT	RW	32	0x0000 0000	0x0000 00A0	0x400C 60A0
SWPWRPROF	RW	32	0x0000 0000	0x0000 00B4	0x400C 60B4

TOP:AUX_SYSIF Register Descriptions

TOP:AUX_SYSIF:OPMODEREQ

Address Offset	0x0000 0000
Physical Address	0x400C 6000	Instance	0x400C 6000
Description	Operational Mode Request AUX can operate in three operational modes. Each mode is associated with: - a SCE clock source or rate, given by AON_PMCTL:AUXSCECLK. This rate is termed SCE_RATE. - a system power supply state request. AUX can request powerdown (uLDO) or active (GLDO or DCDC) system power supply state. Follow these rules: - It is not allowed to change a request until it has been acknowledged through OPMODEACK. - A change in mode request must happen stepwise along this sequence, the direction is irrelevant: PDA - A - LP - PDLP. Failure to follow these rules might result in unexpected behavior and must be avoided.
Type	RW

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

1:0

REQ

AUX operational mode request.

Value	ENUM Name	Description
0x0	A	Active operational mode, characterized by: - Active system power supply state (GLDO or DCDC) request. - AON_PMCTL:AUXSCECLK.SRC sets the SCE clock frequency (SCE_RATE). - An active wakeup flag does not change operational mode.
0x1	LP	Lowpower operational mode, characterized by: - Powerdown system power supply state (uLDO) request. - SCE clock frequency (SCE_RATE) equals SCLK_MF. - An active wakeup flag does not change operational mode.
0x2	PDA	Powerdown operational mode with wakeup to active mode, characterized by: - Powerdown system power supply state (uLDO) request. - AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE). - An active wakeup flag overrides the operational mode externally to active (A) as long as the flag is set.
0x3	PDLP	Powerdown operational mode with wakeup to lowpower mode, characterized by: - Powerdown system power supply state (uLDO) request. - AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE). - An active wakeup flag overrides the operational mode externally to lowpower (LP) as long as the flag is set.

0b00

TOP:AUX_SYSIF:OPMODEACK

Address Offset	0x0000 0004
Physical Address	0x400C 6004	Instance	0x400C 6004
Description	Operational Mode Acknowledgement User must assume that the current operational mode is the one acknowledged.
Type	RO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

1:0

ACK

AUX operational mode acknowledgement.

Value	ENUM Name	Description
0x0	A	Active operational mode is acknowledged.
0x1	LP	Lowpower operational mode is acknowledged.
0x2	PDA	Powerdown operational mode with wakeup to active mode is acknowledged.
0x3	PDLP	Powerdown operational mode with wakeup to lowpower mode is acknowledged.

0b00

TOP:AUX_SYSIF:EVSYNCRATE

Address Offset	0x0000 0048
Physical Address	0x400C 6048	Instance	0x400C 6048
Description	Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus. Select AUX bus rate when system CPU uses the event. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by two when MCU domain is active.
Type	RW

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

AUX_COMPA_SYNC_RATE

Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event.

Value	ENUM Name	Description
0x0	SCE_RATE	SCE rate
0x1	BUS_RATE	AUX bus rate

AUX_COMPB_SYNC_RATE

Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event.

Value	ENUM Name	Description
0x0	SCE_RATE	SCE rate
0x1	BUS_RATE	AUX bus rate

RESERVED0

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

TOP:AUX_SYSIF:PEROPRATE

Address Offset	0x0000 004C
Physical Address	0x400C 604C	Instance	0x400C 604C
Description	Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate. Select AUX bus rate when system CPU uses such peripheral. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by 2 when MCU domain is active.
Type	RW

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x000 0000

ANAIF_DAC_OP_RATE

Select operational rate for AUX_ANAIF DAC sample clock state machine.

Value	ENUM Name	Description
0x0	SCE_RATE	SCE rate
0x1	BUS_RATE	AUX bus rate

TIMER01_OP_RATE

Select operational rate for AUX_TIMER01.

Value	ENUM Name	Description
0x0	SCE_RATE	SCE rate
0x1	BUS_RATE	AUX bus rate

1:0

RESERVED0

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00

TOP:AUX_SYSIF:ADCCLKCTL

Address Offset	0x0000 0050
Physical Address	0x400C 6050	Instance	0x400C 6050
Description	ADC Clock Control
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	ACK	Clock acknowledgement. 0: ADC clock is disabled. 1: ADC clock is enabled.	RO	0
0	REQ	ADC clock request. 0: Disable ADC clock. 1: Enable ADC clock. Only modify REQ when equal to ACK.	RW	0

TOP:AUX_SYSIF:TDCCLKCTL

Address Offset	0x0000 0054
Physical Address	0x400C 6054	Instance	0x400C 6054
Description	TDC Counter Clock Control Controls if the AUX_TDC counter clock source is enabled. These are the recommended steps to configure and request the counter clock: - Ensure that REQ=0 and ACK=0. - Configure clock source in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. - Read DDI_0_OSC:CTL0 to avoid a race condition between previous step and next step. - Set REQ=1 to request the clock. - Wait until ACK=1. After these steps ACK stays high until REQ=0. It is hence not recommended to reconfigure DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL when ACK=1. In this case, there will be no indication of when the new clock source selection is ready. These are the recommended steps to stop the counter clock: - Ensure that REQ=1 and ACK=1. - Set REQ=0 to stop the clock. - Wait until ACK=0.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	ACK	TDC counter clock acknowledgement. 0: TDC counter clock is disabled. 1: TDC counter clock is enabled.	RO	0
0	REQ	TDC counter clock request. 0: Disable TDC counter clock. 1: Enable TDC counter clock. Only modify REQ when equal to ACK.	RW	0

TOP:AUX_SYSIF:TDCREFCLKCTL

Address Offset	0x0000 0058
Physical Address	0x400C 6058	Instance	0x400C 6058
Description	TDC Reference Clock Control Controls if the AUX_TDC reference clock source is enabled. These are the recommended steps to configure and request the reference clock: - Ensure that REQ=0 and ACK=0. - Configure clock source in DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL. - Read DDI_0_OSC:CTL0 to avoid a race condition between previous step and next step. - Set REQ=1 to request the clock. - Wait until ACK=1. After these steps ACK stays high until REQ=0. It is hence not recommended to reconfigure DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL when ACK=1. In this case, there will be no indication of when the new clock source selection is ready. These are the recommended steps to stop the reference clock: - Ensure that REQ=1 and ACK=1. - Set REQ=0 to stop the clock. - Wait until ACK=0.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	ACK	TDC reference clock acknowledgement. 0: TDC reference clock is disabled. 1: TDC reference clock is enabled.	RO	0
0	REQ	TDC reference clock request. 0: Disable TDC reference clock. 1: Enable TDC reference clock. Only modify REQ when equal to ACK.	RW	0

TOP:AUX_SYSIF:RTCSUBSECINC0

Address Offset	0x0000 007C
Physical Address	0x400C 607C	Instance	0x400C 607C
Description	Real Time Counter Sub Second Increment 0 INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	INC15_0	New value for bits 15:0 in AON_RTC:SUBSECINC.	RW	0x0000

TOP:AUX_SYSIF:RTCSUBSECINC1

Address Offset	0x0000 0080
Physical Address	0x400C 6080	Instance	0x400C 6080
Description	Real Time Counter Sub Second Increment 1 INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	INC23_16	New value for bits 23:16 in AON_RTC:SUBSECINC.	RW	0x00

TOP:AUX_SYSIF:RTCSUBSECINCCTL

Address Offset	0x0000 0084
Physical Address	0x400C 6084	Instance	0x400C 6084
Description	Real Time Counter Sub Second Increment Control
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	UPD_ACK	Update acknowledgement. 0: AON_RTC has not acknowledged UPD_REQ. 1: AON_RTC has acknowledged UPD_REQ.	RO	0
0	UPD_REQ	Request AON_RTC to update AON_RTC:SUBSECINC. 0: Clear request to update. 1: Set request to update. Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is 1.	RW	0

TOP:AUX_SYSIF:RTCEVCLR

Address Offset	0x0000 0090
Physical Address	0x400C 6090	Instance	0x400C 6090
Description	AON_RTC Event Clear Request to clear events: - AON_RTC:EVFLAGS.CH2. - AON_RTC:EVFLAGS.CH2 delayed version. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000 0000 0000 0000 0000 0000
0	RTC_CH2_EV_CLR	Clear events from AON_RTC channel 2. 0: No effect. 1: Clear events from AON_RTC channel 2. Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0.	RW	0

TOP:AUX_SYSIF:TIMERHALT

Address Offset	0x0000 00A0
Physical Address	0x400C 60A0	Instance	0x400C 60A0
Description	Timer Halt Debug register
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000 0000 0000
1	AUX_TIMER1	Halt AUX_TIMER01 Timer 1. 0: AUX_TIMER01 Timer 1 operates as normal. 1: Halt AUX_TIMER01 Timer 1 operation.	RW	0
0	AUX_TIMER0	Halt AUX_TIMER01 Timer 0. 0: AUX_TIMER01 Timer 0 operates as normal. 1: Halt AUX_TIMER01 Timer 0 operation.	RW	0

TOP:AUX_SYSIF:SWPWRPROF

Address Offset	0x0000 00B4
Physical Address	0x400C 60B4	Instance	0x400C 60B4
Description	Software Power Profiler
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	RESERVED3	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b0 0000 0000 0000 0000 0000 0000 0000
2:0	STAT	Software status bits that can be read by the power profiler.	RW	0b000