Instance: AUX_EVCTL
Component: AUX_EVCTL
Base address: 0x400C5000
AUX Event Controller (AUX_EVCTL) assembles events originating from:
- AUX submodules, including ADC and comparators.
- AUXIO.
- EVENT.
- AON_PMCTL.
- AON_RTC.
into two 64-bit event buses. One is synchronized to the AUX clock and one is left unsynchronized.
The subscribers to the synchronous event bus are AUX_TIMER01 and AUX_EVCTL.
The subscribers to the asynchronous event bus are AUX_ANAIF, AUX_TDC and AUX_SYSIF.
AUX_EVCTL uses the synchronous event bus to generate events to AON_EVENT and EVENT.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 5000 |
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 5004 |
|
RO |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 5008 |
|
RO |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 500C |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 5018 |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x400C 5020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C 5024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x400C 5028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x400C 502C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x400C 5030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x400C 5034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x400C 5038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x400C 503C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x400C 5040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x400C 5048 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C 5000 | Instance | 0x400C 5000 |
Description | Event Status 0 Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_ANAIF. - AUX_TDC. - AUX_SYSIF. - AUX_AIODIO. - EVOBSCFG. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15 | AUXIO15 | AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. | RO | 0 | ||
14 | AUXIO14 | AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. | RO | 0 | ||
13 | AUXIO13 | AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. | RO | 0 | ||
12 | AUXIO12 | AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. | RO | 0 | ||
11 | AUXIO11 | AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. | RO | 0 | ||
10 | AUXIO10 | AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. | RO | 0 | ||
9 | AUXIO9 | AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. | RO | 0 | ||
8 | AUXIO8 | AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. | RO | 0 | ||
7 | AUXIO7 | AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. | RO | 0 | ||
6 | AUXIO6 | AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. | RO | 0 | ||
5 | AUXIO5 | AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. | RO | 0 | ||
4 | AUXIO4 | AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. | RO | 0 | ||
3 | AUXIO3 | AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. | RO | 0 | ||
2 | AUXIO2 | AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. | RO | 0 | ||
1 | AUXIO1 | AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. | RO | 0 | ||
0 | AUXIO0 | AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. | RO | 0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C 5004 | Instance | 0x400C 5004 |
Description | Event Status 1 Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_ANAIF. - AUX_TDC. - AUX_SYSIF. - AUX_AIODIO. - EVOBSCFG. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15 | AUXIO31 | AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. | RO | 0 | ||
14 | AUXIO30 | AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. | RO | 0 | ||
13 | AUXIO29 | AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. | RO | 0 | ||
12 | AUXIO28 | AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. | RO | 0 | ||
11 | AUXIO27 | AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. | RO | 0 | ||
10 | AUXIO26 | AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. | RO | 0 | ||
9 | AUXIO25 | AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. | RO | 0 | ||
8 | AUXIO24 | AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. | RO | 0 | ||
7 | AUXIO23 | AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. | RO | 0 | ||
6 | AUXIO22 | AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. | RO | 0 | ||
5 | AUXIO21 | AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. | RO | 0 | ||
4 | AUXIO20 | AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. | RO | 0 | ||
3 | AUXIO19 | AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. | RO | 0 | ||
2 | AUXIO18 | AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. | RO | 0 | ||
1 | AUXIO17 | AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. | RO | 0 | ||
0 | AUXIO16 | AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. | RO | 0 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C 5008 | Instance | 0x400C 5008 |
Description | Event Status 2 Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_ANAIF. - AUX_TDC. - AUX_SYSIF. - AUX_AIODIO. - EVOBSCFG. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15 | AUX_COMPB | Comparator B output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the synchronization rate for this event. |
RO | 0 | ||
14 | AUX_COMPA | Comparator A output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the synchronization rate for this event. |
RO | 0 | ||
13 | MCU_OBSMUX1 | Observation input 1 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL1. |
RO | 0 | ||
12 | MCU_OBSMUX0 | Observation input 0 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC. |
RO | 0 | ||
11 | MCU_EV | Event from EVENT configured by EVENT:AUXSEL0. | RO | 0 | ||
10 | ACLK_REF | TDC reference clock. It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ. |
RO | 0 | ||
9 | VDDR_RECHARGE | Event is high during VDDR recharge. | RO | 0 | ||
8 | MCU_ACTIVE | Event is high while system(MCU, AUX, or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state). Event is not high during VDDR recharge. | RO | 0 | ||
7 | PWR_DWN | Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO power supply). | RO | 0 | ||
6 | SCLK_LF | SCLK_LF clock | RO | 0 | ||
5:4 | RESERVED4 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. | RO | 0b00 | ||
3 | AON_RTC_4KHZ | AON_RTC:SUBSEC.VALUE bit 19. AON_RTC:CTL.RTC_4KHZ_EN enables this event. |
RO | 0 | ||
2 | AON_RTC_CH2_DLY | AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. | RO | 0 | ||
1 | AON_RTC_CH2 | AON_RTC:EVFLAGS.CH2. | RO | 0 | ||
0 | MANUAL_EV | Programmable event. See MANUAL for description. | RO | 0 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C 500C | Instance | 0x400C 500C |
Description | Event Status 3 Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock. All events read through this register are synchronized at SCE clock rate, unless otherwise noted. The following subscribers use the asynchronous version of events in this register. - AUX_ANAIF. - AUX_TDC . - AUX_SYSIF. - AUX_AIODIO. - EVOBSCFG. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15 | RESERVED15 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. | RO | 0 | ||
14 | AUX_DAC_HOLD_ACTIVE | AUX_ANAIF:DACSTAT.HOLD_ACTIVE | RO | 0 | ||
13 | AUX_SMPH_AUTOTAKE_DONE | See AUX_SMPH:AUTOTAKE.SMPH_ID for description. | RO | 0 | ||
12 | AUX_ADC_FIFO_NOT_EMPTY | AUX_ANAIF:ADCFIFOSTAT.EMPTY negated | RO | 0 | ||
11 | AUX_ADC_FIFO_ALMOST_FULL | AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL | RO | 0 | ||
10 | AUX_ADC_IRQ | The logical function for this event is configurable. When DMACTL.EN = 1 : Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW When DMACTL.EN = 0 : Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW Bit 7 in UDMA0:DONEMASK must be 0. |
RO | 0 | ||
9 | AUX_ADC_DONE | AUX_ANAIF ADC conversion done event. Event is synchronized at AUX bus rate. |
RO | 0 | ||
8 | AUX_ISRC_RESET_N | AUX_ANAIF:ISRCCTL.RESET_N | RO | 0 | ||
7 | AUX_TDC_DONE | AUX_TDC:STAT.DONE | RO | 0 | ||
6 | AUX_TIMER0_EV | AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. | RO | 0 | ||
5 | AUX_TIMER1_EV | AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. | RO | 0 | ||
4:0 | RESERVED0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. | RO | 0b0 0000 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 5018 | Instance | 0x400C 5018 |
Description | Direct Memory Access Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | REQ_MODE | UDMA0 Request mode
|
RW | 0 | |||||||||||
1 | EN | uDMA ADC interface enable. 0: Disable UDMA0 interface to ADC. 1: Enable UDMA0 interface to ADC. |
RW | 0 | |||||||||||
0 | SEL | Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data.
|
RW | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C 5020 | Instance | 0x400C 5020 |
Description | Software Event Set Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR. Use of these event flags is software-defined. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
2 | SWEV2 | Software event flag 2. 0: No effect. 1: Set software event flag 2. |
WO | 0 | ||
1 | SWEV1 | Software event flag 1. 0: No effect. 1: Set software event flag 1. |
WO | 0 | ||
0 | SWEV0 | Software event flag 0. 0: No effect. 1: Set software event flag 0. |
WO | 0 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x400C 5024 | Instance | 0x400C 5024 |
Description | Events To AON Flags This register contains a collection of event flags routed to AON_EVENT. To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
8 | AUX_TIMER1_EV | This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV. | RW | 0 | ||
7 | AUX_TIMER0_EV | This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV. | RW | 0 | ||
6 | AUX_TDC_DONE | This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE. | RW | 0 | ||
5 | AUX_ADC_DONE | This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE. | RW | 0 | ||
4 | AUX_COMPB | This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB. | RW | 0 | ||
3 | AUX_COMPA | This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA. | RW | 0 | ||
2 | SWEV2 | This event flag is set when software writes a 1 to SWEVSET.SWEV2. | RW | 0 | ||
1 | SWEV1 | This event flag is set when software writes a 1 to SWEVSET.SWEV1. | RW | 0 | ||
0 | SWEV0 | This event flag is set when software writes a 1 to SWEVSET.SWEV0. | RW | 0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x400C 5028 | Instance | 0x400C 5028 |
Description | Events To AON Polarity Event source polarity configuration for EVTOAONFLAGS. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | AUX_TIMER1_EV | Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV.
|
RW | 0 | |||||||||||
7 | AUX_TIMER0_EV | Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV.
|
RW | 0 | |||||||||||
6 | AUX_TDC_DONE | Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE.
|
RW | 0 | |||||||||||
5 | AUX_ADC_DONE | Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE.
|
RW | 0 | |||||||||||
4 | AUX_COMPB | Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB.
|
RW | 0 | |||||||||||
3 | AUX_COMPA | Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA.
|
RW | 0 | |||||||||||
2:0 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x400C 502C | Instance | 0x400C 502C |
Description | Events To AON Clear Clear event flags in EVTOAONFLAGS. In order to clear a level sensitive event flag, the event must be deasserted. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
8 | AUX_TIMER1_EV | Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. Read value is 0. |
WO | 0 | ||
7 | AUX_TIMER0_EV | Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. Read value is 0. |
WO | 0 | ||
6 | AUX_TDC_DONE | Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. Read value is 0. |
WO | 0 | ||
5 | AUX_ADC_DONE | Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. Read value is 0. |
WO | 0 | ||
4 | AUX_COMPB | Write 1 to clear EVTOAONFLAGS.AUX_COMPB. Read value is 0. |
WO | 0 | ||
3 | AUX_COMPA | Write 1 to clear EVTOAONFLAGS.AUX_COMPA. Read value is 0. |
WO | 0 | ||
2 | SWEV2 | Write 1 to clear EVTOAONFLAGS.SWEV2. Read value is 0. |
WO | 0 | ||
1 | SWEV1 | Write 1 to clear EVTOAONFLAGS.SWEV1. Read value is 0. |
WO | 0 | ||
0 | SWEV0 | Write 1 to clear EVTOAONFLAGS.SWEV0. Read value is 0. |
WO | 0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x400C 5030 | Instance | 0x400C 5030 |
Description | Events to MCU Flags This register contains a collection of event flags routed to MCU domain. To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
10 | AUX_ADC_IRQ | This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ. | RW | 0 | ||
9 | MCU_OBSMUX0 | This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0. | RW | 0 | ||
8 | AUX_ADC_FIFO_ALMOST_FULL | This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. | RW | 0 | ||
7 | AUX_ADC_DONE | This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE. | RW | 0 | ||
6 | AUX_SMPH_AUTOTAKE_DONE | This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. | RW | 0 | ||
5 | AUX_TIMER1_EV | This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV. | RW | 0 | ||
4 | AUX_TIMER0_EV | This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV. | RW | 0 | ||
3 | AUX_TDC_DONE | This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE. | RW | 0 | ||
2 | AUX_COMPB | This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB. | RW | 0 | ||
1 | AUX_COMPA | This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA. | RW | 0 | ||
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x400C 5034 | Instance | 0x400C 5034 |
Description | Event To MCU Polarity Event source polarity configuration for EVTOMCUFLAGS. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | AUX_ADC_IRQ | Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ.
|
RW | 0 | |||||||||||
9 | MCU_OBSMUX0 | Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0.
|
RW | 0 | |||||||||||
8 | AUX_ADC_FIFO_ALMOST_FULL | Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.
|
RW | 0 | |||||||||||
7 | AUX_ADC_DONE | Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE.
|
RW | 0 | |||||||||||
6 | AUX_SMPH_AUTOTAKE_DONE | Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.
|
RW | 0 | |||||||||||
5 | AUX_TIMER1_EV | Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV.
|
RW | 0 | |||||||||||
4 | AUX_TIMER0_EV | Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV.
|
RW | 0 | |||||||||||
3 | AUX_TDC_DONE | Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE.
|
RW | 0 | |||||||||||
2 | AUX_COMPB | Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB.
|
RW | 0 | |||||||||||
1 | AUX_COMPA | Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA.
|
RW | 0 | |||||||||||
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x400C 5038 | Instance | 0x400C 5038 |
Description | Events To MCU Flags Clear Clear event flags in EVTOMCUFLAGS. In order to clear a level sensitive event flag, the event must be deasserted. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
10 | AUX_ADC_IRQ | Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. Read value is 0. |
WO | 0 | ||
9 | MCU_OBSMUX0 | Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. Read value is 0. |
WO | 0 | ||
8 | AUX_ADC_FIFO_ALMOST_FULL | Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. Read value is 0. |
WO | 0 | ||
7 | AUX_ADC_DONE | Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. Read value is 0. |
WO | 0 | ||
6 | AUX_SMPH_AUTOTAKE_DONE | Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. Read value is 0. |
WO | 0 | ||
5 | AUX_TIMER1_EV | Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. Read value is 0. |
WO | 0 | ||
4 | AUX_TIMER0_EV | Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. Read value is 0. |
WO | 0 | ||
3 | AUX_TDC_DONE | Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. Read value is 0. |
WO | 0 | ||
2 | AUX_COMPB | Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. Read value is 0. |
WO | 0 | ||
1 | AUX_COMPA | Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. Read value is 0. |
WO | 0 | ||
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x400C 503C | Instance | 0x400C 503C |
Description | Combined Event To MCU Mask Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU. The AUX_COMB event is high as long as one or more of the included event flags are set. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
10 | AUX_ADC_IRQ | EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
9 | MCU_OBSMUX0 | EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
8 | AUX_ADC_FIFO_ALMOST_FULL | EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
7 | AUX_ADC_DONE | EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
6 | AUX_SMPH_AUTOTAKE_DONE | EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
5 | AUX_TIMER1_EV | EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
4 | AUX_TIMER0_EV | EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
3 | AUX_TDC_DONE | EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
2 | AUX_COMPB | EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. 0: Exclude 1: Include. |
RW | 0 | ||
1 | AUX_COMPA | EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. 0: Exclude. 1: Include. |
RW | 0 | ||
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x400C 5040 | Instance | 0x400C 5040 |
Description | Event Observation Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
5:0 | EVOBS_SEL | Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIO. | RW | 0b00 0000 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x400C 5048 | Instance | 0x400C 5048 |
Description | Manual Programmable event. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EV | This bit field sets the value of EVSTAT2.MANUAL_EV. | RW | 0 |
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