nikon_drv.h

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/*
 *  Copyright (C) 2024 Texas Instruments Incorporated
 *
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 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 */
 
 
#ifndef NIKON_DRV_H_
#define NIKON_DRV_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <drivers/pruicss.h>
#include <position_sense/nikon/include/nikon_interface.h>
 
/*  Minimum and Maximum NIKON cycle time depends on various params as below:
    TCycle_max = TMA ∗ (number of RX frames * 18) + TX frame(32)
    + delay between TX and RX + (delay between Multi Transmission commands
    * (maximum encoder address delay t6))
    + Delay between two EEPROM access commands(30milisec)
    TCycle_min = TMA * (number of Rx frames * 18) + TX frame(32)
    + delay between TX and RX
    Instead wait for max of 35 ms as this can vary for different encoders,
    different commands and multi transmission connection.
*/
/* Single PRU - Single channel configuration */
#define NIKON_MODE_SINGLE_CHANNEL_SINGLE_PRU (0U)
/* Single PRU - Multichannel configuration */
#define NIKON_MODE_MULTI_CHANNEL_SINGLE_PRU (1U)
/* Multichannel - Load Share configuration */
#define NIKON_MODE_MULTI_CHANNEL_MULTI_PRU (2U)
 
/* 35 milisec as max cycle timeout (more than 30 mili sec delay is required
between two cycles in memory access commands) */
#define NIKON_MAX_CYCLE_TIMEOUT             35
/* Maximum number of 3-ch peripheral interface Channels*/
#define NUM_ED_CH_MAX                       3
/* Maximum number of Nikon Encoders connected in bus connection*/
#define NUM_ENCODERS_MAX                    3
/* Maximum number of Memory Data Frames to be sent on Tx*/
#define NUM_MDF_CMD_MAX                     3
 
#define NIKON_RX_SAMPLE_SIZE_16MHZ          3       /* 4x over sample rate */
#define NIKON_RX_SAMPLE_SIZE_6_67MHZ        5       /* 6x over sample rate */
#define NIKON_RX_SAMPLE_SIZE                7       /* 8x over sample rate */
/* Allowed frequencies in MHz for NIKON */
#define NIKON_FREQ_2_5MHZ                   2.5     /* 2.5 MHz frequency */
#define NIKON_FREQ_4MHZ                     4       /* 4 MHz frequency */
#define NIKON_FREQ_6_67MHZ                  6       /* 6.67 MHz frequency */
#define NIKON_FREQ_8MHZ                     8       /* 8 MHz frequency */
#define NIKON_FREQ_16MHZ                    16      /* 16 MHz frequency */
/* Number of Rx data CRC bits */
#define NIKON_POS_CRC_LEN                   8
/* Default data length instead of garbage*/
#define NIKON_POS_DATA_LEN_DEFAULT          17
 
/* Enable cycle trigger for firmware*/
#define NIKON_ENABLE_CYCLE_TRIGGER          0x1
 /* Disable cycle trigger */
#define NIKON_DISABLE_CYCLE_TRIGGER         0x0
/* Configure firmware in continuous mode*/
#define NIKON_CONFIG_PERIODIC_TRIGGER_MODE  0x0
/* Configure firmware in host trigger mode*/
#define NIKON_CONFIG_HOST_TRIGGER_MODE      0x1
/* General Macro for clearing any status flag */
#define NIKON_CLEAR_STATUS_FLAG             0x0
/* General Macro for setting any status flag */
#define NIKON_SET_STATUS_FLAG               0x1
 
#define NIKON_CHANNEL0_MASK                 0x1     /* Mask for channel 0 */
#define NIKON_CHANNEL1_MASK                 0x2     /* Mask for channel 1 */
#define NIKON_CHANNEL2_MASK                 0x4     /* Mask for channel 2 */
 
/* 1000usec sleep for timeout count*/
#define NIKON_1MILLISEC_SLEEP_TIME          1000
/* 30milli sec delay for EEPROM update */
#define NIKON_30_MILLI_SEC_DELAY            30000
 
/* Middle bit indexes for Given Oversampling rates */
#define NIKON_FIFO_BIT_IDX_8X_OS            4       /* 8x Oversampling */
#define NIKON_FIFO_BIT_IDX_6X_OS            3       /* 6x Oversampling */
#define NIKON_FIFO_BIT_IDX_4X_OS            2       /* 4x Oversampling */
 
#define NIKON_BASE_VALID_BIT_IDX            24      /* Base valid bit index */
 
/* Lengths of the Specified fields */
#define NIKON_DB_BITS_LEN                   10      /* temperature bits*/
#define NIKON_RX_ONE_FRAME_LEN              16      /* Rx frame*/
#define NIKON_EEPROM_ADDR_LEN               8       /* EEPROM memory address*/
#define NIKON_COMMAND_CODE_LEN              5       /* command code */
#define NIKON_ENC_STATUS_LEN                4       /* encoder status field */
#define NIKON_ENC_ADDR_LEN                  3       /* encoder address */
#define NIKON_SYNC_CODE_LEN                 3       /* sync code */
#define NIKON_TX_CRC_LEN                    3       /* 3bit Tx CRC */
#define NIKON_FRAME_CODE_LEN                2       /* frame code */
#define NIKON_START_BIT_LEN                 1       /* start bit */
#define NIKON_STOP_BIT_LEN                  1       /* stop bit */
#define NIKON_FIXED_BIT_LEN                 1       /* fix bit in info field*/
 
/* Status for request or access */
#define NIKON_EEPROM_READ_ACCESS            1       /* eeprom read access */
#define NIKON_EEPROM_WRITE_ACCESS           2       /* eeprom write access */
#define NIKON_ENABLE_ID_CODE_WRITE          2       /* ID code write request */
 
/* Maximum possible parameters */
#define NIKON_MAX_NUM_RX_FRAMES             4       /* Rx frames */
#define NIKON_MAX_ABS_LEN                   40      /* ABS data length */
#define NIKON_MAX_NUM_DATA_FIELDS           3       /* Rx Data fields */
/* Common parameters for most of the commands */
#define NIKON_AVG_NUM_RX_FRAMES             3       /* Rx frames */
#define NIKON_AVG_ABS_LEN                   24      /* ABS data length*/
/*Minimum possible parameters */
#define NIKON_MIN_NUM_RX_FRAMES             2       /* Rx frames */
#define NIKON_MIN_ABS_LEN                   17      /* ABS data length*/
 
/* Masks for speecified fields */
#define NIKON_DB_BITS_MASK                  0x3FF   /* temperature bits(DB) */
#define NIKON_ENC_STATUS_MASK               0xF     /* encoder status field */
#define NIKON_CMD_CODE_MASK                 0x1F    /* command code field*/
#define NIKON_ENC_ADDR_MASK                 0x7     /* encoder address field */
 
/* Number of cycles required to perform operation or reset specific commands */
#define NIKON_NUM_OF_CYCLE_FOR_RESET        7
 
enum cmd_code
{
    CMD_0,                  
    CMD_1,                  
    CMD_2,                  
    CMD_3,                  
    CMD_4,                  
    CMD_5,                  
    CMD_6,                  
    CMD_7,                  
    CMD_8,                  
    CMD_9,                  
    CMD_10,                 
    CMD_11,                 
    CMD_12,                 
    CMD_13,                 
    CMD_14,                 
    CMD_15,                 
    CMD_16,                 
    CMD_17,                 
    CMD_18,                 
    CMD_19,                 
    CMD_20,                 
    CMD_21,                 
    CMD_22,                 
    CMD_27 = 27,            
    CMD_28,                 
    CMD_29,                 
    CMD_30,                 
    ENCODER_ADR_CHANGE,
    START_CONTINUOUS_MODE,  
    UPDATE_CLOCK_FREQ,      
    UPDATE_ENC_LEN,         
    CMD_CODE_NUM
};
 
struct nikon_clk_cfg
{
    uint16_t  rx_div;
    uint16_t  tx_div;
    uint16_t  rx_div_attr;
    uint16_t  is_core_clk;
};
struct pos_data_info
{
    uint32_t raw_data0[NUM_ENCODERS_MAX];
    uint32_t raw_data1[NUM_ENCODERS_MAX];
    uint32_t raw_data2[NUM_ENCODERS_MAX];
    uint32_t raw_data3[NUM_ENCODERS_MAX];
    uint32_t rcv_crc[NUM_ENCODERS_MAX];
    uint32_t otf_crc[NUM_ENCODERS_MAX];
    uint32_t crc_err_cnt[NUM_ENCODERS_MAX];
    uint64_t abs[NUM_ENCODERS_MAX];
    uint32_t multi_turn[NUM_ENCODERS_MAX];
    float angle[NUM_ENCODERS_MAX];
};
struct enc_info
{
    uint32_t enc_status[NUM_ENCODERS_MAX];
    uint32_t enc_cmd[NUM_ENCODERS_MAX];
    uint32_t enc_addr[NUM_ENCODERS_MAX];
};
struct alm_bits
{
    uint8_t batt;
    uint8_t mt_err;
    uint8_t ov_flow;
    uint8_t ov_spd;
    uint8_t mem_err;
    uint8_t st_err;
    uint8_t ps_err;
    uint8_t busy;
    uint8_t mem_busy;
    uint8_t ov_temp;
    uint8_t inc_err;
};
struct nikon_priv
{
    uint32_t pruicss_slicex;
    uint32_t load_share;
    uint32_t data_len[NUM_ED_CH_MAX][NUM_ENCODERS_MAX];
    uint32_t num_encoders[NUM_ED_CH_MAX];
    uint32_t num_enc_access[NUM_ED_CH_MAX];
    uint32_t single_turn_len[NUM_ED_CH_MAX][NUM_ENCODERS_MAX];
    uint32_t multi_turn_len[NUM_ED_CH_MAX][NUM_ENCODERS_MAX];
    uint32_t channel[NUM_ED_CH_MAX];
    struct nikon_pruicss_xchg *pruicss_xchg;
    uint32_t has_safety;
    void *pruicss_cfg;
    uint32_t tx_cdf[NUM_ED_CH_MAX];
    uint32_t tx_mdf;
    uint32_t num_rx_frames;
    uint32_t totalchannels;
    float_t baud_rate;
    uint32_t core_clk_freq;
    uint32_t uart_clk_freq;
    uint32_t eax[NUM_ED_CH_MAX];
    uint32_t fc;
    uint32_t sync_code;
    uint32_t tx_crc;
    uint32_t mem_data[NUM_MDF_CMD_MAX];
    struct   pos_data_info  pos_data_info[NUM_ED_CH_MAX];
    struct   enc_info   enc_info[NUM_ED_CH_MAX];
    uint32_t temperature[NUM_ED_CH_MAX][NUM_ENCODERS_MAX];
    uint32_t identification_code[NUM_ED_CH_MAX];
    uint32_t alm_field[NUM_ED_CH_MAX][NUM_ENCODERS_MAX];
    struct alm_bits alm_bits[NUM_ED_CH_MAX][NUM_ENCODERS_MAX];
    uint32_t abs_len;
    uint32_t is_continuous_mode;
    void *pruicss_iep;
    uint64_t cmp3;
};
 
#ifdef __cplusplus
}
#endif
 
#endif