4.6. CDD_PWM¶
4.6.1. About This Document¶
Document Title |
User Guide of CDD PWM Driver |
Document Version |
Version 1.1 |
Company |
Texas Instruments |
Document Name |
CDD PWM User Guide |
4.6.2. Document Revision History¶
Version |
Date |
Revision History |
Status |
|---|---|---|---|
Version 1.0 |
20 Dec 2023 |
Initial Release. |
Approved |
Version 1.1 |
16 Feb 2024 |
Update on Driver Speicfic API Details |
Approved |
4.6.3. Table of contents¶
4.6.4. Acronyms and Definitions¶
Acronyms and Definitions Used are presented in below table.
Acronyms |
Descriptions |
|---|---|
BSW |
Basic Software |
DET |
Default Error Tracer |
PWM |
Pulse Width Modulation |
MCU |
Micro Controller Unit |
OS |
Operating System |
PLL |
Phase Locked loop |
AUTOSAR |
Automotive Open System Architecture |
CDD |
Complex Device Driver |
HW |
Hardware |
SW |
Software |
DEM |
Diagnostic Event Manager |
DMA |
Direct Memory Access |
MCAL |
Microcontroller Abstraction Layer |
OS |
Operating System |
API |
Application Programming Interface |
4.6.5. Functional Overview¶
4.6.5.1. Brief Overview¶
This document describes the functionality, API and configuration of the AUTOSAR BSW CDD module PWM.
Supported AUTOSAR Release |
4.3.1 |
Supported Configuration Variants |
Pre-Compile, Post-build |
Vendor ID |
CDD_PWM_VENDOR_ID (44) |
Module ID |
CDD_PWM_MODULE_ID (255) |
Supported Platform |
AM263x |
This document describes the functionality and the API of the CDD_PWM (Complex Device Driver_Pulse Width Modulation) driver for the AM263x.
The CDD PWM driver depends on other modules like DET for error handling, OSEK/AUTOSAR OS for interrupt handling, MCU module for system clock settings and SchM module which is BSW Scheduler provides functions that module CDD PWM calls at begin and end of critical sections.
4.6.5.2. Initialization¶
The driver CDD_PWM is initialized by calling Cdd_Pwm_Init() with a pointer to a configuration as parameter. To re-initialize call Cdd_Pwm_DeInit() first and then Cdd_Pwm_Init() with a different configuration.
The below table represents the various states of CDD PWM Channel
States |
Module state |
|---|---|
CDD_PWM driver Status uninitialized |
CDD_PWM_STATUS_UNINIT |
CDD_PWM driver Status Initialized |
CDD_PWM_STATUS_INIT |
CDD_PWM driver Status stopped |
CDD_PWM_STATUS_STOPPED |
CDD_PWM driver Status running |
CDD_PWM_STATUS_RUNNING |
4.6.6. Driver Architecture¶
The following figure shows where the CDD is located in the AUTOSAR architecture.
Figure 8: CDD in AUTOSAR architecture
The AUTOSAR Architecture distinguishes on the highest abstraction level between three software layers Application, Runtime Environment and Basic Software which run on a Microcontroller.
CDD PWM Driver: The Cdd_Pwm driver is part of the Complex Device Driver layer (CDD). The driver provides special functions and features with direct access to the microcontroller using specific interrupts and/or complex microcontroller peripherals, external devices to fulfill the special functional and timing requirements.
Figure 9: Standard alignment left and right, expressed by high and low priority level
The CDD PWM module generates pulses with variable pulse width, allows the selection of the duty cycle and the signal period time and offers services to,
Start output of a PWM signal.
Stop output of a PWM signal.
Set parameters of a PWM channel’s waveform.
Set compare value for Events.
Enable/disable notifications.
Allows the selection of duty cycle and signal period time.
4.6.6.1. Supported and Not Supported Features¶
The features listed in this chapter cover the complete functionality specified
Supported Features |
Not Supported |
|---|---|
Dedicated 16-bit time-base counter with period and frequency control |
Enhanced Pulse Width Modulator XCMP Mode Operation.(EPWM XCMP) |
Time-base counter three modes of operation (i)Up-Down Count Mode (ii)Up-Count Mode (iii)Down-Count Mode |
Asynchronous override control of PWM signals through software. |
Generates events based on programmable time stamps using the CMPA, CMPB, CMPC, and CMPD registers(Counter Compare) |
Programmable phase-control support for lag or lead operation relative to other ePWM modules |
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations – Two independent PWM outputs with single edge operation. – Two independent PWM outputs with dual- edge symmetric operation. |
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis |
All events can trigger both CPU interrupts and ADC start of conversion. (SOC). |
Programmable event prescaling minimizes CPU overhead on interrupts |
Programmable Trip zone and Advance Trip Zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions. |
Illegal Combo Logic(ICL) |
A trip condition can force either high, low,or high-impedance state logic levels at PWM outputs. |
Diode Emulation which provides hardware features and the necessary hooks into other IPs to implement robust diode mode sense and control in noisy environment. |
Dead-band generation with independent rising and falling edge delay control. |
Enhanced Pulse Width Modulator Global Load Configuration(EPWM Global Load). |
Digital Compare |
|
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives. |
|
The HRPWM is based on micro edge positioner(MEP) technology. |
|
HRPWM feature should use the TI-supplied MEP scale factor optimizer (SFO) software function.The SFO function helps to dynamically determine the number of MEP steps per SYSCLKOUT period. |
|
Provide services to start and stop the output of pulse-width-modulated wave forms/signal. |
|
Changing of frequency and duty cycle for a PWM channel at runtime besides the default configuration. |
|
Enable/disable notifications. Allows the selection of duty cycle and signal period time. |
|
There are a number of waveforms, which are supported by the PWM driver. The most widely used is standard PWM. Each period begins with an active state and changes to idle after the duty cycle has ended. Idle output is configurable allowing high or low for idle state according to requirement. |
|
Minimum dead band logic(MDL) block which provides the ability to configure the minimum dead band duration between a complimentary set of PWMs. |
4.6.6.1.1. CDD PWM Channel 0 and Channel 1 Duty Cycle configuration¶
For each channel, “CddPwmCounterCompareRef” needs to be configured as shown below: Channel 0
Channel 1
Then, for each CounterCompare, “CompareValue” needs to be selected as shown below: CounterCompare 0
CounterCompare 1
This “CompareValue” parameter is used to set Duty Cycle into register.
CDD PWM supports addition of various submodules which have additional features like,
4.6.6.1.2. Time-Base submodule¶
The time-base submodule consists of a dedicated 16-bit counter, along with built-in synchronization logic to allow multiple ePWM modules to work together as a single system.
A clock pre-scaler divides the EPWM clock to the counter and a period register is used to control the frequency and period of the generated waveform.
The period register has a shadow register, which acts like a buffer to allow the register updates to be synchronized with the counter, thus avoiding corruption or spurious operation from the register being modified asynchronously by the software.
The time-base counter operates in three modes: up-count, down-count, and up-down-count.
In up-count mode the time-base counter starts counting from zero and increments until it reaches the period register value, then the time-base counter resets to zero and the count sequence starts again.
In down-count mode the time-base counter starts counting from the period register value and decrements until it reaches zero, then the time-base counter is loaded with the period value and the count sequence starts again.
In up-down-count mode the time-base counter starts counting from zero and increments until it reaches the period register value, then the time base counter decrements until it reaches zero and the count sequence repeats. The up-count and down-count modes are used to generate asymmetrical waveforms, and the up-down-count mode is used to generate symmetrical waveforms.
Figure 1: Time-Base Submodule
4.6.6.1.3. Compare submodule¶
The counter-compare submodule continuously compares the time-base count value to four counter compare registers (CMPA, CMPB, CMPC, and CMPD) and generates four independent compare events (i.e. time-base counter equals a compare register value) which are fed to the action-qualifier and event-trigger submodules.
The counter compare registers are shadowed to prevent corruption or glitches during the active PWM cycle.
Typically CMPA and CMPB are used to control the duty cycle of the generated PWM waveform.
All four compare registers can be used to start an ADC conversion or generate an ePWM interrupt.
For the up-count and down count modes, a counter match occurs only once per cycle, however for the up-down-count mode a counter match occurs twice per cycle since there is a match on the up count and down count.
Figure 2: Compare Submodule
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing provides a way to keep updates to the registers synchronized with the hardware. When shadowing is used,updates to the active registers only occur at strategic points. This prevents corruption or spurious operation due to the register being asynchronously modified by software. The memory address of the active register and the shadow register is identical.
4.6.6.1.4. Action Qualifier submodule¶
The action-qualifier submodule is the key element in the ePWM module which is responsible for constructing and generating the switched PWM waveforms. It utilizes match events from the time-base and counter-compare submodules for performing actions on the EPWMxA and EPWMxB output pins. These first three submodules are the main blocks which are used for generating a basic PWM waveform.
The Action Qualifier actions are setting the pin high, clearing the pin low, toggling the pin, or do nothing to the pin, based independently on count-up and count-down time-base match event.
The match events occur when the time-base counter equals the period register value, the time-base counter is zero, the time-base counter equals CMPA, the time-base counter equals CMPB, or for a Trigger event (T1 and T2) based on a comparator, trip, or sync signal.
Zero and period actions are fixed in time, whereas CMPA and CMPB actions are moveable in time by programming their respective registers. Actions are configured independently for each output using shadowed registers, and any or all events can be configured to generate actions on either output. Also, the output pins can be forced to any action using software.
The next few figures show how the setting of the action qualifier with the compare matches are used to modulate the output pins.
The output pins for EPWMA and EPWMB are completely independent.
In above figure , the EPWMA output is being set high on the zero match and cleared low on the compare A match. The EPWMB output is being set high on the zero match and cleared low on the compare B match.
In the above figure , the EPWMA output is being set high on the compare A match and being cleared low on the compare B match, while the EPWMB output is being toggled on the zero match.
In the above figure , the EPWMA output is being set high on the compare A match and being cleared low on the compare B match, while the EPWMB output is being toggled on the zero match.
Figure 3: Action Qualifier Waveforms using different output actions on the up-count and down count
And finally in the above figure, again using different output actions on the up-count and down count, the EPWMA output is being set high on the compare A up-count match and being cleared low on the compare B down-count match. The EPWMB output is being cleared low on the zero match and being set high on the period match.
Asymmetric and Symmetric Waveform Generation using the ePWM
Count Mode Timing Waveforms
The counter-compare module can generate compare events in all three count modes:
Up-count mode: used to generate an Asymmetric PWM waveform.
Down-count mode: used to generate an Asymmetric PWM waveform.
Up-down-count mode: used to generate a Symmetric PWM PWM waveform.
PWM Switching Frequency
The PWM carrier frequency is determined by the value contained in the time-base period register, and the frequency of the clocking signal. The value needed in the period register is:
Asymmetric PWM
Period register = (TPWM/ TTBCLK) - 1
Symmetric PWM
Period register = TPWM/ 2(TTBCLK)
where, TPWM is the period of the PWM events, called as Switching Period. TTBCLK is the period of the time-base clock, called as timer period.
It is as shown below:
Notice that in the symmetric case, the period value is half that of the asymmetric case. This is because for up/down counting, the actual timer period is twice that specified in the period register (i.e. the timer counts up to the period register value, and then counts back down).
PWM Resolution
The PWM compare function resolution can be computed once the period register value is determined. The largest power of 2 that is less than (or close to) the period value is used for the function resolution. As an example, if asymmetric was 1000, and symmetric was 500, then:
Asymmetric PWM: approx. 10 bit resolution since 2^10 = 1024, approximately equal to 1000
Symmetric PWM: approx. 9 bit resolution since 2^9 = 512, approximately equal to 500
PWM Duty Cycle
Duty cycle calculations are used to define where CMP registers are set. These calculations are simple, provided one remembers that the PWM signal is initially inactive during any particular timer period, and becomes active after the (first) compare match occurs. The timer compare register should be loaded with the value as follows:
Asymmetric PWM: CMPX = (100% - duty cycle)*TBPRD
Symmetric PWM: CMPX = (100% - duty cycle)*TBPRD
PWM Computation Example
Determine TBPRD and CMPA for 100 kHz, 25% duty symmetric PWM from a 100 MHz time base clock.
TBPRD = 0.5* (FTBCLK/FPWM) = 0.5 (100 MHz/ 100 kHz) = 500
CMPA = (100% - duty cycle) TBPRD = 0.75*500=375
Determine TBPRD and CMPA for 100 kHz, 25% duty asymmetric PWM from a 100 MHz time base clock.
TBPRD = (FTBCLK/FPWM) -1 = (100 MHz/ 100 kHz) -1 = 999
CMPA = (100% - duty cycle) (TBPRD +1) -1 = 0.75 * (999 + 1) -1 = 749
4.6.6.1.5. Dead-Band submodule¶
The dead-band sub-module provides a means to delay the switching of a gate signal, thereby allowing time for gates to turn off and preventing a short circuit.
This sub-module supports independently programmable rising-edge and falling-edge delays with various options for generating the appropriate signal outputs on EPWMxA and EPWMxB.
The key functions of the dead-band module are:
Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a single EPWMxA input
Programming signal pairs for:
– Active high (AH)
– Active low (AL)
– Active high complementary (AHC)
– Active low complementary (ALC)
Adding programmable delay to rising edges (RED)
Adding programmable delay to falling edges (FED)
Can be totally bypassed from the signal path
Figure 4: Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
Dead-band control provides a convenient means of combating current shoot-through problems in a power converter. Shoot-through occurs when both the upper and lower gates in the same phase of a power converter are open simultaneously. This condition shorts the power supply and results in a large current draw. Shoot-through problems occur because transistors open faster than they close, and because high-side and low-side power converter gates are typically switched in a complimentary fashion. Although the duration of the shoot-through current path is finite during PWM cycling, (i.e. the closing gate will eventually shut), even brief periods of a short circuit condition can produce excessive heating and overstress in the power converter and power supply.
4.6.6.1.6. Trip-Zone submodule¶
Trip-Zone has a fast, clock-independent logic path to high-impedance the EPWMxA/B output pins.
Interrupt latency may not protect hardware when responding to over current conditions or short-circuits through ISR software.
It supports:
One-shot trip for major short circuits or over current conditions and
Cycle-by-cycle trip for current limiting operation.
Figure 5: Trip-Zone Submodule
The trip-zone submodule utilizes a fast clock-independent logic mechanism to quickly handle fault conditions by forcing the EPWMxA and EPWMxB outputs to a safe state, such as high, low, or high-impedance.
The trip-zone signals can be generated externally from any GPIO pin which is mapped through the Input X-Bar (TZ1 – TZ3), internally from an inverted eQEP error signal (TZ4), system clock failure (TZ5), or from an emulation stop output from the CPU (TZ6). Additionally, numerous trip-zone source signals can be generated from the digital-compare subsystem.
4.6.6.1.7. Advance Trip-Zone Submodule¶
Advance TripZone is similar to normal Trip Zone.
It also Supports :
One-shot trip for major short circuits or over current conditions and
Cycle-by-cycle trip for current limiting operation.
Advance TripZone also provides same fault Conditions similar to Tripzone but It provide one extra safe state i.e Toggle
4.6.6.1.8. Chopper submodule¶
The PWM chopper submodule is used with pulse transformer-based gate drives to control the power switching devices.
This submodule modulates a high-frequency carrier signal with the PWM waveform that is generated by the action-qualifier and dead-band submodules. The key functions of the PWM chopper submodule are:
Programmable chopping (carrier) frequency
Programmable pulse width of first pulse
Programmable duty cycle of second and subsequent pulses
Can be fully bypassed if not required.
Programmable options are available to support the magnetic properties and characteristics of the transformer and associated circuitry.
Shown in the figure below, a high-frequency carrier signal is ANDed with the ePWM outputs. Also, this circuit provides an option to include a larger, one-shot pulse width before the sustaining pulses.
Figure 6: Chopper Submodule
4.6.6.1.9. Event-trigger submodule¶
The event-trigger submodule manages the events generated by the time-base, counter-compare, and digital-compare submodules to generate an interrupt to the CPU and/or a start of conversion pulse to the ADC when a selected event occurs. It provides full visibility of event generation using event counters and flags. The event-trigger submodule also incorporates pre-scaling logic to issue an interrupt request or ADC start of conversion at every event or up to every fifteenth event.
Figure 7: Event Trigger Submodule
These event triggers can occur when the time-base counter equals zero, period, zero or period, the up/down count match of a compare register. It also enable/disable ADC Trigger.
4.6.6.1.10. Digital Compare(DC) Submodule¶
The digital compare (DC) submodule compares signals external to the ePWM module (for instance, CMPSSx signals from the analog comparators) to directly generate PWM events/actions which then feed to the eventtrigger, trip-zone, and time-base submodules.Additionally, blanking window functionality is supported to filter noise or unwanted pulses from the DC event signals.
4.6.6.1.11. High-Resolution Pulse Width Modulator (HRPWM)¶
This module extends the time resolution capabilities of the conventionally derived digital pulse width modulator (PWM). HRPWM is typically used when PWM resolution falls below approximately 9-10 bits.
The key features of HRPWM are: • Extended time resolution capability • Used in both duty cycle and phase-shift control methods • Finer time granularity control or edge positioning using extensions to the Compare A, Compare B and Phase registers • Implemented using the A and B signal path of PWM, that is, on the EPWMxA and EPWMxB output • Dead band high-resolution control for falling and rising edge delay in half cycle clocking operation • Enables high-resolution output swapping on the EPWMxA and EPWMxB output • Enables high-resolution output on EPWMxB signal output using inversion of EPWMxA signal output • Enables high-resolution period, duty and phase control on the EPWMxA and EPWMxB output on devices with an ePWM module
4.6.6.2. Assumptions¶
None
4.6.6.3. Limitations¶
Note
CDD PWM module and MCAL PWM module shall not use same EPWM channel.
4.6.6.4. Design overview¶
Please refer SITARA MCU MCAL Architecture Document and MCAL: CDD PWM Detailed Design Document provided as part of CSP.
4.6.6.5. File Structure¶
Static source C File Structure is defined below in the table.
Static source C File Structure |
Description |
|---|---|
Cdd_Pwm.c |
Implementation of the API’s for CDD_PWM driver. |
Cdd_Pwm.h |
Contains the API’s of the CDD_PWM driver to be used by upper layers |
Cdd_Pwm_Priv.c |
Contains Internal Functions Definitions. |
Cdd_Pwm_Priv.h |
Contains data structures and Internal function declarations |
Cdd_Pwm_Irq.c |
Contains ISR function definitions. |
Cdd_Pwm_Irq.h |
Contains ISR function declaration |
Cdd_Pwm_Sfo.c |
Contains the SFO functionality. |
Cdd_Pwm_Sfo.h |
Contains the header file for SFO functionality. |
Cdd_Pwm_Types.h |
Contains the data tyeps of CDD PWM. |
Plugin file structure is defined below in the table.
Plugin Structure |
Descriptions |
|---|---|
Cdd_Pwm_Cfg.h |
Contains the base addresses, Precompile switches, Macros for channels, counters etc. |
Cdd_Pwm_PBcfg.c |
Contains all channels Post-Build Configuration parameters |
Cdd_Pwm_Cfg.c |
Contains all channels Pre-Compile Configuration parameters |
The below diagram shows the files structure for the PWM driver.Similarly is the strcuture for CDD PWM
Figure 10: Reference : Header file structure of the PWM driver
4.6.7. Deviations to requirements(Requirement Traceability)¶
4.6.7.1. Module Requirements¶
Please refer Software Product Specification document provided as part of CSP.
4.6.7.2. Deviation of requirements against AUTOSAR specification requirements¶
NA
4.6.8. Integration Details¶
4.6.8.1. Dependency on Other Software Modules¶
4.6.8.1.1. OSEK / AUTOSAR OS (Optional)¶
An operating system can be used fortask scheduling, interrupt handling, global suspend and restore of interrupts and creating of the Interrupt Vector Table. The CDD_PWM module may use OSEK/AUTOSAR OS to suspend and restore global interrupts.
4.6.8.1.2. MCU¶
The module MCU powers up the microcontroller’s peripherals at startup time and initializes the PLL(not directly) and the internal clock domains.
The CDD_PWM module depends on MCU module for enabling CDD_PWM clock for channel and crossbar interrupt mapping of CDD_PWM interrupts depending on the CDD_PWM channel configured.
Suppose the CDD_PWM channel 0 is configured for CDD_PWM module as shown in below figure:
Then, the MCU module container McuCddPwmConfiguration should also be configured as shown in below figure:
Similarly, the crossbar interrupts also need to be mapped in MCU module according to CDD_PWM channel configured. The CDD_PWM interrupts needs to be mapped to the corresponding cross bar interrupt.
Also, the input crossbar interrupts also need to be mapped in MCU module according to CDD_PWM channel configured. The CDD_PWM interrupts needs to be mapped to the corresponding cross bar interrupt.
NOTE : McuCddPwmConfiguration and McuPwmConfiguration cannot be used together.
4.6.8.1.3. PORT¶
Module PORT configures the port pins that are used for output of CDD_PWM signal. For details see Technical Reference of Port.
4.6.8.1.4. DET¶
The module CDD_PWM depends on the DET (by default) in order to report development errors. Detection and reporting of development errors can be enabled or disabled by the switch.
“Enable Development Error Detection”.
The DET can be replaced optionally by an equivalent component which is responsible to recognize development errors, if no DET component is available.
4.6.8.1.5. Error Handling¶
Development Error Reporting
By default, development errors are reported to the Development Error Tracer (DET) using the service Det_ReportError() if detection and reporting of development errors is enabled in the configuration tool. If another module is used for development error reporting, the function name for reporting the error can be configured by the integrator, but must have the same signature as the service Det_ReportError().
AUTOSAR requires that API functions shall check the validity of their respective parameters.
Type of Error |
Relevance |
Related Error Code |
Value |
|---|---|---|---|
API service used without module initialization. |
Development |
CDD_PWM_E_UNINIT |
0x02U |
API Cdd_Pwm_Init service called with wrong parameter. |
Development |
CDD_PWM_E_INIT_FAILED |
0x0BU |
API service used with an invalid channel Identifier. |
Development |
CDD_PWM_E_PARAM_INVALID_CHANNEL |
0x03U |
API Cdd_Pwm_SetPinAction() called with an invalid pin action. |
Development |
CDD_PWM_E_PARAM_INVALID_ACTION |
0x05U |
Usage of Cdd_Pwm_DisableNotification() or Cdd_Pwm_EnableNotification on a channel where a NULL pointer is configured as the notification function. |
Development |
CDD_PWM_E_NO_VALID_NOTIF |
0x06U |
API Cdd_Pwm_Init() called while the CDD_PWM driver has already been initialized. |
Development |
CDD_PWM_E_ALREADY_INITIALIZED |
0x07U |
API Cdd_Pwm_GetVersionInfo() is called with a NULL parameter. |
Development |
CDD_PWM_E_PARAM_POINTER |
0x08U |
Cdd_Pwm_StartChannelCounter() called on a channel that is in state RUNNING. |
Development |
CDD_PWM_E_BUSY |
0x09U |
Cdd_Pwm_SetPinAction() called for a channel that doesn’t have an associated output pin. |
Development |
CDD_PWM_E_PARAM_NO_PIN |
0x0AU |
Cdd_Pwm_SetRelativeThreshold() called for with a compare match parameter greater than maximum |
Development |
CDD_PWM_E_PARAM_INVALID_VALUE |
0x1AU |
Invalid Channel parameter |
Development |
CDD_PWM_E_PARAM_CHANNEL |
0x1BU |
4.6.8.1.6. Error Handling: Runtime Errors¶
None
4.6.8.1.7. Callback Notification¶
The Cdd_Pwm driver provide configured notification call back for each interrupt occurred and Trip Zone notification.
4.6.8.2. Hardware - Software - ISR API name mapping¶
For each of the configured hardware units, one interrupt service routine has to be mapped. The Integrator has to map the interrupt service routines to the interrupt sources of the respective CDD_PWM unit interrupt. The supported ISR’s are part of the Cdd_Pwm_Irq.h file.
For interrupt notification, ISR’s are provided in CDD PWM driver. There is one ISR for each CDD PWM hardware unit. Depending on hardware unit configured, it will call group notify function. The interrupt service routines shall be mapped to the interrupt sources of the respective cross bar interrupt. There are 4 Groups and each has 32 Channels:
ISR for PWM Interrupt:
Cdd_Pwm_<GROUP>_Ch<n>Isr
Here, <GROUP> represents the GROUP number, which can be G0, G1, G2, G3.
<n> represents the EPWM Channel number, which can be from 0 to 31.
ISR for PWM Trip Zone:
Cdd_Pwm_<GROUP>_TzCh<n>Isr
Here, <GROUP> represents the GROUP number, which can be G0, G1, G2, G3.
<n> represents the EPWM Channel number, which can be from 0 to 31.
4.6.8.3. Scheduling Strategy¶
4.6.8.3.1. SchM (Optional)¶
Beside the OSEK / AUTOSAR OS the BSW Scheduler provides functions that module CDD PWM calls at begin and end of critical sections. There is only one kind of critical sections in this driver. Within these sections all read /modify / write accesses to internal CDD PWM status variables must be protected. This is handled internally in the CDD PWM driver by invoking SchM_Enter_Cdd_Pwm_PWM_EXCLUSIVE_AREA_0/ SchM_Exit_Cdd_Pwm_PWM_EXCLUSIVE_AREA_0()
4.6.9. API Description¶
4.6.9.1. Description of the API’s¶
Please refer Function Definitions in MCAL: CDD PWM Detailed Design Document provided as part of CSP.
4.6.9.2. API’s with Service ID¶
The following table presents the service IDs and the related services:
Service ID |
Service |
|---|---|
0x0U |
Cdd_Pwm_Init |
0x1U |
Cdd_Pwm_DeInit |
0x2U |
Cdd_Pwm_StartChannelCounter |
0x3U |
Cdd_Pwm_StopChannelCounter |
0x5U |
Cdd_Pwm_SetPinAction |
0x6U |
Cdd_Pwm_GetCounter |
0x8U |
Cdd_Pwm_SetRelativeThreshold |
0x4U |
Cdd_Pwm_GetCounterStatus |
0x15U |
Cdd_Pwm_ClearCounterStatus |
0x2CU |
Cdd_Pwm_CounterComparatorCfg |
0x09U |
Cdd_Pwm_DisableNotification |
0x0AU |
Cdd_Pwm_EnableNotification |
0x16U |
Cdd_Pwm_EtIntrStatus |
0x17U |
Cdd_Pwm_EtIntrClear |
0x18U |
Cdd_Pwm_EtGetEventCount |
0x19U |
Cdd_Pwm_SetAdcTrigger |
0x1BU |
Cdd_Pwm_TzTripEventEnable |
0x1CU |
Cdd_Pwm_TzTripEventDisable |
0x1DU |
Cdd_Pwm_TzIntrEnable |
0x1EU |
Cdd_Pwm_TzIntrDisable |
0x1FU |
Cdd_Pwm_TzGetEventStatus |
0x20U |
Cdd_Pwm_TzEventStatusClear |
0xEU |
Cdd_Pwm_SetPeriodDutyPhase |
0xFU |
Cdd_Pwm_SetOutputToIdle |
0x2AU |
Cdd_Pwm_SyncEnable |
0x2BU |
Cdd_Pwm_SyncDisable |
0x10U |
Cdd_Pwm_DeadbandCfg |
0x11U |
Cdd_Pwm_DeadbandBypass |
0x12U |
Cdd_Pwm_ChopperCfg |
0x13U |
Cdd_Pwm_ChopperEnable |
0xDU |
Cdd_Pwm_RegisterReadback |
0xBU |
Cdd_Pwm_GetVersionInfo |
0x21U |
Cdd_Pwm_HrSetPeriodDutyPhase |
0x22U |
Cdd_Pwm_HrSfoCalibration |
0x23U |
Cdd_Pwm_HrSfoStatus |
4.6.10. Configuration Description¶
4.6.10.1. Configuration Variants¶
The PWM is configured through GUI in Post-Build and Pre-Compile Variants.
Variants |
Configured Files |
|---|---|
PostBuild |
Cdd_Pwm_PBcfg.c, Cdd_Pwm_Cfg.c, Cdd_Pwm_Cfg.h |
Pre-Compile |
Cdd_Pwm_Cfg.c, Cdd_Pwm_Cfg.h |
4.6.10.2. Parameter Description¶
4.6.10.2.1. IP Specific Configuration¶
Parameters |
Description |
Default Value |
Range |
Unit |
|---|---|---|---|---|
CddPwmDeInitApi |
Adds / removes the service CddPwmDeInit() from the codeis reached. |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmGetCounterApi |
Adds / removes the service CddPwmGetCounter() from the code |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmVersionInfoApi |
Switch to indicate that the CddPwmGetVersionInfo() is supported |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmEnableRegisterReadbackApi |
Switch to indicate that the CddPwmRegisterReadBack is supported |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmSystemClock |
This parameter specifies the starting parameter of the EDMA channel for use as own resource |
200000000 |
0..200000000 |
INTEGER |
CddPwmMaxDutyCycle |
The physical hardware channel that is assigned to this logical channel |
65536 |
0..65536 |
INTEGER |
CddPwmNumberofChannel |
Number of actual HW channels. This is of type published information and not editable |
32 |
NA |
INTEGER |
CddPwmChannelId |
The physical hardware channel that is assigned to this logical channel |
same as channel id |
0..127 |
INTEGER |
CddPwmTimerBaseId |
The Timer Base unit ID |
0 |
0..255 |
INTEGER |
CddPwmEnablePhaseShiftValue |
Phase Shift Value:Phase Shift Value for the Time Base Counter Submodule |
1 |
0..65535 |
INTEGER |
CddPwmSetOutputToIdle |
Switches the API Cdd_Pwm_SetOutputToIdle |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmGetCounterStatus |
Switches the API Cdd_Pwm_GetCounterStatus |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmCounterComparatorCfg |
Switches the API Cdd_Pwm_CounterComparatorCfg |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmSetAdcTriggerApi |
Switch to indicate that the ADC enable API is supported |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmTimerBaseSyncId |
The Timer Base Sync unit ID. |
same as sync id |
0..255 |
INTEGER |
CddPwmCounterCompareId |
The Counter Compare unit ID |
same as compare |
0..255 |
INTEGER |
CddPwmCompareValueCmpA |
Counter Compare A (CMPA) value |
1 |
0..65536 |
INTEGER |
CddPwmCompareValueCmpB |
Counter Compare B (CMPB) value |
1 |
0..65536 |
INTEGER |
CddPwmCompareValueCmpC |
Counter Compare C (CMPC) value |
1 |
0..65536 |
INTEGER |
CddPwmCompareValueCmpD |
Counter Compare D (CMPD) value |
1 |
0..65536 |
INTEGER |
CddPwmNotificationSupported |
Adds / removes the services CddPwmEnableNotification() and CddPwmDisableNotification() from the code |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmDevErrorDetect |
Switches the Development Error Detection ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmEventTriggerEnable |
Switches the Pwm event trigger functionality ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmTripZoneEnable |
Switches the Pwm Trip zone functionality ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmDigitalCompareEnable |
Switches the Pwm Digital Compare functionality ON or OFF |
FALSE |
TRUE/FALSE |
BOOLEAN |
CddPwmActionQualifierId |
The Action Qualifier unit ID |
Same as qualifier id |
0..255 |
INTEGER |
CddPwmEventTriggerId |
The Action Qualifier unit ID |
Same as trigger id |
0..255 |
INTEGER |
CddPwmEventCountInitialValue |
Value of the pre-event value that is to be loaded into the SOC trigger event counter |
1 |
0..15 |
INTEGER |
CddPwmDeadBandEnable |
Switches the PWM dead band functionality ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmChopperEnable |
Switches the PWM chopper functionality ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmActionQualifierEnable |
Switches the Pwm Action Qualifier functionality ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmInterruptCount |
The number of events that have to occur before an interrupt is issued |
1 |
1..15 |
INTEGER |
CddPwmChannelTimerBaseSyncEnable |
Switches the PWM timer base sync functionality ON or OFF. |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmChannelHighResPwmEnable |
Switches the High Resolution PWM functionality ON or OFF |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmHrSetPeriodDutyEnable |
Enable/Disable switch the API Cdd_Pwm_HrSetPeriodDutyPhase |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmHrSfoCalibrationEnable |
Enable/disable switch to the API Cdd_Pwm_HrSfoCalibration |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmHrSfoStatusEnable |
Enable/disable switch to the API Cdd_Pwm_HrSfoStatus |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmAdcEventTriggerId |
The ADC event triggered ID |
same as trigger id |
0..255 |
INTEGER |
CddPwmTimerBaseGlobalLoad |
Use global load configuration for PRD |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmTimerBaseShadowMode |
The physical hardware channel that is assigned to this logical channel |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmEnablePhaseShift |
Enable Phase Shift Load:Enable phase shift load for the Time Base Counter Submodule |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocAEventCountInitialValue |
Value of the pre-event value that is to be loaded into the SOC trigger event counter |
1 |
0..15 |
INTEGER |
CddPwmSocAInterruptCount |
The number of events that have to occur before an SOC is issued |
1 |
1..15 |
INTEGER |
CddPwmSocBEventCountInitialValue |
Value of the pre-event value that is to be loaded into the SOC B trigger event counter |
1 |
0..15 |
INTEGER |
CddPwmSocBInterruptCount |
The number of events that have to occur before an SOC B is issued |
1 |
1..15 |
INTEGER |
CddPwmTripZoneId |
Pwm Trip Zone unit ID |
same as trip id |
0..255 |
INTEGER |
CddPwmDeadBandId |
Dead band unit ID |
same as band id |
0..255 |
INTEGER |
CddPwmREDDelayValue |
Raising edge delay value |
1 |
0..65536 |
INTEGER |
CddPwmFEDDelayValue |
Falling edge delay value |
1 |
0..65536 |
INTEGER |
BlankingWindowOffset |
Set the offset of the blanking window (TBCLK count) |
0 |
0..65536 |
INTEGER |
BlankingWindowLength |
Set the length of the blanking window (TBCLK count). |
0 |
0..65536 |
INTEGER |
SoftwareValleyDelayValue |
Set SWVDELVAL(Software Valley Delay Value).This value along with the valley delay divider will be used to calculate the HWDELVAL |
0 |
0..65535 |
INTEGER |
CddPwmChopperId |
PWM Chopper unit ID |
Same as Chopper Id |
0..255 |
INTEGER |
CddPwmForceSync |
Force A Sync Pulse:Force a sync pulse for the Time Base Counter Submodule |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnSoftware |
Software force generated EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnCntrZero |
Counter zero event generates EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnCntCmpB |
Counter equal to CMPB event generates EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnCntCmpC |
Counter equal to CMPC event generates EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnCntCmpD |
Counter equal to CMPD event generates EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnDCAEVT1SYNC |
DCA Event 1 Sync signal generates EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnDCBEVT1SYNC |
DCB Event 1 Sync signal generates EPWM sync-out pulse |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutPulseOnALL |
The physical hardware channel that is assigned to this logical channel |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareGlobalLoadCmpA |
Enable Counter Compare A Global Load Use global load configuration for CMPA |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareShadowModeCmpA |
Enable Shadow Counter Compare A Enable Shadow Counter Compare A (CMPA) value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareGlobalLoadCmpB |
Enable Counter Compare B Global Load Use global load configuration for CMPB |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareShadowModeCmpB |
Enable Shadow Counter Compare B Enable Shadow Counter Compare B (CMPB) value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareGlobalLoadCmpC |
Enable Counter Compare C Global Load Use global load configuration for CMPC |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareShadowModeCmpC |
Enable Shadow Counter Compare C Enable Shadow Counter Compare C (CMPC) value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareGlobalLoadCmpD |
Enable Counter Compare D Global Load Use global load configuration for CMPD |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCounterCompareShadowModeCmpD |
Enable Shadow Counter Compare D Enable Shadow Counter Compare D (CMPD) value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmActionGlobalLoadEPWMA |
Enable Action qualifier Global Load A Use global load configuration |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmActionShadowModeEPWMA |
Enable Shadow Action Qualifier A Enable Shadow for action qualifier |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmActionGlobalLoadEPWMB |
Enable Action qualifier Global Load B Use global load configuration |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmActionShadowModeEPWMB |
Enable Shadow Action Qualifier B Enable Shadow for action qualifier |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmForceEventValue |
Forces the ePWM interrupt counter to be pre-interrupt loaded with the init count value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmEnableEventCountInitialValue |
Enables the ePWM SOC trigger counter to be pre-event loaded with a count value after a software force |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrZero |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrPeriod |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrUCmpA |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrDCmpA |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrUCmpB |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrDCmpB |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrUCmpC |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrDCmpC |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrUCmpD |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixTbctrDCmpD |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntMixDCAEvt1 |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocAEpwmEvent |
Enable the SOC trigger generated by the ET submodule |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocAForceEventValue |
Forces the ePWM SOC trigger counter to be pre-event loaded with the init count value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocAEventCountInitialValueEnable |
Enables the ePWM SOC trigger counter to be pre-event loaded with a count value after a software force |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrZero |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrPeriod |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrUCmpA |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrDCmpA |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrUCmpB |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrDCmpB |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrUCmpC |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrDCmpC |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrUCmpD |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocAMixTbctrDCmpD |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocAIntMixDCAEvt1 |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocBEpwmEvent |
Enable the SOC B trigger generated by the ET submodule |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocBForceEventValue |
Forces the ePWM SOC B trigger counter to be pre-event loaded with the init count value |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocBEventCountInitialValueEnable |
Enables the ePWM SOC B trigger counter to be pre-event loaded with a count value after a software force |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrZero |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrPeriod |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrUCmpA |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrDCmpA |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrUCmpB |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrDCmpB |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrUCmpC |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrDCmpC |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrUCmpD |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmIntSocBMixTbctrDCmpD |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSocBIntMixDCAEvt1 |
Switches the PWM dead band functionality ON or OFF |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmAdvancedTripZoneAction |
Enable / disable the trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotTZ1 |
Enable / disable one shot trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotTZ2 |
Enable / disable one shot trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotTZ3 |
Enable / disable one shot trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotTZ4 |
Enable / disable one shot trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotTZ5 |
Enable / disable one shot trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotTZ6 |
Enable / disable one shot trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotDCAEVT1 |
Enable / disable one shot Digital comapre A event |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmOneShotDCBEVT1 |
Enable / disable one shot Digital comapre B event |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCBCTZ1 |
Enable / disable cycle by cycle trip zone |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmCBCDCBEVT2 |
Enable / disable cycle by cycle Digital comapre B event. |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmTZCBCInterrupt |
Enable / disable cycle by cycle trip zone interupt |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmTZOneShotInterrupt |
Enable / disable one shot trip zone interupt |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDCAEVT1Interrupt |
Enable / disable digital compare A event 1 interupt |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDCAEVT2Interrupt |
Enable / disable digital compare A event 2 interupt |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDCBEVT1Interrupt |
Enable / disable digital compare B event 1 interupt |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDCBEVT2Interrupt |
Enable / disable digital compare B event 2 interupt |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDeadBandGlobalLoad |
Enable Deadband global load configuration |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDeadBandShadowMode |
Enable Deadband shandowing |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDeadBandSwapOutputA |
Enable swap the output, Channel A path to Out B. |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDeadBandSwapOutputB |
Enable swap the output, Channel B path to Out A |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmRedGlobalLoad |
Enable global load for RED |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmRedShadowMode |
Enable RED shandowing |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmREDEnable |
Enable the Raising edge delay(RED) |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmFedGlobalLoad |
Enable global load for FED |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmFedShadowMode |
Enable FED shandowing |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmFEDEnable |
Enable the falling edge delay(FED) |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmAdcSocEventA |
Enables/Disables the ADC SOC Event for Digital compare module A digital compare number 1. |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutEventA |
Enables/Disables the ADC Syncout Event for Digital compare module A digital compare number 1 |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmAdcSocEventB |
Enables/Disables the ADC SOC Event for Digital compare module B digital compare number 1 |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmSyncOutEventB |
Enables/Disables the ADC Syncout Event for Digital compare module B digital compare number 1 |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmUseBlankingWindow |
Use blanking window to blank the DCEVTFILT signal |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDCCounterCaptureShadowMode |
Use DC counter capture feature in shadow mode |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmUseDCCounterCapture |
Use DC counter capture feature to capture the TBCTR value at the selected event |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmEdgeFilterValleyCapture |
This will enable valley capturing feature/allows the input signal selected for valley capturing to reset the edge filter count |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmStartValleyCaptureLogic |
Start the valley capture logic |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmDelayedOutputEdgeFilter |
Start the valley capture logic |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmUseEdgeFilter |
The DCEVTFILT signal and DCCAP (counter capture) will use the output of the edge filter |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmChopperEnable |
Enable the Chopper |
FALSE |
TRUE / FALSE |
BOOLEAN |
CddPwmEnableHRPWM |
Enable/Disable the HRPWM functionality |
TRUE |
TRUE / FALSE |
BOOLEAN |
CddPwmAutoHRMStepScaling |
Enable/Disable the automatic HR step scaling |
TRUE |
TRUE / FALSE |
BOOLEAN |
CddPwmEnableHRPeriodCtrl |
Enable/Disable the HRPWM Period |
TRUE |
TRUE / FALSE |
BOOLEAN |
CddPwmEnableHRPhaseCtrl |
Enable/Disable the HRPWM Phase load |
TRUE |
TRUE / FALSE |
BOOLEAN |
CddPwmSwapOutputCtrl |
Swap A and B channels HRPWM outputs |
TRUE |
TRUE / FALSE |
BOOLEAN |
CddPwmChopperDuty |
Chopper duty cycle |
1 |
1..8 |
INTEGER |
CddPwmChopperFreqency |
Chopper freqency |
1 |
1..8 |
INTEGER |
CddPwmChopperFirstPulseWidth |
Chopper first pulse width |
1 |
1..16 |
INTEGER |
CddPwmHRPwmId |
HR Pwm unit ID |
Same as HRPwmId |
0..256 |
INTEGER |
CddPwmCmpHRPWMA |
HR CMPA Value |
0 |
0..4294967296 |
INTEGER |
CddPwmCmpHRPWMB |
HR CMPB Value |
0 |
0..4294967296 |
INTEGER |
CddPwmHRPeriod |
HR Period Value |
0 |
0..4294967296 |
INTEGER |
CddPwmHRPhase |
HR Phase Value |
0 |
0..4294967296 |
INTEGER |
CddPwmRisingEdgeDelay |
HR Rising Edge delay value |
0 |
0..4294967296 |
INTEGER |
CddPwmFallingEdgeDelay |
HR Falling Edge delay value |
0 |
0..4294967296 |
INTEGER |
CddPwmTypeofInterruptFunction |
Type of ISR function |
CDD_PWM_ISR_VOID |
CDD_PWM_ISR_VOID CDD_PWM_ISR_CAT1 CDD_PWM_ISR_CAT2 |
ENUMERATION |
CddPwmDeviceVariant |
Device variant MCAL |
AM263X |
AM263X |
ENUMERATION |
CddPwmHwChannel |
The physical hardware channel that is assigned to this logical channel |
CDD_PWM_CHANNEL_0 |
CDD_PWM_CHANNEL_0 CDD_PWM_CHANNEL_1 CDD_PWM_CHANNEL_2 CDD_PWM_CHANNEL_3 CDD_PWM_CHANNEL_4 CDD_PWM_CHANNEL_5 CDD_PWM_CHANNEL_6 CDD_PWM_CHANNEL_7 CDD_PWM_CHANNEL_8 CDD_PWM_CHANNEL_9 CDD_PWM_CHANNEL_10 CDD_PWM_CHANNEL_11 CDD_PWM_CHANNEL_12 CDD_PWM_CHANNEL_13 CDD_PWM_CHANNEL_14 CDD_PWM_CHANNEL_15 CDD_PWM_CHANNEL_16 CDD_PWM_CHANNEL_17 CDD_PWM_CHANNEL_18 CDD_PWM_CHANNEL_19 CDD_PWM_CHANNEL_20 CDD_PWM_CHANNEL_21 CDD_PWM_CHANNEL_22 CDD_PWM_CHANNEL_23 CDD_PWM_CHANNEL_24 CDD_PWM_CHANNEL_25 CDD_PWM_CHANNEL_26 CDD_PWM_CHANNEL_27 CDD_PWM_CHANNEL_28 CDD_PWM_CHANNEL_29 CDD_PWM_CHANNEL_30 CDD_PWM_CHANNEL_31 |
ENUMERATION |
CddPwmGroupUnit |
The parameter is used to select the EPWM Group unit: G0, G1, G2 and G3 |
CDD_PWM_CONTROLSS_G0 |
CDD_PWM_CONTROLSS_G0 CDD_PWM_CONTROLSS_G1 CDD_PWM_CONTROLSS_G2 CDD_PWM_CONTROLSS_G3 |
ENUMERATION |
CddPwmOutPutChannelSelection |
The parameter is used to select the EPWM Channel EPWMA or EPWMB or Both |
CDD_PWM_OUTPUT_CH_BOTH_A_AND_B |
CDD_PWM_OUTPUT_CH_BOTH_A_AND_B CDD_PWM_OUTPUT_CH_A CDD_PWM_OUTPUT_CH_B |
ENUMERATION |
CddPwmPolarity |
The parameter is used to select the EPWM Channel Polarity HIGH or LOW |
CDD_PWM_HIGH |
CDD_PWM_HIGH CDD_PWM_LOW |
ENUMERATION |
CddPwmEmulationMode |
Behavior of the ePWM time-base counter during emulation events: Stop after next Time Base counter increment or decrement, Stop when counter completes whole cycle, Free run counter |
CDD_PWM_EMULATION_FREE_RUN |
CDD_PWM_EMULATION_STOP_AFTER_NEXT_TB CDD_PWM_EMULATION_STOP_AFTER_FULL_CYCLE CDD_PWM_EMULATION_FREE_RUN |
ENUMERATION |
CddPwmClockDivider |
Time Base Clock Divider:CLKDIV CLKDIV: These bits select the time base clock pre-scale value, TBCLK = EPWMCLK/(HSPCLKDIV*CLKDIV). |
CDD_PWM_CLOCK_DIVIDER_1 |
CDD_PWM_CLOCK_DIVIDER_1 CDD_PWM_CLOCK_DIVIDER_2 CDD_PWM_CLOCK_DIVIDER_4 CDD_PWM_CLOCK_DIVIDER_8 CDD_PWM_CLOCK_DIVIDER_16 CDD_PWM_CLOCK_DIVIDER_32 CDD_PWM_CLOCK_DIVIDER_64 CDD_PWM_CLOCK_DIVIDER_128 |
ENUMERATION |
CddPwmHSClockDivider |
High Speed Clock Divider:CLKDIV HSPCLKDIV:These bits determine part of the time-base clock pre-scale value, TBCLK = EPWMCLK/(HSPCLKDIV*CLKDIV). |
CDD_PWM_HSCLOCK_DIVIDER_1 |
CDD_PWM_HSCLOCK_DIVIDER_1 CDD_PWM_HSCLOCK_DIVIDER_2 CDD_PWM_HSCLOCK_DIVIDER_4 CDD_PWM_HSCLOCK_DIVIDER_6 CDD_PWM_HSCLOCK_DIVIDER_8 CDD_PWM_HSCLOCK_DIVIDER_10 CDD_PWM_HSCLOCK_DIVIDER_12 CDD_PWM_HSCLOCK_DIVIDER_14 |
ENUMERATION |
CddPwmTbPeriod |
Value of period used for Initialization.(in seconds) |
1 |
0.0..Infinity |
FLOAT |
CddPwmTbPeriodInitValue |
Value of period used for Initialization.(in seconds). Initial Counter value for the Time Base Counter Submodule |
1 |
0.0..Infinity |
FLOAT |
CddPwmCounterMode |
Counter Mode:Mode of the Counter value for the Time Base Counter Submodule |
CDD_PWM_COUNTER_MODE_STOP_FREEZE |
CDD_PWM_COUNTER_MODE_UP CDD_PWM_COUNTER_MODE_DOWN CDD_PWM_COUNTER_MODE_UP_DOWN CDD_PWM_COUNTER_MODE_STOP_FREEZE |
ENUMERATION |
CddPwmPeriodLoadMode |
Time Base Period Load Mode:Period load mode for the Time Base Counter Submodule |
CDD_PWM_PERIOD_DIRECT_LOAD |
CDD_PWM_PERIOD_SHADOW_LOAD CDD_PWM_PERIOD_DIRECT_LOAD |
ENUMERATION |
CddPwmTbprdlink |
Time Base Period Link:Simultaneous write to the current ePWM module PRD register |
CDD_PWM_LINK_DISABLE |
CDD_PWM_LINK_DISABLE CDD_PWM_LINK_WITH_PWM_0 CDD_PWM_LINK_WITH_PWM_1 CDD_PWM_LINK_WITH_PWM_2 CDD_PWM_LINK_WITH_PWM_3 CDD_PWM_LINK_WITH_PWM_4 CDD_PWM_LINK_WITH_PWM_5 CDD_PWM_LINK_WITH_PWM_6 CDD_PWM_LINK_WITH_PWM_7 CDD_PWM_LINK_WITH_PWM_8 CDD_PWM_LINK_WITH_PWM_9 CDD_PWM_LINK_WITH_PWM_10 CDD_PWM_LINK_WITH_PWM_11CDD_PWM_LINK_WITH_PWM_12 CDD_PWM_LINK_WITH_PWM_13 CDD_PWM_LINK_WITH_PWM_14 CDD_PWM_LINK_WITH_PWM_15 CDD_PWM_LINK_WITH_PWM_16 CDD_PWM_LINK_WITH_PWM_17CDD_PWM_LINK_WITH_PWM_18 CDD_PWM_LINK_WITH_PWM_19 CDD_PWM_LINK_WITH_PWM_20 CDD_PWM_LINK_WITH_PWM_21 CDD_PWM_LINK_WITH_PWM_22 CDD_PWM_LINK_WITH_PWM_23 CDD_PWM_LINK_WITH_PWM_24 CDD_PWM_LINK_WITH_PWM_25 CDD_PWM_LINK_WITH_PWM_26 CDD_PWM_LINK_WITH_PWM_27 CDD_PWM_LINK_WITH_PWM_28 CDD_PWM_LINK_WITH_PWM_29 CDD_PWM_LINK_WITH_PWM_30 CDD_PWM_LINK_WITH_PWM_31 |
ENUMERATION |
CddPwmPeriodShadowLoadMode |
Not available |
CDD_PWM_SHADOW_LOAD_MODE_COUNTER_ZERO |
CDD_PWM_SHADOW_LOAD_MODE_COUNTER_ZERO CDD_PWM_SHADOW_LOAD_MODE_COUNTER_SYNC CDD_PWM_SHADOW_LOAD_MODE_SYNC |
ENUMERATION |
CddPwmOneShotSyncOutTrigger |
One-Shot Sync Out Trigger:One-Shot Sync Out Trigger for the Time Base Counter Submodule |
CDD_PWM_OSHT_SYNC_OUT_TRIG_SYNC |
CDD_PWM_OSHT_SYNC_OUT_TRIG_SYNC CDD_PWM_OSHT_SYNC_OUT_TRIG_RELOAD |
ENUMERATION |
CddPwmTbprdlink |
Not available |
CDD_PWM_LINK_DISABLE |
CDD_PWM_LINK_DISABLE CDD_PWM_LINK_WITH_PWM_0 CDD_PWM_LINK_WITH_PWM_1 CDD_PWM_LINK_WITH_PWM_2 CDD_PWM_LINK_WITH_PWM_3 CDD_PWM_LINK_WITH_PWM_4 CDD_PWM_LINK_WITH_PWM_5 CDD_PWM_LINK_WITH_PWM_6 CDD_PWM_LINK_WITH_PWM_7 CDD_PWM_LINK_WITH_PWM_8 CDD_PWM_LINK_WITH_PWM_9 CDD_PWM_LINK_WITH_PWM_10 CDD_PWM_LINK_WITH_PWM_11CDD_PWM_LINK_WITH_PWM_12 CDD_PWM_LINK_WITH_PWM_13 CDD_PWM_LINK_WITH_PWM_14 CDD_PWM_LINK_WITH_PWM_15 CDD_PWM_LINK_WITH_PWM_16 CDD_PWM_LINK_WITH_PWM_17CDD_PWM_LINK_WITH_PWM_18 CDD_PWM_LINK_WITH_PWM_19 CDD_PWM_LINK_WITH_PWM_20 CDD_PWM_LINK_WITH_PWM_21 CDD_PWM_LINK_WITH_PWM_22 CDD_PWM_LINK_WITH_PWM_23 CDD_PWM_LINK_WITH_PWM_24 CDD_PWM_LINK_WITH_PWM_25 CDD_PWM_LINK_WITH_PWM_26 CDD_PWM_LINK_WITH_PWM_27 CDD_PWM_LINK_WITH_PWM_28 CDD_PWM_LINK_WITH_PWM_29 CDD_PWM_LINK_WITH_PWM_30 CDD_PWM_LINK_WITH_PWM_31 |
ENUMERATION |
CddPwmSyncOutPulseSource |
Sync In Pulse Source:Sync in Pulse for the Time Base Counter Submodule |
CDD_PWM_SYNC_IN_PULSE_SRC_DISABLE |
|
ENUMERATION |
CddPwmCounterBlockCmpA |
Compare A (CMPA) Block |
CDD_PWM_CMP_A |
CDD_PWM_CMP_A |
ENUMERATION |
CddPwmCounterCompareShadowEventCmpA |
Counter Compare A Shadow Load Event |
CDD_PWM_COMP_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmTbprdlinkCmpA |
Time Base Period Link:Simultaneous write to the current ePWM module CMP A register |
CDD_PWM_LINK_DISABLE |
CDD_PWM_LINK_DISABLE CDD_PWM_LINK_WITH_PWM_0 CDD_PWM_LINK_WITH_PWM_1 CDD_PWM_LINK_WITH_PWM_2 CDD_PWM_LINK_WITH_PWM_3 CDD_PWM_LINK_WITH_PWM_4 CDD_PWM_LINK_WITH_PWM_5 CDD_PWM_LINK_WITH_PWM_6 CDD_PWM_LINK_WITH_PWM_7 CDD_PWM_LINK_WITH_PWM_8 CDD_PWM_LINK_WITH_PWM_9 CDD_PWM_LINK_WITH_PWM_10 CDD_PWM_LINK_WITH_PWM_11CDD_PWM_LINK_WITH_PWM_12 CDD_PWM_LINK_WITH_PWM_13 CDD_PWM_LINK_WITH_PWM_14 CDD_PWM_LINK_WITH_PWM_15 CDD_PWM_LINK_WITH_PWM_16 CDD_PWM_LINK_WITH_PWM_17CDD_PWM_LINK_WITH_PWM_18 CDD_PWM_LINK_WITH_PWM_19 CDD_PWM_LINK_WITH_PWM_20 CDD_PWM_LINK_WITH_PWM_21 CDD_PWM_LINK_WITH_PWM_22 CDD_PWM_LINK_WITH_PWM_23 CDD_PWM_LINK_WITH_PWM_24 CDD_PWM_LINK_WITH_PWM_25 CDD_PWM_LINK_WITH_PWM_26 CDD_PWM_LINK_WITH_PWM_27 CDD_PWM_LINK_WITH_PWM_28 CDD_PWM_LINK_WITH_PWM_29 CDD_PWM_LINK_WITH_PWM_30 CDD_PWM_LINK_WITH_PWM_31 |
ENUMERATION |
CddPwmCounterBlockCmpB |
Compare B (CMPB) Block |
CDD_PWM_CMP_B |
CDD_PWM_CMP_B |
ENUMERATION |
CddPwmCounterCompareShadowEventCmpB |
Counter Compare B Shadow Load Event |
CDD_PWM_COMP_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmTbprdlinkCmpB |
Time Base Period Link:Simultaneous write to the current ePWM module CMP B register |
CDD_PWM_LINK_DISABLE |
|
ENUMERATION |
CddPwmCounterBlockCmpC |
Compare C (CMPC) Block |
CDD_PWM_CMP_C |
CDD_PWM_CMP_C |
ENUMERATION |
CddPwmCounterCompareShadowEventCmpC |
Counter Compare C Shadow Load Event |
CDD_PWM_COMP_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmTbprdlinkCmpC |
Time Base Period Link:Simultaneous write to the current ePWM module CMP C register |
CDD_PWM_LINK_DISABLE |
|
ENUMERATION |
CddPwmCounterBlockCmpD |
Compare D (CMPD) Block |
CDD_PWM_CMP_D |
CDD_PWM_CMP_D |
ENUMERATION |
CddPwmCounterCompareShadowEventCmpD |
Counter Compare D Shadow Load Event |
CDD_PWM_COMP_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmTbprdlinkCmpD |
Time Base Period Link:Simultaneous write to the current ePWM module CMP D register |
CDD_PWM_LINK_DISABLE |
|
ENUMERATION |
CddPwmOutptEPWMA |
Not available |
CDD_PWM_E_A |
CDD_PWM_E_A |
ENUMERATION |
CddPwmActionShadowEventEPWMA |
Action Qualifer EPWM A Shadow Load Event |
CDD_PWM_AQ_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmT1TriggerSourceEPWMA |
Trigger 1 event sources |
CDD_PWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 |
|
ENUMERATION |
CddPwmT2TriggerSourceEPWMA |
Trigger 2 event sources |
CDD_PWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 |
|
ENUMERATION |
CddPwmActionQualifierOneTimeSwOutputEPWMA |
One time software forced event, output state based |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
CDD_PWM_AQ_OUTPUT_NO_CHANGE CDD_PWM_AQ_OUTPUT_LOW CDD_PWM_AQ_OUTPUT_HIGH CDD_PWM_AQ_OUTPUT_TOGGLE |
ENUMERATION |
CddPwmActionQualifierContinuousSwOutputEPWMA |
Continuous software forced event, output state based |
CDD_PWM_AQ_SW_DISABLED |
CDD_PWM_AQ_SW_DISABLED CDD_PWM_AQ_SW_OUTPUT_LOW CDD_PWM_AQ_SW_OUTPUT_HIGH |
ENUMERATION |
CddPwmAqOutputOnTimebaseZEROEPWMA |
Action when event generate, when TBCTR Equals Zero |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
CDD_PWM_AQ_OUTPUT_NO_CHANGE CDD_PWM_AQ_OUTPUT_LOW CDD_PWM_AQ_OUTPUT_HIGH CDD_PWM_AQ_OUTPUT_TOGGLE |
ENUMERATION |
CddPwmAqOutputOnTimebasePERIODEPWMA |
Action when event generate, when TBCTR Equals period |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseUPCMPAEPWMA |
Action when event generate, when TBCTR Equals CMPA in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseDOWNCMPAEPWMA |
Action when event generate, when TBCTR Equals CMPA in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseUPCMPBEPWMA |
Action when event generate, when TBCTR Equals CMPB in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
CDD_PWM_AQ_OUTPUT_NO_CHANGE CDD_PWM_AQ_OUTPUT_LOW CDD_PWM_AQ_OUTPUT_HIGH CDD_PWM_AQ_OUTPUT_TOGGLE |
ENUMERATION |
CddPwmAqOutputOnTimebaseDOWNCMPBEPWMA |
Action when event generate, when TBCTR Equals CMPB in Down counter mode |
ENUMERATION |
||
CddPwmAqOutputOnT1COUNTUPEPWMA |
Action when event generate, when T1 event occures in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT1COUNTDOWNEPWMA |
Action when event generate, when T1 event occures in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT2COUNTUPEPWMA |
Action when event generate, when T2 event occures in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT2COUNTDOWNEPWMA |
Action when event generate, when T2 event occures in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmOutptEPWMB |
Not available |
CDD_PWM_E_B |
CDD_PWM_E_B |
ENUMERATION |
CddPwmActionShadowEventEPWMB |
Action Qualifer EPWM B Shadow Load Event |
CDD_PWM_AQ_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmT1TriggerSourceEPWMB |
Trigger 1 event sources |
CDD_PWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 |
|
ENUMERATION |
CddPwmT2TriggerSourceEPWMB |
Trigger 2 event sources |
CDD_PWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 |
|
ENUMERATION |
CddPwmActionQualifierOneTimeSwOutputEPWMB |
One time software forced event, output state based |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmActionQualifierContinuousSwOutputEPWMB |
Continuous software forced event, output state based |
CDD_PWM_AQ_SW_DISABLED |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseZEROEPWMB |
Action when event generate, when TBCTR Equals Zero |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebasePERIODEPWMB |
Action when event generate, when TBCTR Equals period |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseUPCMPAEPWMB |
Action when event generate, when TBCTR Equals CMPA in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseDOWNCMPAEPWMB |
Action when event generate, when TBCTR Equals CMPA in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseUPCMPBEPWMB |
Action when event generate, when TBCTR Equals CMPB in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseDOWNCMPBEPWMB |
Action when event generate, when TBCTR Equals CMPB in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT1COUNTUPEPWMA |
Action when event generate, when T1 event occures in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT1COUNTDOWNEPWMA |
Action when event generate, when T1 event occures in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT2COUNTUPEPWMA |
Action when event generate, when T2 event occures in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT2COUNTDOWNEPWMA |
Action when event generate, when T2 event occures in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmOutptEPWMB |
Not available |
CDD_PWM_E_B |
CDD_PWM_E_B |
ENUMERATION |
CddPwmActionShadowEventEPWMB |
Action Qualifer EPWM B Shadow Load Event |
CDD_PWM_AQ_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmT1TriggerSourceEPWMB |
Trigger 1 event sources |
CDD_PWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 |
|
ENUMERATION |
CddPwmT2TriggerSourceEPWMB |
Trigger 2 event sources |
CDD_PWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 |
|
ENUMERATION |
CddPwmActionQualifierOneTimeSwOutputEPWMB |
One time software forced event, output state based. |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmActionQualifierContinuousSwOutputEPWMB |
Continuous software forced event, output state based. |
CDD_PWM_AQ_SW_DISABLED |
CDD_PWM_AQ_SW_DISABLED CDD_PWM_AQ_SW_OUTPUT_LOW CDD_PWM_AQ_SW_OUTPUT_HIGH |
ENUMERATION |
CddPwmAqOutputOnTimebaseZEROEPWMB |
Action when event generate, when TBCTR Equals Zero |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebasePERIODEPWMB |
Action when event generate, when TBCTR Equals period |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseUPCMPAEPWMB |
Action when event generate, when TBCTR Equals CMPA in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseDOWNCMPAEPWMB |
Action when event generate, when TBCTR Equals CMPA in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseUPCMPBEPWMB |
Action when event generate, when TBCTR Equals CMPB in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnTimebaseDOWNCMPBEPWMB |
Action when event generate, when TBCTR Equals CMPB in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT1COUNTUPEPWMB |
Action when event generate, when T1 event occures in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT1COUNTDOWNEPWMB |
Action when event generate, when T1 event occures in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT2COUNTUPEPWMB |
Action when event generate, when T2 event occures in Up counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmAqOutputOnT2COUNTDOWNEPWMB |
Action when event generate, when T2 event occures in Down counter mode |
CDD_PWM_AQ_OUTPUT_NO_CHANGE |
|
ENUMERATION |
CddPwmInterruptEventSources |
Events that must be enabled to generate an EPWM interrupt |
CDD_PWM_INT_TBCTR_ZERO |
|
ENUMERATION |
CddPwmSocAInterruptEventSources |
Select the SOC trigger source for SOCA |
CDD_PWM_SOC_TBCTR_ZERO |
|
ENUMERATION |
CddPwmSocBInterruptEventSources |
Select the SOC trigger source for SOCB |
CDD_PWM_SOC_DCxEVT1 |
|
ENUMERATION |
CddPwmTZAEvent |
|
CDD_PWM_HZ_STATE |
|
ENUMERATION |
CddPwmTZAAdvUEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmTZAAdvDEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmTZBEvent |
|
CDD_PWM_HZ_STATE |
|
ENUMERATION |
CddPwmTZBAdvUEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmTZBAdvDEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCAEVT1Event |
|
CDD_PWM_HZ_STATE |
|
ENUMERATION |
CddPwmDCAEVT1AdvUEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCAEVT1AdvDEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCAEVT2Event |
|
CDD_PWM_HZ_STATE |
|
ENUMERATION |
CddPwmDCAEVT2AdvUEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCAEVT2AdvDEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCBEVT1Event |
|
CDD_PWM_HZ_STATE |
|
ENUMERATION |
CddPwmDCBEVT1AdvUEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCBEVT1AdvDEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCBEVT2Event |
|
CDD_PWM_HZ_STATE |
|
ENUMERATION |
CddPwmDCBEVT2AdvUEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmDCBEVT2AdvDEvent |
|
CDD_PWM_TZ_ADV_ACTION_HIGH_Z |
|
ENUMERATION |
CddPwmCycleByCycleTripZoneClearMode |
CBC trip zone latch clear signal |
CDD_PWM_TZ_CBC_PULSE_CLR_CNTR_ZERO |
CDD_PWM_TZ_CBC_PULSE_CLR_CNTR_ZERO CDD_PWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD CDD_PWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD |
ENUMERATION |
CddPwmDeadBandClockMode |
Dead band clock rate |
CDD_PWM_DB_COUNTER_CLOCK_FULL_CYCLE |
CDD_PWM_DB_COUNTER_CLOCK_FULL_CYCLE CDD_PWM_DB_COUNTER_CLOCK_HALF_CYCLE |
ENUMERATION |
CddPwmDeadBandDelayLoadMode |
Shadow to active load event |
CDD_PWM_RED_LOAD_ON_CNTR_ZERO |
CDD_PWM_RED_LOAD_ON_CNTR_ZERO CDD_PWM_RED_LOAD_ON_CNTR_PERIOD CDD_PWM_RED_LOAD_ON_CNTR_ZERO_PERIOD CDD_PWM_RED_LOAD_FREEZE |
ENUMERATION |
CddPwmRedBandPolarity |
RED polarity: To invert the signal |
CDD_PWM_DB_POLARITY_ACTIVE_HIGH |
CDD_PWM_DB_POLARITY_ACTIVE_HIGH CDD_PWM_DB_POLARITY_ACTIVE_LOW |
ENUMERATION |
CddPwmREDDelayInput |
Source for RED |
CDD_PWM_DB_INPUT_EPWMA |
CDD_PWM_DB_INPUT_EPWMA CDD_PWM_DB_INPUT_EPWMB |
ENUMERATION |
CddPwmFedDelayLoadMode |
Shadow to active load FED event |
CDD_PWM_RED_LOAD_ON_CNTR_ZERO |
CDD_PWM_RED_LOAD_ON_CNTR_ZERO CDD_PWM_RED_LOAD_ON_CNTR_PERIOD CDD_PWM_RED_LOAD_ON_CNTR_ZERO_PERIOD CDD_PWM_RED_LOAD_FREEZE |
ENUMERATION |
CddPwmFedBandPolarity |
CDD_PWM_DB_POLARITY_ACTIVE_HIGH |
CDD_PWM_DB_POLARITY_ACTIVE_HIGH CDD_PWM_DB_POLARITY_ACTIVE_LOW |
ENUMERATION |
|
CddPwmFEDDelayInput |
Source for FED |
CDD_PWM_DB_INPUT_EPWMA |
CDD_PWM_DB_INPUT_EPWMA CDD_PWM_DB_INPUT_EPWMB CDD_PWM_DB_INPUT_DB_RED |
ENUMERATION |
CombinationInputSource(DCAHigh) |
Select the sources to include in the combination input sources |
EPWM_DC_TRIP_COMBINATION |
|
ENUMERATION |
CddPwmDCAHigh |
Trip Input to the DCA High |
EPWM_DC_TRIP_TRIPIN1 |
|
ENUMERATION |
CombinationInputSource(DCALow) |
Select the sources to include in the combination input sources |
EPWM_DC_TRIP_COMBINATION |
|
ENUMERATION |
CddPwmDCALow |
Trip Input to the DCA Low |
EPWM_DC_TRIP_TRIPIN1 |
|
ENUMERATION |
CddPwmDCAOutputHigh1A |
Condition for DCA output high1 for channel A |
EPWM_TZ_EVENT_DC_DISABLED |
|
ENUMERATION |
CddPwmDCAOutputHigh2A |
Condition for DCA output high2 for channel A |
EPWM_TZ_EVENT_DC_DISABLED |
|
ENUMERATION |
CddPwmSyncModeAEVT1 |
Select the Sync mode for digital compare module A Event Number 1 |
EPWM_DC_EVENT_INPUT_SYNCED |
EPWM_DC_EVENT_INPUT_SYNCED EPWM_DC_EVENT_INPUT_NOT_SYNCED |
ENUMERATION |
CddPwmSignalSoureAEVT1 |
Select the Sync mode for digital compare module A Event Number 1 |
EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL |
EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL EPWM_DC_EVENT_SOURCE_FILT_SIGNAL |
ENUMERATION |
CddPwmCBCLatchModeDCAEVT1 |
Select the CBC LAtch mode for digital compare module A Event Number 1 |
EPWM_DC_CBC_LATCH_DISABLED |
EPWM_DC_CBC_LATCH_DISABLED EPWM_DC_CBC_LATCH_ENABLED |
ENUMERATION |
CddPwmCBCLatchClearModeDCAEVT1 |
Select the CBC Latch clear mode for digital compare module A Event Number 1 |
EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO |
EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD |
ENUMERATION |
CddPwmSyncModeAEVT2 |
Select the Sync mode for digital compare module A Event Number 2 |
EPWM_DC_EVENT_INPUT_SYNCED |
EPWM_DC_EVENT_INPUT_SYNCED EPWM_DC_EVENT_INPUT_NOT_SYNCED |
ENUMERATION |
CddPwmSignalSoureBEVT2 |
Select the Sync mode for digital compare module B Event Number 2 |
EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL |
EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL EPWM_DC_EVENT_SOURCE_FILT_SIGNAL |
ENUMERATION |
CddPwmCBCLatchModeDCBEVT2 |
Select the CBC LAtch mode for digital compare module B Event Number 2 |
EPWM_DC_CBC_LATCH_DISABLED |
EPWM_DC_CBC_LATCH_DISABLED EPWM_DC_CBC_LATCH_ENABLED |
ENUMERATION |
CddPwmCBCLatchClearModeDCBEVT2 |
Select the CBC Latch clear mode for digital compare module B Event Number 2 |
EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO |
EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD |
ENUMERATION |
BlankingWindowStartMixedEvent |
Select the mixed event source that starts the blanking window counter (And resets the counter) |
0 |
|
ENUMERATION |
BlankingWindowStartEvent |
Select the event source that starts the blanking window counter (And resets the counter) |
EPWM_DC_WINDOW_START_TBCTR_PERIOD |
|
ENUMERATION |
CddPwmStartValleyCapture |
The number of trigger events required to start the valley capture count |
Events_0 |
|
ENUMERATION |
CddPwmUseEdgeFilterCounterCaptureSignal |
Sets the signal source for valley capture and edge filter counter reset |
EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE |
|
ENUMERATION |
CddPwmEdgeFilterCount |
Sets the number of edges detected bye the digital compare event edge filter mode to generate an event |
EPWM_DC_EDGEFILT_EDGECNT_0 |
|
ENUMERATION |
CddPwmEdgeFilterMode |
Sets the digital compare event edge filter mode |
EPWM_DC_EDGEFILT_MODE_RISING |
EPWM_DC_EDGEFILT_MODE_RISING EPWM_DC_EDGEFILT_MODE_FALLING EPWM_DC_EDGEFILT_MODE_BOTH |
ENUMERATION |
CddPwmValleyDelayDivider |
The delay divider along with SWVDELVAL will be used calculate the HWDELVAL |
EPWM_VALLEY_DELAY_MODE_SW_DELAY |
|
ENUMERATION |
CddPwmDcFilterInputEventSource |
Select the event source for the DCEVTFILT signal |
EPWM_DC_WINDOW_SOURCE_DCAEVT1 |
|
ENUMERATION |
CddPwmCtrlModeHRPWMA |
Control Mode For Channel A |
HRPWM_MEP_DUTY_PERIOD_CTRL |
HRPWM_MEP_DUTY_PERIOD_CTRL HRPWM_MEP_PHASE_CTRL |
ENUMERATION |
CddPwmCtrlModeHRPWMB |
Control Mode For Channel B |
HRPWM_MEP_DUTY_PERIOD_CTRL |
HRPWM_MEP_DUTY_PERIOD_CTRL HRPWM_MEP_PHASE_CTRL |
ENUMERATION |
CddPwmEdgeModeHRPWMA |
Not available |
HRPWM_MEP_CTRL_DISABLE |
|
ENUMERATION |
CddPwmShadowActiveLoadEventHRPWMA |
CMPAHR Shadow To Active Load Event |
HRPWM_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmEdgeModeHRPWMB |
Not available |
HRPWM_MEP_CTRL_DISABLE |
|
ENUMERATION |
CddPwmShadowActiveLoadEventHRPWMB |
CMPBHR Shadow To Active Load Event |
HRPWM_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmPWMSyncSelect |
HR PWMSYNC Source Select |
HRPWM_PWMSYNC_SOURCE_ZERO |
|
ENUMERATION |
CddPwmDeadbandEdgeMode |
HR PWM Deadband MEP Edge Mode Selection |
HRPWM_DB_MEP_CTRL_DISABLE |
|
ENUMERATION |
CddPwmRisEdgeShadowActiveLoad |
DBREDHR Shadow To Active Load Event |
HRPWM_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmFalEdgeShadowActiveLoad |
DBFEDHR Shadow To Active Load Event |
HRPWM_LOAD_ON_CNTR_ZERO |
|
ENUMERATION |
CddPwmHROutputCtrlPWMB |
EPWMxB Output Selection |
HRPWM_OUTPUT_ON_B_NORMAL |
HRPWM_OUTPUT_ON_B_NORMAL HRPWM_OUTPUT_ON_B_INV_A |
ENUMERATION |
CddPwmSetRelativeThreshold |
Switches the API Cdd_Pwm_SetRelativeThreshold |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmSetAbsoluteThreshold |
Switches the API Cdd_Pwm_SetAbsoluteThreshold. |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmSetPinAction |
Switches the API Cdd_Pwm_SetPinAction |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmSetPeriodDutyPhase |
Switches the API Cdd_Pwm_SetPeriodDutyPhase |
TRUE |
TRUE/FALSE |
BOOLEAN |
CddPwmCBCTZ2 |
Enable / disable cycle by cycle trip zone |
FALSE |
TRUE/FALSE |
BOOLEAN |
CddPwmCBCTZ3 |
Enable / disable cycle by cycle trip zone |
FALSE |
TRUE/FALSE |
BOOLEAN |
CddPwmCBCTZ4 |
Enable / disable cycle by cycle trip zone |
FALSE |
TRUE/FALSE |
BOOLEAN |
CddPwmCBCTZ5 |
Enable / disable cycle by cycle trip zone |
FALSE |
TRUE/FALSE |
BOOLEAN |
CddPwmCBCTZ6 |
Enable / disable cycle by cycle trip zone |
FALSE |
TRUE/FALSE |
BOOLEAN |
CddPwmCBCDCAEVT2 |
Enable / disable cycle by cycle Digital comapre A event |
FALSE |
TRUE/FALSE |
BOOLEAN |
4.6.10.3. Symbolic Names deviations¶
None
4.6.10.4. Configuration rules and constraints to enable plausibility checks¶
None.
4.6.11. Memory Mapping¶
Memory Mapping Sections |
CDD_PWM_CODE |
CDD_PWM_CODE_ISR |
CDD_PWM_VAR_INIT |
CDD_PWM_VAR_NO_INIT |
CDD_PWM_PBCFG |
|---|---|---|---|---|---|
CDD_PWM_START_SEC_VAR_INIT_8(.bss) |
x |
||||
CDD_PWM_STOP_SEC_VAR_INIT_8 |
x |
||||
CDD_PWM_START_SEC_CONFIG_DATA (.const) |
x |
||||
CDD_PWM_STOP_SEC_CONFIG_DATA |
x |
||||
CDD_PWM_START_SEC_CODE(.text) |
x |
||||
CDD_PWM_STOP_SEC_CODE |
x |
||||
CDD_PWM_START_SEC_VAR_NO_INIT_16(.bss) |
x |
||||
CDD_PWM_STOP_SEC_VAR_NO_INIT_16 |
x |
||||
CDD_PWM_START_SEC_VAR_NO_INIT_32(.bss) |
x |
||||
CDD_PWM_STOP_SEC_VAR_NO_INIT_32 |
x |
||||
CDD_PWM_START_SEC_ISR_CODE |
x |
||||
CDD_PWM_STOP_SEC_ISR_CODE |
x |
||||
CDD_PWM_START_SEC_VAR_NO_INIT_UNSPECIFIED |
x |
||||
CDD_PWM_STOP_SEC_VAR_NO_INIT_UNSPECIFIED |
x |
4.6.12. Memory footprint¶
Please refer Memory Footprint for more details.
4.6.13. Performance¶
CDD PWM Module Performance |
|
|---|---|
Input PWM Signal Period |
1ms |
Duty Cycle |
50% |
Time taken by Normal ISR to process |
0.3750us |
Time taken by tripzone ISR to process |
0.524us |
4.6.14. Example Usage¶
Cdd_Pwm example applications demonstrating the MCAL CDD PWM driver features is in folder <MCAL_ROOT>/examples/Epwm.
These application can be built from the build folder by giving :
“gmake -s epwm_app PLATFORM= am263”
“gmake -s epwm_app_tz PLATFORM= am263”
4.6.14.1. CDD PWM Signal verification Application¶
Module is tested in AM263-CC board.
Oscilloscope is used to monitor CDD PWM dutycycle and frequency Variation
The CDD PWM module example is configured with channel ID 0 and 1 , which is mapped to physical channel EPWM0 and EPWM1
Connect EPWM output pin of 0 and 1st channel to Oscilloscope and check the output in CRO
Example code is tested for:
Frequency and DutyCycle Variation.
PWM Interrupt Verification.
PWM module triggering ADC module.
4.6.14.2. Trip- Zone Application¶
Trip Zone Signal is tested on GPIO 122 Pin.
Connect Jumper Wire to GPIO 122 pin and keep it open
when in terminal it shows to move the state from high to low, move the GPIO122 pin to high to low then tripzone interrupt occur to take configured action i.e high , low , high Impendence , No change
The Coressponding action we can observe in CRO
Change the GPIO 122 to low to high state and observe normal pwm signal
Since Cdd_PWM supports so many other features listed below :
4.6.14.2.1. CddPwm_DeadBand:¶
The DeadBand feature can be tested by following Points
Invoke Cdd_Pwm_Init() with necessary configurtion Parameters
Make pwm signal to idle by calling Cdd_Pwm_SetOutputToIdle()
Configure the necessary deadband related parametrs and Invoke Cdd_Pwm_DeadbandCfg()
Invoke Cdd_Pwm_SetPeriodDutyPhase() and observe the filterd signgal in CRO
4.6.14.2.2. Cdd_Pwm_ChopperCfg:¶
The Chopper feature can be tested by following Points
Invoke Cdd_Pwm_Init() with necessary configurtion Parameters
Configure dutyCycle by Invoking Cdd_Pwm_SetPeriodDutyPhase().
Configure the necessary chopper related parametrs and Invoke Cdd_Pwm_ChopperCfg().
Enable chopper feature by invoking Cdd_Pwm_ChopperEnable() with enablechopper parameter as TRUE and observe the signgal in CRO showing chopping action.
Chopping action can be disabled by invoking Cdd_Pwm_ChopperEnable() with enablechopper parameter as FALSE.
4.6.14.2.3. CddPwm_HrDutyCycle:¶
The CddPwm HRdutyCycle feature can be tested by following Points
Invoke Cdd_Pwm_Init() by enabling HRPWM in Configuartion Parametrs
Invoke Cdd_Pwm_HrSetPeriodDutyPhase() with Proper DutyCycle.
Observe the DutyCycle value in CRO matches with the configured dutyCycle or not.
4.6.14.2.4. CddPwm_HrUpDown :¶
The CddPwm HRdutyCycle feature can be tested by following Points
Invoke Cdd_Pwm_Init() by enabling HRPWM and setting the updown mode in Configuartion Parametrs
Invoke Cdd_Pwm_HrSetPeriodDutyPhase() with Proper DutyCycle.
Observe the DutyCycle value in CRO matches with the configured dutyCycle or not in Updown mode.
4.6.14.2.5. Cdd_PWM_AdvanceTripzone:¶
The CddPwm Advance TripZone feature can be tested by following Points
Invoke Cdd_Pwm_Init() by enabling Advance Tripzone and digital compare in Configuartion Parametrs
Configure dutyCycle by Invoking Cdd_Pwm_SetPeriodDutyPhase().
Enable the TripZone Interrupt for particular by Invoking Cdd_Pwm_TzIntrEnable().
Add Delay and make GPIO122 pin high to low to generate Advance TripZone Interrupt to take configured action.
That Action we can observe In CRO (i.e high state ,Low state , High Impendence , No change , Toggle state)
Place the GPIO122 Pin to normal state low to high to observe normal pwm signal.
4.6.14.3. Example Logs CDD PWM Signal¶
CDD_PWM_APP: Sample Application - STARTS !!!
CDD PWM MCAL Version Info
---------------------
Vendor ID : 44
Module ID : 255
SW Major Version : 9
SW Minor Version : 1
SW Patch Version : 0
PWM Signal is generated with default configured parameters.
PWM Signal is generated with below parameters on Channel A and B Pins.
: PERIOD 2500 : FREQUENCY 10000 : DUTYCYCLE in percentage 75 : DUTYCYCLE in Count 49152 :
PWM Signal is generated with below parameters on Channel A.
: PERIOD 5000 : FREQUENCY 5000 : DUTYCYCLE in percentage 50 : DUTYCYCLE in Count 32768 :
PWM Signal is generated with below parameters on Channel B.
: PERIOD 5000 : FREQUENCY 5000 : DUTYCYCLE in percentage 25 : DUTYCYCLE in Count 16384 :
ADC Test Application In Progress.
ADC Test Application Passed.
Edge Interrupt is enable.
Wait till interrupt is recived.
Interrupts Recieved are : 40480
CDD_PWM_APP: Sample Application - DONE !!!
CDD Stack Usage: 960 bytes
All tests have passed
4.6.14.4. Tripzone Application Testing¶
CDD_PWM_APP: Sample Application - STARTS !!!
CDD PWM MCAL Version Info
---------------------
Vendor ID : 44
Module ID : 255
SW Major Version : 9
SW Minor Version : 1
SW Patch Version : 0
Keep the GPIO 122 to High State.
PWM Signal is generated with default configured parameters.
Wait for sometime and Change the GPIO 122 to Low State from High State.
Trip zone signal occurred
new GPIO122 state : 1
PWM Signal is generated with below parameters on Channel A and B Pins.
: PERIOD 2500 : FREQUENCY 10000 : DUTYCYCLE in percentage 75 : DUTYCYCLE in Count 49152 :
Wait for sometime and Change the GPIO 122 to Low State from High State.
Trip zone signal occurred
PWM Signal is generated with below parameters on Channel A and B Pins.
: PERIOD 25000 : FREQUENCY 1000 : DUTYCYCLE in percentage 50 : DUTYCYCLE in Count 32768 :
CDD_PWM_APP: Sample Application - DONE !!!
CDD Stack Usage: 792 bytes
All tests have passed
4.6.15. FAQ’s¶
Will be updated in future release
4.6.16. Test Report(Link to test report)¶
Please refer AM26x CDD PWM Driver Test Report provided as part of CSP.
4.6.17. References¶
4.6.18. TI Disclaimer¶
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