mibspi/v0/mibspi.h

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/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef MIBSPI_H_
#define MIBSPI_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <kernel/dpl/SystemP.h>
#include <kernel/dpl/SemaphoreP.h>
#include <kernel/dpl/HwiP.h>
#include <drivers/hw_include/csl_types.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/hw_include/cslr_mibspi.h>
#include <drivers/hw_include/cslr.h>
#include <drivers/edma.h>
#include <drivers/mibspi/v0/soc/mibspi_soc.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
typedef void *MIBSPI_Handle;
 
#define MIBSPI_RAM_BUFFER_MODE              (7U)
 
#define MIBSPI_SLAVEMODE_TRANS_GROUP        (0U)
 
#define MIBSPI_INT_LEVEL                    (1U)
 
#define MIBSPI_FEATURE_PARALLEL_MODE_ENA        (0x1U << 0)
 
#define MIBSPI_FEATURE_PARALLEL_MODE_DIS        (0U)
 
#define MIBSPI_FEATURE_MODULO_MODE_ENA          (0x1U << 1)
 
#define MIBSPI_FEATURE_MODULO_MODE_DIS          (0U)
 
#define MIBSPI_FEATURE_SPIENA_PIN_ENA           (0x1U << 2)
 
#define MIBSPI_FEATURE_SPIENA_PIN_DIS           (0U)
 
#define MIBSPI_RAM_MAX_ELEM          (128U)
 
#define MIBSPI_SLAVE_MAX             (3U)
 
#define MIBSPI_DMA_REQLINE_MAX       (3U)
 
#define MIBSPI_MAX_CS                (MIBSPI_SLAVE_MAX)
 
#define MIBSPI_NUM_TRANS_GROUP       (8U)
 
#define MIBSPI_NUM_DMA_GROUP         (8U)
 
#define MIBSPI_CS_NONE               (0xFFU)
 
/* ========================================================================== */
/*                           enums                                            */
/* ========================================================================== */
 
enum MIBSPI_EdmaCBFlag_e
{
    MIBSPI_NONE_EDMA_CALLBACK_OCCURED  =   0x0U,
    MIBSPI_TX_EDMA_CALLBACK_OCCURED    =   0x1U,
    MIBSPI_RX_EDMA_CALLBACK_OCCURED    =   0x2U,
};
 
enum MIBSPI_XferErr_e {
    MIBSPI_XFER_ERR_NONE,   /* No transfer error */
    MIBSPI_XFER_ERR_RXOR,   /* Receiver overrun error */
    MIBSPI_XFER_ERR_BE,     /* Bit error */
    MIBSPI_XFER_ERR_TIMEOUT /* Transfer timeout error */
};
 
typedef enum {
    MIBSPI_TRANSFER_COMPLETED = 0,
    MIBSPI_TRANSFER_STARTED,
    MIBSPI_TRANSFER_CANCELED,
    MIBSPI_TRANSFER_FAILED,
    MIBSPI_TRANSFER_CSN_DEASSERT,
    MIBSPI_TRANSFER_TIMEOUT
} MIBSPI_Status;
 
typedef enum {
    MIBSPI_PINMODE_3PIN     = 0,      
    MIBSPI_PINMODE_4PIN_CS  = 1       
} MIBSPI_PinMode;
 
typedef enum {
    MIBSPI_MSB_FIRST = 0,    
    MIBSPI_LSB_FIRST = 1     
} MIBSPI_DataShiftFmt;
 
typedef enum {
    MIBSPI_LOOPBK_DIGITAL = 0,    
    MIBSPI_LOOPBK_ANALOG  = 1,    
    MIBSPI_LOOPBK_NONE    = 2,    
} MIBSPI_LoopBackType;
 
typedef enum {
    MIBSPI_MASTER      = 0,    
    MIBSPI_SLAVE       = 1     
} MIBSPI_Mode;
 
typedef enum {
    MIBSPI_POL0_PHA0   = 0,    
    MIBSPI_POL0_PHA1   = 1,    
    MIBSPI_POL1_PHA0   = 2,    
    MIBSPI_POL1_PHA1   = 3,    
} MIBSPI_FrameFormat;
 
typedef enum {
    MIBSPI_MODE_BLOCKING,
    MIBSPI_MODE_CALLBACK
} MIBSPI_TransferMode;
 
typedef enum {
    MIBSPI_DMACTRL_CH_TX,   
    MIBSPI_DMACTRL_CH_RX,   
    MIBSPI_DMACTRL_CH_BOTH, 
} MIBSPI_DmaCtrlChType;
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
typedef struct
{
    uint32_t    dlenErr;
    uint32_t    timeout;
    uint32_t    parErr;
    uint32_t    desync;
    uint32_t    bitErr;
    uint32_t    rxOvrnErr;
    uint32_t    rxFull;
    uint32_t    txEmpty;
    uint32_t    tgComplete[MIBSPI_NUM_TRANS_GROUP];
}MIBSPI_HW_Stats;
 
typedef struct
{
    uint32_t   dlenErr;     
    uint32_t   timeout;     
    uint32_t   parErr;      
    uint32_t   desync;      
    uint32_t   bitErr;      
    uint32_t   rxOvrnErr;   
} MIBSPI_Stats;
 
typedef struct
{
    uint8_t             chipSelect;   
    uint8_t             ramBufLen;    
    uint32_t            dmaReqLine;   
} MIBSPI_SlaveProfile;
 
typedef struct
{
    uint32_t            dmaReqLine;    
    uint8_t             chipSelect;    
} MIBSPI_SlaveModeParams;
 
typedef struct
{
    uint32_t    rxDmaIntCnt;
    uint32_t    txDmaIntCnt;
} MIBSPI_DriverDmaInfo;
 
typedef struct
{
    uint8_t     txDmaReqLine;
    uint8_t     rxDmaReqLine;
}MIBSPI_DMAReqlineCfg;
 
typedef struct
{
    uintptr_t saddr; 
    uintptr_t daddr; 
} MIBSPI_DMAXferAddrInfo;
 
typedef struct
{
    uint16_t elemSize; 
    uint16_t elemCnt;  
    uint16_t frameCnt; 
} MIBSPI_DMAXferSizeInfo;
 
typedef struct
{
    MIBSPI_DMAXferAddrInfo tx;   
    MIBSPI_DMAXferAddrInfo rx;   
    MIBSPI_DMAXferSizeInfo size; 
    uint32_t  dmaReqLine;        
} MIBSPI_DMAXferInfo;
 
typedef struct
{
    /* User input (write-only) fields */
    uint32_t   count;      
    void      *txBuf;      
    void      *rxBuf;      
    void      *arg;        
    /* User output (read-only) fields */
    MIBSPI_Status status;     
    uint8_t   slaveIndex; 
} MIBSPI_Transaction;
 
typedef struct
{
    volatile enum MIBSPI_EdmaCBFlag_e edmaCbCheck;    
    enum MIBSPI_XferErr_e             transferErr;    
    MIBSPI_Transaction               *transaction;    
    volatile uint16_t                 remainSize;     
    volatile uint16_t                 dataLength;     
    volatile uint16_t                 dataSizeInBytes;
} MIBSPI_TransactionState;
 
typedef void        (*MIBSPI_CallbackFxn) (MIBSPI_Handle handle,
                                           MIBSPI_Transaction *transaction);
 
/* ========================================================================== */
/*                  Internal/Private Structure Declarations                   */
/* ========================================================================== */
 
typedef struct
{
    uint32_t            bitRate;                        
    uint8_t             numSlaves;                      
    uint8_t             t2cDelay;                       
    uint8_t             c2tDelay;                       
    uint8_t             wDelay;                         
    MIBSPI_SlaveProfile    slaveProf[MIBSPI_SLAVE_MAX]; 
} MIBSPI_MasterModeParams;
 
typedef struct
{
    uint32_t edmaTcc;
    uint32_t edmaChId;
    uint32_t edmaParam;
} MIBSPI_EDMAChParams;
 
typedef struct
{
    MIBSPI_Mode            mode;                
    MIBSPI_TransferMode    transferMode;        
    Bool                   iCountSupport;       
    MIBSPI_CallbackFxn     transferCallbackFxn; 
    uint32_t               dataSize;            
    MIBSPI_FrameFormat     frameFormat;         
    union
    {
        MIBSPI_MasterModeParams  masterParams;  
        MIBSPI_SlaveModeParams   slaveParams;   
    }u;                                         
    MIBSPI_PinMode         pinMode;             
    MIBSPI_DataShiftFmt    shiftFormat;         
    uint8_t                dmaEnable;           
    int32_t                edmaInst;            
    void                   *dmaHandle;         
    uint8_t                eccEnable;           
    uint8_t                csHold;              
    uint16_t               txDummyValue;        
    uint32_t               transferTimeout;     
    Bool                   compatibilityMode;   
    uint16_t               edmaLinkParamId;     
} MIBSPI_OpenParams;
 
typedef struct
{
    uint32_t                 mibspiInstId;
    CSL_mss_spiRegs         *ptrSpiRegBase;
    CSL_mibspiRam           *ptrMibSpiRam;
    uint32_t                 clockSrcFreq;
    uint32_t                 interrupt0Num;
    uint32_t                 interrupt1Num;
    uint32_t                 mibspiRamSize;
    uint32_t                 numTransferGroups;
    uint32_t                 numParallelModePins;
    uint32_t                 featureBitMap;
    uint32_t                 numDmaReqLines;
    MIBSPI_DMAReqlineCfg     dmaReqlineCfg[MIBSPI_DMA_REQLINE_MAX];
} MIBSPI_Attrs;
 
typedef struct
{
    MIBSPI_Handle             mibspiHandle;
    const MIBSPI_Attrs        *ptrHwCfg;
    MIBSPI_OpenParams          params;
    MIBSPI_DriverDmaInfo       dmaInfo[MIBSPI_SLAVE_MAX];
    uint8_t                    rambufStart[MIBSPI_SLAVE_MAX];
    uint8_t                    rambufEnd[MIBSPI_SLAVE_MAX];
    uint16_t                   rxScratchBuffer;
    uint16_t                   txScratchBuffer;
     /*
     * State variables
     */
    uint32_t                   isOpen;
    void                      *transferSem;
    SemaphoreP_Object          transferSemObj;
    void                      *hwiHandle;
    HwiP_Object                hwiObj;
    MIBSPI_HW_Stats     hwStats;
    MIBSPI_TransactionState transactionState;
    uint32_t                edmaBaseAddr;
    uint32_t                edmaRegionId;
    MIBSPI_EDMAChParams     edmaParamsTx[MIBSPI_DMA_REQLINE_MAX];
    MIBSPI_EDMAChParams     edmaParamsRx[MIBSPI_DMA_REQLINE_MAX];
    Edma_IntrObject         intrTxObj;
    Edma_IntrObject         intrRxObj;
    Edma_IntrObject         intrDummyObj;
} MIBSPI_Object;
 
typedef struct
{
    const MIBSPI_Attrs      *attrs;
    MIBSPI_Object           *object;
} MIBSPI_Config;
 
extern MIBSPI_Config         gMibspiConfig[];
extern uint32_t              gMibspiConfigNum;
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void MIBSPI_init(void);
 
void MIBSPI_deinit(void);
 
MIBSPI_Handle MIBSPI_open(uint32_t index, MIBSPI_OpenParams *params);
 
void MIBSPI_close(MIBSPI_Handle handle);
 
int32_t MIBSPI_transfer(MIBSPI_Handle handle, MIBSPI_Transaction *transaction);
 
void MIBSPI_transferCancel(MIBSPI_Handle handle);
 
 int32_t MIBSPI_enableLoopback(MIBSPI_Handle handle,
                               MIBSPI_LoopBackType loopbacktype);
 
 int32_t MIBSPI_disableLoopback(MIBSPI_Handle handle);
 
 int32_t MIBSPI_setClockPhasePolarity(MIBSPI_Handle handle,
                                      uint8_t clockFmt);
 
 int32_t MIBSPI_getDrvStats(MIBSPI_Handle handle,
                            MIBSPI_Stats *ptrStats);
 
void MIBSPI_dmaDoneCb(MIBSPI_Handle mibspiHandle);
 
static inline void MIBSPI_Params_init(MIBSPI_OpenParams *openPrms);
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
static inline void MIBSPI_Params_init(MIBSPI_OpenParams *openPrms)
{
    if (openPrms != NULL)
    {
        openPrms->mode                  = MIBSPI_MASTER;
        openPrms->dataSize              = 16U;
        openPrms->frameFormat           = MIBSPI_POL0_PHA0;
        openPrms->transferMode          = MIBSPI_MODE_BLOCKING;
        openPrms->iCountSupport         = FALSE;
        openPrms->transferCallbackFxn   = NULL;
        openPrms->pinMode               = MIBSPI_PINMODE_4PIN_CS;
        openPrms->shiftFormat           = MIBSPI_MSB_FIRST;
        openPrms->dmaEnable             = (uint8_t)1U;
        openPrms->eccEnable             = (uint8_t)0U;
        openPrms->csHold                = (uint8_t)0U;
        openPrms->txDummyValue          = (uint16_t)0xFFFFU;
        openPrms->transferTimeout       = 0xFFFFFFFFU;
        openPrms->compatibilityMode     = FALSE;
 
        /* Initlaize master mode params */
        openPrms->u.masterParams.bitRate   = 5000000U;
        openPrms->u.masterParams.numSlaves = 1;
        openPrms->u.masterParams.t2cDelay  = 0;
        openPrms->u.masterParams.c2tDelay  = 0;
        openPrms->u.masterParams.wDelay    = 0;
        openPrms->u.masterParams.slaveProf[0].chipSelect = (uint8_t)0U;
        openPrms->u.masterParams.slaveProf[0].ramBufLen = (uint8_t)MIBSPI_RAM_MAX_ELEM;
        openPrms->u.masterParams.slaveProf[0].dmaReqLine = 0U;
    }
}
 
#ifdef __cplusplus
}
#endif
 
#endif /* #ifndef MIBSPI_H_ */