The VISS kernels in this kernel extension. More...

#include <VX/vx.h>
#include <VX/vx_kernels.h>
#include <TI/hwa_vpac_viss_fcp.h>
#include <TI/hwa_vpac_viss1.h>

Data Structures
struct	tivx_ae_awb_params_t
	Data corresponding to results of 2A algorithm. More...

struct	tivx_h3a_aew_config
	H3A AEW configuration data structure used by the TIVX_KERNEL_VISS kernel. More...

struct	tivx_h3a_data_t
	The h3a_output data structure used by the TIVX_KERNEL_VISS kernel. More...

struct	tivx_vpac_viss_safety_mechanism_params_t
	Safety parameters structure for VPAC VISS. More...

Macros
#define	TIVX_KERNEL_VPAC_VISS_NAME "com.ti.hwa.vpac_viss"
	vpac_viss kernel name

#define	TIVX_VPAC_VISS_CMD_SET_DCC_PARAMS (0x30000000u)
	Control Command to set the DCC (Dynamic Camera Configuration) information to the given VISS Node. More...

#define	TIVX_VPAC_VISS_CMD_GET_ERR_STATUS (0x30000001u)
	Control Command to get the combined error status Returns the combined error status of the last processed frame, incorporating error interrupts and watchdog timer error interrupt. A reference to vx_scalar is passed as an argument with this control command. The node returns a bit-mask of the error status in the U32 variable of vx_scalar. More...

#define	TIVX_VPAC_VISS_CMD_GET_PSA_STATUS (0x30000002u)
	Control Command to retrieve the PSA signature values.

#define	TIVX_VPAC_VISS_CMD_ENABLE_ERROR_EVENTS (0x30000004u)
	Control Command to enable/disable error events.

#define	TIVX_VPAC_VISS_CMD_ENABLE_SAFETY_MECHANISM (0x30000005u)
	Control Command to enable VPAC VISS safety mechanism User data object tivx_vpac_viss_safety_mechanism_params_t is passed as argument with this control command.

#define	TIVX_VPAC_VISS_MAX_H3A_STAT_NUMBYTES (24576U)
	Maximum H3A number of bytes in statistics data array. More...

#define	TIVX_VPAC_VISS_H3A_OUT_BUFF_ALIGN (64U)
	The H3A output memory address alignment. More...

#define	TIVX_VPAC_VISS_H3A_IN_RAW0 (0U)

#define	TIVX_VPAC_VISS_H3A_IN_RAW1 (1U)

#define	TIVX_VPAC_VISS_H3A_IN_RAW2 (2U)

#define	TIVX_VPAC_VISS_H3A_IN_LSC (3U)

#define	TIVX_VPAC_VISS_H3A_MODE_AEWB (0U)

#define	TIVX_VPAC_VISS_H3A_MODE_AF (1U)

#define	TIVX_VPAC_VISS_FCP0 (0U)

#define	TIVX_VPAC_VISS_FCP1 (1U)

#define	TIVX_VPAC_VISS_FCP_OUT0 (0U)

#define	TIVX_VPAC_VISS_FCP_OUT1 (0U)

#define	TIVX_VPAC_VISS_FCP_OUT2 (1U)

#define	TIVX_VPAC_VISS_FCP_OUT3 (1U)

#define	TIVX_VPAC_VISS_FCP_OUT4 (0U)

#define	TIVX_VPAC_VISS_FCP1_DISABLED (0U)

#define	TIVX_VPAC_VISS_FCP1_INPUT_RFE (1U)

#define	TIVX_VPAC_VISS_FCP1_INPUT_CAC (2U)

#define	TIVX_VPAC_VISS_FCP1_INPUT_NSF4 (3U)

#define	TIVX_VPAC_VISS_FCP1_INPUT_GLBCE (4U)

#define	TIVX_VPAC_VISS_MAP_FCP_OUTPUT(fcp, output) (output<<1 \| fcp)

#define	TIVX_VPAC_VISS_WDTIMER_DISABLE (0u)
	Disable Watchdog Timer (default)

#define	TIVX_VPAC_VISS_WDTIMER_ENABLE (1u)
	Enable Watchdog Timer.

#define	TIVX_VPAC_VISS_WDTIMER_64K_CYCLES (0u)
	Watchdog Timer timeout: 64K cycles (default)

#define	TIVX_VPAC_VISS_WDTIMER_128K_CYCLES (1u)
	Watchdog Timer timeout: 128K cycles.

#define	TIVX_VPAC_VISS_RAWFE_CFG_ERR_INTR (0x1U)
	Config read or write memory acccess occurred during functional operation and likely corrupted functional opertion. VISS merges all config error sources from RawFE and refer to RawFE spec for the entire error source list.

#define	TIVX_VPAC_VISS_RAWFE_AEW_PULSE_INTR (0x2U)

#define	TIVX_VPAC_VISS_RAWFE_AF_PULSE_INTR (0x4U)

#define	TIVX_VPAC_VISS_RAWFE_H3A_PULSE_INTR (0x8U)

#define	TIVX_VPAC_VISS_RAWFE_H3A_BUF_OVRFLOW_PULSE_INTR (0x10U)

#define	TIVX_VPAC_VISS_NSF4V_LINEMEM_CFG_ERR_INTR (0x20U)

#define	TIVX_VPAC_VISS_NSF4V_HBLANK_ERR_INTR (0x40U)

#define	TIVX_VPAC_VISS_NSF4V_VBLANK_ERR_INTR (0x80U)

#define	TIVX_VPAC_VISS_GLBCE_CFG_ERR_INTR (0x100U)

#define	TIVX_VPAC_VISS_GLBCE_FILT_START_INTR (0x200U)

#define	TIVX_VPAC_VISS_GLBCE_FILT_DONE_INTR (0x400U)

#define	TIVX_VPAC_VISS_GLBCE_HSYNC_ERR_INTR (0x800U)

#define	TIVX_VPAC_VISS_GLBCE_VSYNC_ERR_INTR (0x1000U)

#define	TIVX_VPAC_VISS_GLBCE_VP_ERR_INTR (0x2000U)

#define	TIVX_VPAC_VISS_FCFA_CFG_ERR_INTR (0x4000U)

#define	TIVX_VPAC_VISS_FCC_CFG_ERR_INTR (0x8000U)

#define	TIVX_VPAC_VISS_FCC_OUTIF_OVF_ERR_INTR (0x10000U)

#define	TIVX_VPAC_VISS_FCC_HIST_READ_ERR_INTR (0x20000U)

#define	TIVX_VPAC_VISS_EE_CFG_ERR (0x40000U)

#define	TIVX_VPAC_VISS_EE_SYNCOVF_ERR (0x80000U)

#define	TIVX_VPAC_VISS_LSE_FR_DONE_EVT_INTR (0x100000U)

#define	TIVX_VPAC_VISS_LSE_SL2_RD_ERR_INTR (0x200000U)

#define	TIVX_VPAC_VISS_LSE_SL2_WR_ERR_INTR (0x400000U)

#define	TIVX_VPAC_VISS_LSE_CAL_VP_ERR_INTR (0x800000U)

#define	TIVX_VPAC_VISS_WDTIMER_ERR (0x40000000U)

Functions
void	tivxRegisterHwaTargetVpacVissKernels (void)
	Function to register HWA Kernels on the vpac_viss Target.

void	tivxUnRegisterHwaTargetVpacVissKernels (void)
	Function to un-register HWA Kernels on the vpac_viss Target.

void	tivx_vpac_viss_params_init (tivx_vpac_viss_params_t *prms)
	Function to initialize VISS Parameters. More...

void	tivx_h3a_data_init (tivx_h3a_data_t *prms)
	Function to initialize H3A data Parameters. More...

void	tivx_ae_awb_params_init (tivx_ae_awb_params_t *prms)
	Function to initialize AEWB Output Parameters These parameters come from the AEWB algorithm. More...

void	tivx_h3a_aew_config_init (tivx_h3a_aew_config *prms)
	Function to initialize H3A aew Config. More...

void	tivx_vpac_viss_safety_mech_prms_init (tivx_vpac_viss_safety_mechanism_params_t *prms)
	Function to initialize VISS safety mechanism parameters with default values. More...

VX_API_ENTRY vx_node VX_API_CALL	tivxVpacVissNode (vx_graph graph, vx_user_data_object configuration, vx_user_data_object ae_awb_result, vx_user_data_object dcc_buf, tivx_raw_image raw, vx_image output0, vx_image output1, vx_image output2, vx_image output3, vx_image output4, vx_user_data_object h3a_output, vx_distribution histogram0, vx_distribution histogram1, vx_distribution raw_histogram)
	[Graph] Creates a VPAC_VISS Node.