4.13.7.1. J721e Peripheral Interrupt Source Descriptions¶

4.13.7.1.1. Introduction¶

This chapter provides information on peripheral interrupt source IDs that are permitted in the j721e SoC. The interrupt source IDs represent outputs from SoC peripherals capable of generating an egress interrupt or event signal. The System Firmware interrupt management TISCI message APIs take interrupt source IDs as input to set and release interrupt routes between source peripherals and destination host processors.

4.13.7.1.2. Event-Based Interrupt Source IDs¶

Device Name	Device ID	Interrupt Source Name	Interrupt Source Index
J721E_DEV_NAVSS0_RINGACC_0	211	Ring events	0 to 973
J721E_DEV_MCU_NAVSS0_RINGACC0	235	Ring events	0 to 255
J721E_DEV_NAVSS0_RINGACC_0	211	Ring monitor events	1024 to 1055
J721E_DEV_MCU_NAVSS0_RINGACC0	235	Ring monitor events	1024 to 1055
J721E_DEV_NAVSS0_RINGACC_0	211	Ring global error event	2048
J721E_DEV_MCU_NAVSS0_RINGACC0	235	Ring global error event	2048
J721E_DEV_NAVSS0_UDMAP_0	212	UDMA transmit channel OES events	0 to 299
J721E_DEV_NAVSS0_UDMAP_0	212	UDMA transmit channel EOES events	512 to 811
J721E_DEV_NAVSS0_UDMAP_0	212	UDMA receive channel OES events	1024 to 1163
J721E_DEV_NAVSS0_UDMAP_0	212	UDMA receive channel EOES events	1280 to 1419
J721E_DEV_NAVSS0_UDMAP_0	212	UDMA global configuration invalid flow event	1536
J721E_DEV_MCU_NAVSS0_UDMAP_0	236	UDMA transmit channel OES events	0 to 47
J721E_DEV_MCU_NAVSS0_UDMAP_0	236	UDMA transmit channel EOES events	512 to 559
J721E_DEV_MCU_NAVSS0_UDMAP_0	236	UDMA receive channel OES events	1024 to 1071
J721E_DEV_MCU_NAVSS0_UDMAP_0	236	UDMA receive channel EOES events	1280 to 1327
J721E_DEV_MCU_NAVSS0_UDMAP_0	236	UDMA global configuration invalid flow event	1536
J721E_DEV_NAVSS0_PROXY_0	210	Proxy events	0 to 63
J721E_DEV_MCU_NAVSS0_PROXY0	234	Proxy events	0 to 63

4.13.7.1.3. Non-Event Interrupt Source IDs¶

Device Name	Device ID	Interrupt Source Design Name	Interrupt Source Index
J721E_DEV_AASRC0	139	err_level 0	0
J721E_DEV_AASRC0	139	infifo_level 0	1
J721E_DEV_AASRC0	139	ingroup_level 0	2
J721E_DEV_AASRC0	139	outfifo_level 0	3
J721E_DEV_AASRC0	139	outgroup_level 0	4
J721E_DEV_COMPUTE_CLUSTER0	3	gic_output_waker_gic_pwr0_wake_request 0 to 1	0 to 1
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	soc_events_out_level 0 to 31	0 to 31
J721E_DEV_CPSW0	19	cpts_comp 0	0
J721E_DEV_CPSW0	19	cpts_genf0 0	1
J721E_DEV_CPSW0	19	cpts_genf1 0	2
J721E_DEV_CPSW0	19	cpts_sync 0	3
J721E_DEV_CPSW0	19	evnt_pend 0	4
J721E_DEV_CPSW0	19	mdio_pend 0	5
J721E_DEV_CPSW0	19	stat_pend 0	6
J721E_DEV_CSI_RX_IF0	26	csi_err_irq 0	0
J721E_DEV_CSI_RX_IF0	26	csi_irq 0	1
J721E_DEV_CSI_RX_IF0	26	csi_level 0	2
J721E_DEV_CSI_RX_IF1	27	csi_err_irq 0	0
J721E_DEV_CSI_RX_IF1	27	csi_irq 0	1
J721E_DEV_CSI_RX_IF1	27	csi_level 0	2
J721E_DEV_CSI_TX_IF0	28	csi_interrupt 0	0
J721E_DEV_CSI_TX_IF0	28	csi_level 0	1
J721E_DEV_DCC0	30	intr_done_level 0	0
J721E_DEV_DCC1	31	intr_done_level 0	0
J721E_DEV_DCC10	41	intr_done_level 0	0
J721E_DEV_DCC11	42	intr_done_level 0	0
J721E_DEV_DCC12	43	intr_done_level 0	0
J721E_DEV_DCC2	32	intr_done_level 0	0
J721E_DEV_DCC3	33	intr_done_level 0	0
J721E_DEV_DCC4	34	intr_done_level 0	0
J721E_DEV_DCC5	36	intr_done_level 0	0
J721E_DEV_DCC6	37	intr_done_level 0	0
J721E_DEV_DCC7	38	intr_done_level 0	0
J721E_DEV_DCC8	39	intr_done_level 0	0
J721E_DEV_DCC9	40	intr_done_level 0	0
J721E_DEV_DDR0	47	ddrss_controller 0	0
J721E_DEV_DDR0	47	ddrss_hs_phy_global_error 0	1
J721E_DEV_DDR0	47	ddrss_pll_freq_change_req 0	2
J721E_DEV_DDR0	47	ddrss_v2a_other_err_lvl 0	3
J721E_DEV_DECODER0	144	irq 0	0
J721E_DEV_DSS0	152	dss_inst0_dispc_func_irq_proc0 0	0
J721E_DEV_DSS0	152	dss_inst0_dispc_func_irq_proc1 0	1
J721E_DEV_DSS0	152	dss_inst0_dispc_safety_error_irq_proc0 0	2
J721E_DEV_DSS0	152	dss_inst0_dispc_safety_error_irq_proc1 0	3
J721E_DEV_DSS0	152	dss_inst0_dispc_secure_irq_proc0 0	4
J721E_DEV_DSS0	152	dss_inst0_dispc_secure_irq_proc1 0	5
J721E_DEV_DSS_DSI0	150	dsi_0_func_intr 0	0
J721E_DEV_DSS_EDP0	151	intr 0 to 3	0 to 3
J721E_DEV_ECAP0	80	ecap_int 0	0
J721E_DEV_ECAP1	81	ecap_int 0	0
J721E_DEV_ECAP2	82	ecap_int 0	0
J721E_DEV_EHRPWM0	83	epwm_etint 0	0
J721E_DEV_EHRPWM0	83	epwm_tripzint 0	1
J721E_DEV_EHRPWM1	84	epwm_etint 0	0
J721E_DEV_EHRPWM1	84	epwm_tripzint 0	1
J721E_DEV_EHRPWM2	85	epwm_etint 0	0
J721E_DEV_EHRPWM2	85	epwm_tripzint 0	1
J721E_DEV_EHRPWM3	86	epwm_etint 0	0
J721E_DEV_EHRPWM3	86	epwm_tripzint 0	1
J721E_DEV_EHRPWM4	87	epwm_etint 0	0
J721E_DEV_EHRPWM4	87	epwm_tripzint 0	1
J721E_DEV_EHRPWM5	88	epwm_etint 0	0
J721E_DEV_EHRPWM5	88	epwm_tripzint 0	1
J721E_DEV_ELM0	89	elm_porocpsinterrupt_lvl 0	0
J721E_DEV_ENCODER0	153	irq 0	0
J721E_DEV_EQEP0	94	eqep_int 0	0
J721E_DEV_EQEP1	95	eqep_int 0	0
J721E_DEV_EQEP2	96	eqep_int 0	0
J721E_DEV_ESM0	97	esm_int_cfg_lvl 0	0
J721E_DEV_ESM0	97	esm_int_hi_lvl 0	1
J721E_DEV_ESM0	97	esm_int_low_lvl 0	2
J721E_DEV_GPIO0	105	gpio_bank 0 to 7	0 to 7
J721E_DEV_GPIO1	106	gpio_bank 0 to 2	0 to 2
J721E_DEV_GPIO2	107	gpio_bank 0 to 7	0 to 7
J721E_DEV_GPIO3	108	gpio_bank 0 to 2	0 to 2
J721E_DEV_GPIO4	109	gpio_bank 0 to 7	0 to 7
J721E_DEV_GPIO5	110	gpio_bank 0 to 2	0 to 2
J721E_DEV_GPIO6	111	gpio_bank 0 to 7	0 to 7
J721E_DEV_GPIO7	112	gpio_bank 0 to 2	0 to 2
J721E_DEV_GPMC0	115	gpmc_sinterrupt 0	0
J721E_DEV_GTC0	61	gtc_push_event 0	0
J721E_DEV_I2C0	187	pointrpend 0	0
J721E_DEV_I2C1	188	pointrpend 0	0
J721E_DEV_I2C2	189	pointrpend 0	0
J721E_DEV_I2C3	190	pointrpend 0	0
J721E_DEV_I2C4	191	pointrpend 0	0
J721E_DEV_I2C5	192	pointrpend 0	0
J721E_DEV_I2C6	193	pointrpend 0	0
J721E_DEV_I3C0	116	i3c__int 0	0
J721E_DEV_MCAN0	156	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN0	156	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN1	158	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN1	158	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN10	168	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN10	168	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN11	169	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN11	169	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN12	170	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN12	170	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN13	171	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN13	171	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN2	160	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN2	160	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN3	161	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN3	161	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN4	162	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN4	162	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN5	163	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN5	163	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN6	164	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN6	164	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN7	165	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN7	165	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN8	166	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN8	166	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCAN9	167	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCAN9	167	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCASP0	174	rec_intr_pend 0	0
J721E_DEV_MCASP0	174	xmit_intr_pend 0	1
J721E_DEV_MCASP1	175	rec_intr_pend 0	0
J721E_DEV_MCASP1	175	xmit_intr_pend 0	1
J721E_DEV_MCASP10	184	rec_intr_pend 0	0
J721E_DEV_MCASP10	184	xmit_intr_pend 0	1
J721E_DEV_MCASP11	185	rec_intr_pend 0	0
J721E_DEV_MCASP11	185	xmit_intr_pend 0	1
J721E_DEV_MCASP2	176	rec_intr_pend 0	0
J721E_DEV_MCASP2	176	xmit_intr_pend 0	1
J721E_DEV_MCASP3	177	rec_intr_pend 0	0
J721E_DEV_MCASP3	177	xmit_intr_pend 0	1
J721E_DEV_MCASP4	178	rec_intr_pend 0	0
J721E_DEV_MCASP4	178	xmit_intr_pend 0	1
J721E_DEV_MCASP5	179	rec_intr_pend 0	0
J721E_DEV_MCASP5	179	xmit_intr_pend 0	1
J721E_DEV_MCASP6	180	rec_intr_pend 0	0
J721E_DEV_MCASP6	180	xmit_intr_pend 0	1
J721E_DEV_MCASP7	181	rec_intr_pend 0	0
J721E_DEV_MCASP7	181	xmit_intr_pend 0	1
J721E_DEV_MCASP8	182	rec_intr_pend 0	0
J721E_DEV_MCASP8	182	xmit_intr_pend 0	1
J721E_DEV_MCASP9	183	rec_intr_pend 0	0
J721E_DEV_MCASP9	183	xmit_intr_pend 0	1
J721E_DEV_MCSPI0	266	intr_spi 0	0
J721E_DEV_MCSPI1	267	intr_spi 0	0
J721E_DEV_MCSPI2	268	intr_spi 0	0
J721E_DEV_MCSPI3	269	intr_spi 0	0
J721E_DEV_MCSPI4	270	intr_spi 0	0
J721E_DEV_MCSPI5	271	intr_spi 0	0
J721E_DEV_MCSPI6	272	intr_spi 0	0
J721E_DEV_MCSPI7	273	intr_spi 0	0
J721E_DEV_MCU_ADC12_16FFC0	0	gen_level 0	0
J721E_DEV_MCU_ADC12_16FFC1	1	gen_level 0	0
J721E_DEV_MCU_CPSW0	18	cpts_comp 0	0
J721E_DEV_MCU_CPSW0	18	cpts_genf0 0	1
J721E_DEV_MCU_CPSW0	18	cpts_genf1 0	2
J721E_DEV_MCU_CPSW0	18	cpts_sync 0	3
J721E_DEV_MCU_CPSW0	18	evnt_pend 0	4
J721E_DEV_MCU_CPSW0	18	mdio_pend 0	5
J721E_DEV_MCU_CPSW0	18	stat_pend 0	6
J721E_DEV_MCU_DCC0	44	intr_done_level 0	0
J721E_DEV_MCU_DCC1	45	intr_done_level 0	0
J721E_DEV_MCU_DCC2	46	intr_done_level 0	0
J721E_DEV_MCU_ESM0	98	esm_int_cfg_lvl 0	0
J721E_DEV_MCU_ESM0	98	esm_int_hi_lvl 0	1
J721E_DEV_MCU_ESM0	98	esm_int_low_lvl 0	2
J721E_DEV_MCU_FSS0_FSAS_0	101	ecc_intr_err_pend 0	0
J721E_DEV_MCU_FSS0_FSAS_0	101	otfa_intr_err_pend 0	1
J721E_DEV_MCU_FSS0_HYPERBUS1P0_0	102	hpb_intr 0	0
J721E_DEV_MCU_FSS0_OSPI_0	103	ospi_lvl_intr 0	0
J721E_DEV_MCU_FSS0_OSPI_1	104	ospi_lvl_intr 0	0
J721E_DEV_MCU_I2C0	194	pointrpend 0	0
J721E_DEV_MCU_I2C1	195	pointrpend 0	0
J721E_DEV_MCU_I3C0	117	i3c__int 0	0
J721E_DEV_MCU_I3C1	118	i3c__int 0	0
J721E_DEV_MCU_MCAN0	172	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCU_MCAN0	172	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCU_MCAN1	173	mcanss_ext_ts_rollover_lvl_int 0	0
J721E_DEV_MCU_MCAN1	173	mcanss_mcan_lvl_int 0 to 1	1 to 2
J721E_DEV_MCU_MCSPI0	274	intr_spi 0	0
J721E_DEV_MCU_MCSPI1	275	intr_spi 0	0
J721E_DEV_MCU_MCSPI2	276	intr_spi 0	0
J721E_DEV_MCU_NAVSS0_MCRC_0	238	dma_event_intr 0 to 3	0 to 3
J721E_DEV_MCU_NAVSS0_MCRC_0	238	intaggr_vintr_pend 0	4
J721E_DEV_MCU_SA2_UL0	265	sa_ul_pka 0	0
J721E_DEV_MCU_SA2_UL0	265	sa_ul_trng 0	1
J721E_DEV_MCU_TIMER0	35	intr_pend 0	0
J721E_DEV_MCU_TIMER1	71	intr_pend 0	0
J721E_DEV_MCU_TIMER2	72	intr_pend 0	0
J721E_DEV_MCU_TIMER3	73	intr_pend 0	0
J721E_DEV_MCU_TIMER4	74	intr_pend 0	0
J721E_DEV_MCU_TIMER5	75	intr_pend 0	0
J721E_DEV_MCU_TIMER6	76	intr_pend 0	0
J721E_DEV_MCU_TIMER7	77	intr_pend 0	0
J721E_DEV_MCU_TIMER8	78	intr_pend 0	0
J721E_DEV_MCU_TIMER9	79	intr_pend 0	0
J721E_DEV_MCU_UART0	149	usart_irq 0	0
J721E_DEV_MLB0	186	mlbss_mlb_ahb_int 0 to 1	0 to 1
J721E_DEV_MLB0	186	mlbss_mlb_int 0	2
J721E_DEV_MMCSD0	91	emmcss_intr 0	0
J721E_DEV_MMCSD1	92	emmcsdss_intr 0	0
J721E_DEV_MMCSD2	93	emmcsdss_intr 0	0
J721E_DEV_NAVSS0	199	cpts0_comp 0	0
J721E_DEV_NAVSS0	199	cpts0_genf0 0	1
J721E_DEV_NAVSS0	199	cpts0_genf1 0	2
J721E_DEV_NAVSS0	199	cpts0_genf2 0	3
J721E_DEV_NAVSS0	199	cpts0_genf3 0	4
J721E_DEV_NAVSS0	199	cpts0_genf4 0	5
J721E_DEV_NAVSS0	199	cpts0_genf5 0	6
J721E_DEV_NAVSS0	199	cpts0_sync 0	7
J721E_DEV_NAVSS0_CPTS_0	201	event_pend_intr 0	0
J721E_DEV_NAVSS0_MAILBOX_0	214	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_1	215	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_10	224	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_11	225	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_2	216	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_3	217	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_4	218	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_5	219	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_6	220	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_7	221	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_8	222	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MAILBOX_9	223	pend_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MCRC_0	227	dma_event_intr 0 to 3	0 to 3
J721E_DEV_NAVSS0_MCRC_0	227	intaggr_vintr_pend 0	4
J721E_DEV_NAVSS0_TBU_0	228	io_tbu0_ras_intr 0	0
J721E_DEV_NAVSS0_TCU_0	229	tcu_cmd_sync_ns_intr 0	3
J721E_DEV_NAVSS0_TCU_0	229	tcu_cmd_sync_s_intr 0	4
J721E_DEV_NAVSS0_TCU_0	229	tcu_event_q_ns_intr 0	5
J721E_DEV_NAVSS0_TCU_0	229	tcu_event_q_s_intr 0	6
J721E_DEV_NAVSS0_TCU_0	229	tcu_global_ns_intr 0	1
J721E_DEV_NAVSS0_TCU_0	229	tcu_global_s_intr 0	2
J721E_DEV_NAVSS0_TCU_0	229	tcu_ras_intr 0	0
J721E_DEV_PCIE0	239	pcie_cpts_comp 0	0
J721E_DEV_PCIE0	239	pcie_cpts_genf0 0	1
J721E_DEV_PCIE0	239	pcie_cpts_hw1_push 0	2
J721E_DEV_PCIE0	239	pcie_cpts_pend 0	3
J721E_DEV_PCIE0	239	pcie_cpts_sync 0	4
J721E_DEV_PCIE0	239	pcie_downstream_pulse 0	5
J721E_DEV_PCIE0	239	pcie_error_pulse 0	6
J721E_DEV_PCIE0	239	pcie_flr_pulse 0	7
J721E_DEV_PCIE0	239	pcie_hot_reset_pulse 0	8
J721E_DEV_PCIE0	239	pcie_legacy_pulse 0	9
J721E_DEV_PCIE0	239	pcie_link_state_pulse 0	10
J721E_DEV_PCIE0	239	pcie_local_level 0	11
J721E_DEV_PCIE0	239	pcie_phy_level 0	12
J721E_DEV_PCIE0	239	pcie_ptm_valid_pulse 0	13
J721E_DEV_PCIE0	239	pcie_pwr_state_pulse 0	14
J721E_DEV_PCIE1	240	pcie_cpts_comp 0	0
J721E_DEV_PCIE1	240	pcie_cpts_genf0 0	1
J721E_DEV_PCIE1	240	pcie_cpts_hw1_push 0	2
J721E_DEV_PCIE1	240	pcie_cpts_pend 0	3
J721E_DEV_PCIE1	240	pcie_cpts_sync 0	4
J721E_DEV_PCIE1	240	pcie_downstream_pulse 0	5
J721E_DEV_PCIE1	240	pcie_error_pulse 0	6
J721E_DEV_PCIE1	240	pcie_flr_pulse 0	7
J721E_DEV_PCIE1	240	pcie_hot_reset_pulse 0	8
J721E_DEV_PCIE1	240	pcie_legacy_pulse 0	9
J721E_DEV_PCIE1	240	pcie_link_state_pulse 0	10
J721E_DEV_PCIE1	240	pcie_local_level 0	11
J721E_DEV_PCIE1	240	pcie_phy_level 0	12
J721E_DEV_PCIE1	240	pcie_ptm_valid_pulse 0	13
J721E_DEV_PCIE1	240	pcie_pwr_state_pulse 0	14
J721E_DEV_PCIE2	241	pcie_cpts_comp 0	0
J721E_DEV_PCIE2	241	pcie_cpts_genf0 0	1
J721E_DEV_PCIE2	241	pcie_cpts_hw1_push 0	2
J721E_DEV_PCIE2	241	pcie_cpts_pend 0	3
J721E_DEV_PCIE2	241	pcie_cpts_sync 0	4
J721E_DEV_PCIE2	241	pcie_downstream_pulse 0	5
J721E_DEV_PCIE2	241	pcie_error_pulse 0	6
J721E_DEV_PCIE2	241	pcie_flr_pulse 0	7
J721E_DEV_PCIE2	241	pcie_hot_reset_pulse 0	8
J721E_DEV_PCIE2	241	pcie_legacy_pulse 0	9
J721E_DEV_PCIE2	241	pcie_link_state_pulse 0	10
J721E_DEV_PCIE2	241	pcie_local_level 0	11
J721E_DEV_PCIE2	241	pcie_phy_level 0	12
J721E_DEV_PCIE2	241	pcie_ptm_valid_pulse 0	13
J721E_DEV_PCIE2	241	pcie_pwr_state_pulse 0	14
J721E_DEV_PCIE3	242	pcie_cpts_comp 0	0
J721E_DEV_PCIE3	242	pcie_cpts_genf0 0	1
J721E_DEV_PCIE3	242	pcie_cpts_hw1_push 0	2
J721E_DEV_PCIE3	242	pcie_cpts_pend 0	3
J721E_DEV_PCIE3	242	pcie_cpts_sync 0	4
J721E_DEV_PCIE3	242	pcie_downstream_pulse 0	5
J721E_DEV_PCIE3	242	pcie_error_pulse 0	6
J721E_DEV_PCIE3	242	pcie_flr_pulse 0	7
J721E_DEV_PCIE3	242	pcie_hot_reset_pulse 0	8
J721E_DEV_PCIE3	242	pcie_legacy_pulse 0	9
J721E_DEV_PCIE3	242	pcie_link_state_pulse 0	10
J721E_DEV_PCIE3	242	pcie_local_level 0	11
J721E_DEV_PCIE3	242	pcie_phy_level 0	12
J721E_DEV_PCIE3	242	pcie_ptm_valid_pulse 0	13
J721E_DEV_PCIE3	242	pcie_pwr_state_pulse 0	14
J721E_DEV_PRU_ICSSG0	119	pr1_edc0_sync0_out 0	0
J721E_DEV_PRU_ICSSG0	119	pr1_edc0_sync1_out 0	1
J721E_DEV_PRU_ICSSG0	119	pr1_edc1_sync0_out 0	2
J721E_DEV_PRU_ICSSG0	119	pr1_edc1_sync1_out 0	3
J721E_DEV_PRU_ICSSG0	119	pr1_host_intr_pend 0 to 7	4 to 11
J721E_DEV_PRU_ICSSG0	119	pr1_host_intr_req 0 to 7	12 to 19
J721E_DEV_PRU_ICSSG0	119	pr1_iep0_cmp_intr_req 0 to 15	20 to 35
J721E_DEV_PRU_ICSSG0	119	pr1_iep1_cmp_intr_req 0 to 15	36 to 51
J721E_DEV_PRU_ICSSG0	119	pr1_rx_sof_intr_req 0 to 1	52 to 53
J721E_DEV_PRU_ICSSG0	119	pr1_tx_sof_intr_req 0 to 1	54 to 55
J721E_DEV_PRU_ICSSG1	120	pr1_edc0_sync0_out 0	0
J721E_DEV_PRU_ICSSG1	120	pr1_edc0_sync1_out 0	1
J721E_DEV_PRU_ICSSG1	120	pr1_edc1_sync0_out 0	2
J721E_DEV_PRU_ICSSG1	120	pr1_edc1_sync1_out 0	3
J721E_DEV_PRU_ICSSG1	120	pr1_host_intr_pend 0 to 7	4 to 11
J721E_DEV_PRU_ICSSG1	120	pr1_host_intr_req 0 to 7	12 to 19
J721E_DEV_PRU_ICSSG1	120	pr1_iep0_cmp_intr_req 0 to 15	20 to 35
J721E_DEV_PRU_ICSSG1	120	pr1_iep1_cmp_intr_req 0 to 15	36 to 51
J721E_DEV_PRU_ICSSG1	120	pr1_rx_sof_intr_req 0 to 1	52 to 53
J721E_DEV_PRU_ICSSG1	120	pr1_tx_sof_intr_req 0 to 1	54 to 55
J721E_DEV_RTI24	254	intr_wwd 0	0
J721E_DEV_RTI25	255	intr_wwd 0	0
J721E_DEV_SA2_UL0	264	sa_ul_pka 0	0
J721E_DEV_SA2_UL0	264	sa_ul_trng 0	1
J721E_DEV_TIMER0	49	intr_pend 0	0
J721E_DEV_TIMER1	50	intr_pend 0	0
J721E_DEV_TIMER10	60	intr_pend 0	0
J721E_DEV_TIMER11	62	intr_pend 0	0
J721E_DEV_TIMER12	63	intr_pend 0	0
J721E_DEV_TIMER13	64	intr_pend 0	0
J721E_DEV_TIMER14	65	intr_pend 0	0
J721E_DEV_TIMER14	65	timer_pwm 0	1
J721E_DEV_TIMER15	66	intr_pend 0	0
J721E_DEV_TIMER15	66	timer_pwm 0	1
J721E_DEV_TIMER16	67	intr_pend 0	0
J721E_DEV_TIMER16	67	timer_pwm 0	1
J721E_DEV_TIMER17	68	intr_pend 0	0
J721E_DEV_TIMER17	68	timer_pwm 0	1
J721E_DEV_TIMER18	69	intr_pend 0	0
J721E_DEV_TIMER18	69	timer_pwm 0	1
J721E_DEV_TIMER19	70	intr_pend 0	0
J721E_DEV_TIMER19	70	timer_pwm 0	1
J721E_DEV_TIMER2	51	intr_pend 0	0
J721E_DEV_TIMER3	52	intr_pend 0	0
J721E_DEV_TIMER4	53	intr_pend 0	0
J721E_DEV_TIMER5	54	intr_pend 0	0
J721E_DEV_TIMER6	55	intr_pend 0	0
J721E_DEV_TIMER7	57	intr_pend 0	0
J721E_DEV_TIMER8	58	intr_pend 0	0
J721E_DEV_TIMER9	59	intr_pend 0	0
J721E_DEV_UART0	146	usart_irq 0	0
J721E_DEV_UART1	278	usart_irq 0	0
J721E_DEV_UART2	279	usart_irq 0	0
J721E_DEV_UART3	280	usart_irq 0	0
J721E_DEV_UART4	281	usart_irq 0	0
J721E_DEV_UART5	282	usart_irq 0	0
J721E_DEV_UART6	283	usart_irq 0	0
J721E_DEV_UART7	284	usart_irq 0	0
J721E_DEV_UART8	285	usart_irq 0	0
J721E_DEV_UART9	286	usart_irq 0	0
J721E_DEV_UFS0	277	ufs_intr 0	0
J721E_DEV_USB0	288	host_system_error 0	0
J721E_DEV_USB0	288	irq 0 to 7	1 to 8
J721E_DEV_USB0	288	otgirq 0	9
J721E_DEV_USB1	289	host_system_error 0	0
J721E_DEV_USB1	289	irq 0 to 7	1 to 8
J721E_DEV_USB1	289	otgirq 0	9
J721E_DEV_VPFE0	291	ccdc_intr_pend 0	0
J721E_DEV_VPFE0	291	rat_exp_intr 0	1
J721E_DEV_WKUP_ESM0	99	esm_int_cfg_lvl 0	0
J721E_DEV_WKUP_ESM0	99	esm_int_hi_lvl 0	1
J721E_DEV_WKUP_ESM0	99	esm_int_low_lvl 0	2
J721E_DEV_WKUP_GPIO0	113	gpio_bank 0 to 5	0 to 5
J721E_DEV_WKUP_GPIO1	114	gpio_bank 0 to 5	0 to 5
J721E_DEV_WKUP_I2C0	197	pointrpend 0	0
J721E_DEV_WKUP_UART0	287	usart_irq 0	0
J721E_DEV_WKUP_VTM0	154	therm_lvl_gt_th1_intr 0	0
J721E_DEV_WKUP_VTM0	154	therm_lvl_gt_th2_intr 0	1