4.17. UDMA¶
4.17.1. Introduction¶
UDMA is the DMA engine used to do direct memory access (DMA) between different peripherals like McASP, SPI, UART and memory (DDR, L2, L3, MSMC) without CPU intervention in next generation TI SoCs like J721E. The DMA architecture specifies the data structures used by standard communications modules to facilitate direct memory access (DMA) and to provide a consistent application programming interface (API) to the host software in multi-core devices. The data structures and the API used to manipulate them will be jointly referred to as Navigator Subsystem (NAVSS).
For more information on NAVSS DMA architecture, refer to J721E Technical Reference Manual
The UDMA driver provides API to program the DMA portion of the Navigator Subsystem (NAVSS) to setup and initiate transfers. Below are the high level features supported by the driver |
- Both Main and MCU NAVSS instances
- Supports all DMA operations from these instances from all the cores in the SOC
- UDMAP block copy using native NAVSS channels
- DRU block copy using direct TR submission to DRU register
- DRU block copy using indirect (PSIL) TR submission to UDMA external channels
- PDMA module to initiate transfers to/from PDMA peripherals like UART, McASP, McSPI, ADC, MCAN
- DMA transfer to/from from native PSIL peripherals like EMAC, CPSW, SA2UL
- Event and interrupt management like DMA completion, channel chaining, interrupt sharing using IA
- Resources management across instances and cores for UDMAP DMA channels,RX flow, External UTC channel (DRU), interrupt aggregators (IA), interrupt routers (IR),global events, ring accelerators (RA)
- Interaction with DMSC RM module via SCICLIENT for all non-RealTime (NRT) configuration
- Supports both RTOS and baremetal
Notes
- UDMA driver doesn’t manage/allocate the descriptor and RA memory.The caller need to allocate and provide the required memory.
- UDMA driver doesn’t use any global variables. All the required object memory like channel, driver instance, event etc should be allocated by the caller
This document has detailed API description that user can use to make use of the UDMA driver.
4.17.2. User Interface¶
For details about individual fields of this library structure, see the PDK doxygen documentation
4.17.2.1. APIs¶
The UDMA driver API can be broadly divided into the following categories
- UDMAP native channel API
- DRU (External UTC) channel API
- PDMA channel operations
- Event and interrupt API
- Ring API
In addition to above drivers the UDMA package also includes many sample examples which show how to use the drivers in different ways. Many of these sample examples use a common set of APIs which a user may find useful to refer to for use in their final application.
API reference for application:
#include <ti/drv/udma/udma.h>
4.17.3. Application¶
4.17.3.1. Examples¶
| Example | Application Name | Description | Expected Results |
|---|---|---|---|
| UDMA ADC RX | udma_adc_testapp | This performs PDMA RX data capture from ADC. ADC is configured in single shot mode and captures APP_ADC_NUM_CH channel of ADC data. The FIFO is configured to generate a DMA trigger after all channel data is captured | The application checks the ADC channel ID and prints pass on successful completion |
| UDMA Chaining | udma_chaining_testapp | UDMA chaining sample application performing a chain of block copy using channel global trigger: CH0 -> CH1 -> ... -> CHx. The first channel doesn’t use a global trigger and each channel triggers the next channel’s global trigger through the channel’s TR event register. A channel’s source buffer is previous channel destination buffer. This ensures that chaining trigger worked in a synchronized manner when the memory compare matches | The application checks the destination buffer with source buffer and prints pass on successful completion |
| UDMA CRC | udma_crc_testapp | This performs UDMA CRC operation | The application checks the calculated CRC value with pre-calculated CRC value and prints pass on successful completion |
| UDMA Direct TR DRU | udma_dru_direct_tr_testapp | UDMA DRU memcpy sample application performing block copy using direct TR submission via DRU registers | The application checks the destination buffer with source buffer and prints pass on successful completion |
| UDMA In-Direct TR DRU | udma_dru_testapp | UDMA DRU memory copy sample application performing block copy using Type 15 Transfer Record (TR15) using Transfer Record Packet Descriptor (TRPD) for developers. | The application checks the destination buffer with source buffer and prints pass on successful completion |
| UDMA Blockcopy | udma_memcpy_testapp | UDMA memory copy sample application performing block copy using Type 15 Transfer Record (TR15) using Transfer Record Packet Descriptor (TRPD) | The application checks the destination buffer with source buffer and prints pass on successful completion |
| UDMA SW Trigger | udma_sw_trigger_testapp | UDMA SW trigger sample application performs 3D transfer using SW trigger method. (i) SW trigger CH 0 -> Triggers DDR to IRAM (ii) Wait for CH 0 icnt0 x icnt1 to complete (iii) SW trigger Channel 1 -> Triggers IRAM to DDR (iv) Wait for CH 1 icnt0 x icnt1 to complete. Loop (i)-(iv) N times (icnt2) Each loop transfers M (icnt0 x icnt1) bytes of data. DDR size is M x N and IRAM size is just M bytes. IRAM memory set to wrap around after M bytes of transfer | The application checks the destination buffer with source buffer and prints pass on successful completion |
| UDMA OSPI Flash | udma_baremetal_ospi_flash_testapp | UDMA OSPI Flash sample application performs DAC DMA mode ospi write and read at 133MHz RCLK and 166MHz RCLK with UDMA 3D transfer using SW trigger method. Here OSPI read illustrates TR Reload Feature in which TR Reload count is set as 0x1FFU for perpetual loop. | The application checks the destination buffer with source buffer and prints pass on successful completion |