metaonly interface ti.catalog.msp430.peripherals.timer.ITimer_B
index URL

MSP430 ITimer_B interface

XDCspec summary sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
metaonly interface ITimer_B {  ...
// inherits ti.catalog.msp430.peripherals.timer.ITimer
    // inherits xdc.platform.IPeripheral
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
package ti.catalog.msp430.peripherals.timer;
 
metaonly interface ITimer_B inherits ITimer {
module-wide constants & types
    enum CAP_t//  {
        CAP_OFF,
        CAP
    };
 
    enum CCIE_t//  {
        CCIE_OFF,
        CCIE
    };
 
    enum CCIFG_t//  {
        CCIFG_OFF,
        CCIFG
    };
 
    enum CCIS_t//  {
        CCIS_0// CCIxA,
        CCIS_1// CCIxB,
        CCIS_2// GND,
        CCIS_3// Vcc
    };
 
    enum CCI_t//  {
        CCI_OFF,
        CCI
    };
 
    enum CLLD_t//  {
        CLLD_0,
        CLLD_1,
        CLLD_2,
        CLLD_3
    };
 
    enum CM_t//  {
        CM_0// No Capture,
        CM_1// Rising Edge,
        CM_2// Falling Edge,
        CM_3// Both Edges
    };
 
    enum CNTL_t//  {
        CNTL_0// 16-bit, TBR(max) = 0FFFFh,
        CNTL_1// 12-bit, TBR(max) = 0FFFh,
        CNTL_2// 10-bit, TBR(max) = 03FFh,
        CNTL_3// 8-bit, TBR(max) = 0FFh
    };
 
    enum COV_t//  {
        COV_OFF,
        COV
    };
 
    enum ID_t//  {
        ID_0// Divider - /1,
        ID_1// Divider - /2,
        ID_2// Divider - /4,
        ID_3// Divider - /8
    };
 
    enum MC_t//  {
        MC_0// Stop Mode,
        MC_1// Up Mode,
        MC_2// Continuous Mode,
        MC_3// Up/Down Mode
    };
 
    enum OUTMOD_t//  {
        OUTMOD_0// PWM output mode: 0 - OUT bit value,
        OUTMOD_1// PWM output mode: 1 - Set,
        OUTMOD_2// PWM output mode: 2 - PWM toggle/reset,
        OUTMOD_3// PWM output mode: 3 - PWM set/reset,
        OUTMOD_4// PWM output mode: 4 - Toggle,
        OUTMOD_5// PWM output mode: 5 - Reset,
        OUTMOD_6// PWM output mode: 6 - PWM toggle/set,
        OUTMOD_7// PWM output mode: 7 - PWM reset/set
    };
 
    enum OUT_t//  {
        OUT_OFF,
        OUT
    };
 
    enum SCCI_t//  {
        SCCI_OFF,
        SCCI
    };
 
    enum SCS_t//  {
        SCS_OFF,
        SCS
    };
 
    enum TBCLGRP_t//  {
        TBCLGRP_0,
        TBCLGRP_1,
        TBCLGRP_2,
        TBCLGRP_3
    };
 
    enum TBCLR_t//  {
        TBCLR_OFF,
        TBCLR
    };
 
    enum TBIE_t//  {
        TBIE_OFF,
        TBIE
    };
 
    enum TBIFG_t//  {
        TBIFG_OFF,
        TBIFG
    };
 
    enum TBSSEL_t//  {
        TBSSEL_0// TBCLK,
        TBSSEL_1// ACLK,
        TBSSEL_2// SMCLK,
        TBSSEL_3// INCLK
    };
 
    typedef IPeripheral.Instance IPeripheralArray// [];
    typedef String StringArray// [];
 
    metaonly struct ForceSetDefaultRegister_t// Force Set Default Register {
        String register;
        Bool regForceSet;
    };
 
    metaonly struct TBCCTLx_t//  {
        ITimer_B.CM_t CM// Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges;
        ITimer_B.CCIS_t CCIS// Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC;
        ITimer_B.SCS_t SCS// Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture;
        ITimer_B.CLLD_t CLLD// Compare latch load. These bits select the compare latch load event. 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 (up or continuous mode) TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode) 11 TBCLx loads when TBR counts to TBCLx;
        ITimer_B.CAP_t CAP// Capture mode 0 Compare mode 1 Capture mode;
        ITimer_B.OUTMOD_t OUTMOD// Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set;
        ITimer_B.CCIE_t CCIE// Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled;
        ITimer_B.CCI_t CCI// Capture/compare input. The selected input signal can be read by this bit;
        ITimer_B.OUT_t OUT// Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high;
        ITimer_B.COV_t COV// Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred;
        ITimer_B.CCIFG_t CCIFG// Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending;
    };
 
    metaonly struct TBCTL_t// Timer_B Control Register {
        ITimer_B.TBCLGRP_t TBCLGRP// TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update) TBCL0 independent 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update);
        ITimer_B.CNTL_t CNTL// Counter Length 00 16-bit, TBR(max) = 0FFFFh 01 12-bit, TBR(max) = 0FFFh 10 10-bit, TBR(max) = 03FFh 11 8-bit, TBR(max) = 0FFh;
        ITimer_B.TBSSEL_t TBSSEL// Timer_B clock source select. 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK;
        ITimer_B.ID_t ID// Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8;
        ITimer_B.MC_t MC// Mode control. Setting MCx = 00h when Timer_B is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TBCL0 10 Continuous mode: the timer counts up to the value set by CNTLx 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h;
        ITimer_B.TBCLR_t TBCLR// Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero;
        ITimer_B.TBIE_t TBIE// Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled;
        ITimer_B.TBIFG_t TBIFG// Timer_B interrupt flag. 0 No interrupt pending 1 Interrupt pending;
    };
 
    metaonly struct regIntVect_t// Interrupt vector description {
        String registerName;
        String registerDescription;
        String isrToggleString;
        String priorityName;
        Bool interruptEnable;
        Bool interruptHandler;
        Int priority;
    };
module-wide functions
    IPeripheral.IPeripheralArray getAll// Find all peripherals of a certain type();
    IPeripheral.StringArray getRegisters// Find all registers defined by the peripheral();
 
 
instance:
per-instance config parameters
    config Float INCLK// Timer_B INCLK = 0;
    config Float TBCLK// Timer_B TBCLK = 0;
    config UInt baseAddr// Address of the peripheral's control register;
    config UInt intNum// Interrupt source number;
    config Bool isInternal// Boolean that is true if a Timer is internal, meaning it has no external inputs or outputs = false;
    config String name// Specific peripheral name given by the device;
    config UChar numberOfTimers// Stores the number of available timer capture compare blocks;
    config String owner// String specifying the entity that manages the peripheral;
per-instance creation
    create// Create an instance-object(IClock.Instance clock);
per-instance functions
    Bits16 getTxxCCRx// Returns TxxCCRx register value based on which CCR register(UChar ccrNumber);
    Void setTxxCCRx// Sets TxxCCRx register value based on which CCR register(UChar ccrNumber, Bits16 value);
}
 
enum ITimer_B.CAP_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CAP_t {
    CAP_OFF,
    CAP
};
 
 
enum ITimer_B.CCIE_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CCIE_t {
    CCIE_OFF,
    CCIE
};
 
 
enum ITimer_B.CCIFG_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CCIFG_t {
    CCIFG_OFF,
    CCIFG
};
 
 
enum ITimer_B.CCIS_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CCIS_t {
    CCIS_0,
    // CCIxA
    CCIS_1,
    // CCIxB
    CCIS_2,
    // GND
    CCIS_3
    // Vcc
};
 
 
enum ITimer_B.CCI_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CCI_t {
    CCI_OFF,
    CCI
};
 
 
enum ITimer_B.CLLD_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CLLD_t {
    CLLD_0,
    CLLD_1,
    CLLD_2,
    CLLD_3
};
 
 
enum ITimer_B.CM_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CM_t {
    CM_0,
    // No Capture
    CM_1,
    // Rising Edge
    CM_2,
    // Falling Edge
    CM_3
    // Both Edges
};
 
 
enum ITimer_B.CNTL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum CNTL_t {
    CNTL_0,
    // 16-bit, TBR(max) = 0FFFFh
    CNTL_1,
    // 12-bit, TBR(max) = 0FFFh
    CNTL_2,
    // 10-bit, TBR(max) = 03FFh
    CNTL_3
    // 8-bit, TBR(max) = 0FFh
};
 
 
enum ITimer_B.COV_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum COV_t {
    COV_OFF,
    COV
};
 
 
enum ITimer_B.ID_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum ID_t {
    ID_0,
    // Divider - /1
    ID_1,
    // Divider - /2
    ID_2,
    // Divider - /4
    ID_3
    // Divider - /8
};
 
 
enum ITimer_B.MC_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum MC_t {
    MC_0,
    // Stop Mode
    MC_1,
    // Up Mode
    MC_2,
    // Continuous Mode
    MC_3
    // Up/Down Mode
};
 
 
enum ITimer_B.OUTMOD_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum OUTMOD_t {
    OUTMOD_0,
    // PWM output mode: 0 - OUT bit value
    OUTMOD_1,
    // PWM output mode: 1 - Set
    OUTMOD_2,
    // PWM output mode: 2 - PWM toggle/reset
    OUTMOD_3,
    // PWM output mode: 3 - PWM set/reset
    OUTMOD_4,
    // PWM output mode: 4 - Toggle
    OUTMOD_5,
    // PWM output mode: 5 - Reset
    OUTMOD_6,
    // PWM output mode: 6 - PWM toggle/set
    OUTMOD_7
    // PWM output mode: 7 - PWM reset/set
};
 
 
enum ITimer_B.OUT_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum OUT_t {
    OUT_OFF,
    OUT
};
 
 
enum ITimer_B.SCCI_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum SCCI_t {
    SCCI_OFF,
    SCCI
};
 
 
enum ITimer_B.SCS_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum SCS_t {
    SCS_OFF,
    SCS
};
 
 
enum ITimer_B.TBCLGRP_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum TBCLGRP_t {
    TBCLGRP_0,
    TBCLGRP_1,
    TBCLGRP_2,
    TBCLGRP_3
};
 
 
enum ITimer_B.TBCLR_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum TBCLR_t {
    TBCLR_OFF,
    TBCLR
};
 
 
enum ITimer_B.TBIE_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum TBIE_t {
    TBIE_OFF,
    TBIE
};
 
 
enum ITimer_B.TBIFG_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum TBIFG_t {
    TBIFG_OFF,
    TBIFG
};
 
 
enum ITimer_B.TBSSEL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
enum TBSSEL_t {
    TBSSEL_0,
    // TBCLK
    TBSSEL_1,
    // ACLK
    TBSSEL_2,
    // SMCLK
    TBSSEL_3
    // INCLK
};
 
 
typedef ITimer_B.IPeripheralArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
typedef IPeripheral.Instance IPeripheralArray[];
 
 
typedef ITimer_B.StringArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
typedef String StringArray[];
 
 
struct ITimer_B.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
metaonly struct ForceSetDefaultRegister_t {
    String register;
    Bool regForceSet;
};
 
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
 
struct ITimer_B.TBCCTLx_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
metaonly struct TBCCTLx_t {
    ITimer_B.CM_t CM;
    // Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges
    ITimer_B.CCIS_t CCIS;
    // Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC
    ITimer_B.SCS_t SCS;
    // Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture
    ITimer_B.CLLD_t CLLD;
    // Compare latch load. These bits select the compare latch load event. 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 (up or continuous mode) TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode) 11 TBCLx loads when TBR counts to TBCLx
    ITimer_B.CAP_t CAP;
    // Capture mode 0 Compare mode 1 Capture mode
    ITimer_B.OUTMOD_t OUTMOD;
    // Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set
    ITimer_B.CCIE_t CCIE;
    // Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled
    ITimer_B.CCI_t CCI;
    // Capture/compare input. The selected input signal can be read by this bit
    ITimer_B.OUT_t OUT;
    // Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high
    ITimer_B.COV_t COV;
    // Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred
    ITimer_B.CCIFG_t CCIFG;
    // Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending
};
 
 
struct ITimer_B.TBCTL_t
index URL

Timer_B Control Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
metaonly struct TBCTL_t {
    ITimer_B.TBCLGRP_t TBCLGRP;
    // TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update) TBCL0 independent 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update)
    ITimer_B.CNTL_t CNTL;
    // Counter Length 00 16-bit, TBR(max) = 0FFFFh 01 12-bit, TBR(max) = 0FFFh 10 10-bit, TBR(max) = 03FFh 11 8-bit, TBR(max) = 0FFh
    ITimer_B.TBSSEL_t TBSSEL;
    // Timer_B clock source select. 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK
    ITimer_B.ID_t ID;
    // Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8
    ITimer_B.MC_t MC;
    // Mode control. Setting MCx = 00h when Timer_B is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TBCL0 10 Continuous mode: the timer counts up to the value set by CNTLx 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h
    ITimer_B.TBCLR_t TBCLR;
    // Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero
    ITimer_B.TBIE_t TBIE;
    // Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled
    ITimer_B.TBIFG_t TBIFG;
    // Timer_B interrupt flag. 0 No interrupt pending 1 Interrupt pending
};
 
SEE
TBCTL_t
 
struct ITimer_B.regIntVect_t
index URL

Interrupt vector description

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
metaonly struct regIntVect_t {
    String registerName;
    String registerDescription;
    String isrToggleString;
    String priorityName;
    Bool interruptEnable;
    Bool interruptHandler;
    Int priority;
};
 
DETAILS
Type to describe a single interrupt vector pin and all its possible configurations.
SEE
regIntVect_t
 
ITimer_B.getAll()  // module-wide
index URL

Find all peripherals of a certain type

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
IPeripheral.IPeripheralArray getAll();
 
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
 
ITimer_B.getRegisters()  // module-wide
index URL

Find all registers defined by the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
IPeripheral.StringArray getRegisters();
 
RETURNS
Returns an array of register names
 
config ITimer_B.INCLK  // instance
index URL

Timer_B INCLK

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config Float INCLK = 0;
 
 
config ITimer_B.TBCLK  // instance
index URL

Timer_B TBCLK

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config Float TBCLK = 0;
 
 
config ITimer_B.baseAddr  // instance
index URL

Address of the peripheral's control register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config UInt baseAddr;
 
DETAILS
A peripheral's registers are commonly accessed through a structure that defines the offsets of a particular register from the lowest address mapped to a peripheral. That lowest address is specified by this parameter.
 
config ITimer_B.intNum  // instance
index URL

Interrupt source number

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config UInt intNum;
 
 
config ITimer_B.isInternal  // instance
index URL

Boolean that is true if a Timer is internal, meaning it has no external inputs or outputs

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config Bool isInternal = false;
 
 
config ITimer_B.name  // instance
index URL

Specific peripheral name given by the device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config String name;
 
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
 
config ITimer_B.numberOfTimers  // instance
index URL

Stores the number of available timer capture compare blocks

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config UChar numberOfTimers;
 
 
config ITimer_B.owner  // instance
index URL

String specifying the entity that manages the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
config String owner;
 
Instance Creation
index URL

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
create(IClock.Instance clock);
// Create an instance-object
 
ITimer_B.getTxxCCRx()  // instance
index URL

Returns TxxCCRx register value based on which CCR register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
Bits16 getTxxCCRx(UChar ccrNumber);
 
SEE
getTxxCCRx
 
ITimer_B.setTxxCCRx()  // instance
index URL

Sets TxxCCRx register value based on which CCR register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/timer/ITimer_B.xdc
Void setTxxCCRx(UChar ccrNumber, Bits16 value);
 
SEE
setTxxCCRx
generated on Thu, 27 Sep 2012 23:24:47 GMT