// CCIxA

    // CCIxB

    // GND

    // Vcc

    // No Capture

    // Rising Edge

    // Falling Edge

    // Both Edges

    // 16-bit, TBR(max) = 0FFFFh

    // 12-bit, TBR(max) = 0FFFh

    // 10-bit, TBR(max) = 03FFh

    // 8-bit, TBR(max) = 0FFh

    // Divider - /1

    // Divider - /2

    // Divider - /4

    // Divider - /8

    // Stop Mode

    // Up Mode

    // Continuous Mode

    // Up/Down Mode

    // PWM output mode: 0 - OUT bit value

    // PWM output mode: 1 - Set

    // PWM output mode: 2 - PWM toggle/reset

    // PWM output mode: 3 - PWM set/reset

    // PWM output mode: 4 - Toggle

    // PWM output mode: 5 - Reset

    // PWM output mode: 6 - PWM toggle/set

    // PWM output mode: 7 - PWM reset/set

    // TBCLK

    // ACLK

    // SMCLK

    // INCLK

    // Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges

    // Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC

    // Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture

    // Compare latch load. These bits select the compare latch load event. 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 (up or continuous mode) TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode) 11 TBCLx loads when TBR counts to TBCLx

    // Capture mode 0 Compare mode 1 Capture mode

    // Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set

    // Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled

    // Capture/compare input. The selected input signal can be read by this bit

    // Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high

    // Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred

    // Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending

    // TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update) TBCL0 independent 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update)

    // Counter Length 00 16-bit, TBR(max) = 0FFFFh 01 12-bit, TBR(max) = 0FFFh 10 10-bit, TBR(max) = 03FFh 11 8-bit, TBR(max) = 0FFh

    // Timer_B clock source select. 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK

    // Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8

    // Mode control. Setting MCx = 00h when Timer_B is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TBCL0 10 Continuous mode: the timer counts up to the value set by CNTLx 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h

    // Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero

    // Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled

    // Timer_B interrupt flag. 0 No interrupt pending 1 Interrupt pending

// Create an instance-object