1 import ti.catalog.msp430.peripherals.clock.IClock;
2
3 /*!
4 * ======== ITimer_B ========
5 * MSP430 ITimer_B interface
6 */
7 metaonly interface ITimer_B inherits xdc.platform.IPeripheral {
8
9 enum TBCLGRP_t {
10 TBCLGRP_0 = (0*0x100u),
11 TBCLGRP_1 = (1*0x100u),
12 TBCLGRP_2 = (2*0x100u),
13 TBCLGRP_3 = 3*0x100u
14 };
15
16 enum CNTL_t {
17 CNTL_0 = (0*0x100u), /*! 16-bit, TBR(max) = 0FFFFh */
18 CNTL_1 = (1*0x100u), /*! 12-bit, TBR(max) = 0FFFh */
19 CNTL_2 = (2*0x100u), /*! 10-bit, TBR(max) = 03FFh */
20 CNTL_3 = 3*0x100u /*! 8-bit, TBR(max) = 0FFh */
21 };
22
23 enum TBSSEL_t {
24 TBSSEL_0 = (0*0x100u), /*! TBCLK */
25 TBSSEL_1 = (1*0x100u), /*! ACLK */
26 TBSSEL_2 = (2*0x100u), /*! SMCLK */
27 TBSSEL_3 = 3*0x100u /*! INCLK */
28 };
29
30 enum TBCLR_t {
31 TBCLR_OFF = (0x0000),
32 TBCLR = 0x0004
33 };
34
35 enum TBIE_t {
36 TBIE_OFF = (0x0000),
37 TBIE = 0x0002
38 };
39
40 enum TBIFG_t {
41 TBIFG_OFF = (0x000),
42 TBIFG = (0x0001)
43 };
44
45 enum MC_t {
46 MC_0 = (0*0x10u), /*! Stop Mode */
47 MC_1 = (1*0x10u), /*! Up Mode */
48 MC_2 = (2*0x10u), /*! Continuous Mode */
49 MC_3 = 3*0x10u /*! Up/Down Mode */
50 };
51
52 enum ID_t {
53 ID_0 = (0*0x40u), /*! Divider - /1 */
54 ID_1 = (1*0x40u), /*! Divider - /2 */
55 ID_2 = (2*0x40u), /*! Divider - /4 */
56 ID_3 = 3*0x40u /*! Divider - /8 */
57 };
58
59 enum CM_t {
60 CM_0 = (0*0x4000u), /*! No Capture */
61 CM_1 = (1*0x4000u), /*! Rising Edge */
62 CM_2 = (2*0x4000u), /*! Falling Edge */
63 CM_3 = 3*0x4000u /*! Both Edges */
64 };
65
66 enum CCIS_t {
67 CCIS_0 = (0*0x1000u), /*! CCIxA */
68 CCIS_1 = (1*0x1000u), /*! CCIxB */
69 CCIS_2 = (2*0x1000u), /*! GND */
70 CCIS_3 = 3*0x1000u /*! Vcc */
71 };
72
73 enum SCS_t {
74 SCS_OFF = (0x0000),
75 SCS = 0x0800
76 };
77
78 enum CLLD_t {
79 CLLD_0 = (0*0x1000u),
80 CLLD_1 = (1*0x1000u),
81 CLLD_2 = (2*0x1000u),
82 CLLD_3 = 3*0x1000u
83 };
84
85 enum SCCI_t {
86 SCCI_OFF = (0x0000),
87 SCCI = 0x0400
88 };
89
90 enum CAP_t {
91 CAP_OFF = (0x0000),
92 CAP = 0x0100
93 };
94
95 enum CCIE_t {
96 CCIE_OFF = (0x0000),
97 CCIE = (0x0010)
98 };
99
100 enum CCI_t {
101 CCI_OFF = (0x0008),
102 CCI = (0x0008)
103 };
104
105 enum OUT_t {
106 OUT_OFF = (0x0000),
107 OUT = (0x0004)
108 };
109
110 enum COV_t {
111 COV_OFF = (0x0000),
112 COV = (0x0002)
113 };
114
115 enum CCIFG_t {
116 CCIFG_OFF = (0x0000),
117 CCIFG = (0x0001)
118 };
119
120 enum OUTMOD_t {
121 OUTMOD_0 = (0*0x20u), /*! PWM output mode: 0 - OUT bit value */
122 OUTMOD_1 = (1*0x20u), /*! PWM output mode: 1 - Set */
123 OUTMOD_2 = (2*0x20u), /*! PWM output mode: 2 - PWM toggle/reset */
124 OUTMOD_3 = (3*0x20u), /*! PWM output mode: 3 - PWM set/reset */
125 OUTMOD_4 = (4*0x20u), /*! PWM output mode: 4 - Toggle */
126 OUTMOD_5 = (5*0x20u), /*! PWM output mode: 5 - Reset */
127 OUTMOD_6 = (6*0x20u), /*! PWM output mode: 6 - PWM toggle/set */
128 OUTMOD_7 = 7*0x20u /*! PWM output mode: 7 - PWM reset/set */
129 };
130
131 /*!
132 * ======== TBCTL_t ========
133 * Timer_B Control Register
134 *
135 * @see #TBCTL_t
136 */
137 struct TBCTL_t {
138 TBCLGRP_t TBCLGRP; /*! TBCLx group
139 * 00 Each TBCLx latch loads independently
140 * 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update)
141 * TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update)
142 * TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)
143 * TBCL0 independent
144 * 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update)
145 * TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)
146 * TBCL0 independent
147 * 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6
148 * (TBCCR1 CLLDx bits control the update) */
149 CNTL_t CNTL; /*! Counter Length
150 * 00 16-bit, TBR(max) = 0FFFFh
151 * 01 12-bit, TBR(max) = 0FFFh
152 * 10 10-bit, TBR(max) = 03FFh
153 * 11 8-bit, TBR(max) = 0FFh */
154 TBSSEL_t TBSSEL; /*! Timer_B clock source select.
155 * 00 TBCLK
156 * 01 ACLK
157 * 10 SMCLK
158 * 11 Inverted TBCLK */
159 ID_t ID; /*! Input divider. These bits select the divider for the input clock.
160 * 00 /1
161 * 01 /2
162 * 10 /4
163 * 11 /8 */
164 MC_t MC; /*! Mode control. Setting MCx = 00h when Timer_B is not in use conserves
165 * power.
166 * 00 Stop mode: the timer is halted
167 * 01 Up mode: the timer counts up to TBCL0
168 * 10 Continuous mode: the timer counts up to the value set by CNTLx
169 * 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h */
170 TBCLR_t TBCLR; /*! Timer_B clear. Setting this bit resets TBR, the clock divider, and the count
171 * direction. The TBCLR bit is automatically reset and is always read as zero. */
172 TBIE_t TBIE; /*! Timer_B interrupt enable. This bit enables the TBIFG interrupt request.
173 * 0 Interrupt disabled
174 * 1 Interrupt enabled */
175 TBIFG_t TBIFG; /*! Timer_B interrupt flag.
176 * 0 No interrupt pending
177 * 1 Interrupt pending */
178 }
179
180
181 struct TBCCTLx_t {
182 CM_t CM; /*! Capture mode
183 * 00 No capture
184 * 01 Capture on rising edge
185 * 10 Capture on falling edge
186 * 11 Capture on both rising and falling edges */
187 CCIS_t CCIS; /*! Capture/compare input select. These bits select the TBCCRx input signal.
188 * See the device-specific data sheet for specific signal connections.
189 * 00 CCIxA
190 * 01 CCIxB
191 * 10 GND
192 * 11 VCC */
193 SCS_t SCS; /*! Synchronize capture source. This bit is used to synchronize the capture input
194 * signal with the timer clock.
195 * 0 Asynchronous capture
196 * 1 Synchronous capture */
197 CLLD_t CLLD; /*! Compare latch load. These bits select the compare latch load event.
198 * 00 TBCLx loads on write to TBCCRx
199 * 01 TBCLx loads when TBR counts to 0
200 * 10 TBCLx loads when TBR counts to 0 (up or continuous mode)
201 * TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode)
202 * 11 TBCLx loads when TBR counts to TBCLx */
203 CAP_t CAP; /*! Capture mode
204 * 0 Compare mode
205 * 1 Capture mode */
206 OUTMOD_t OUTMOD; /*! Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx
207 * = EQU0.
208 * 000 OUT bit value
209 * 001 Set
210 * 010 Toggle/reset
211 * 011 Set/reset
212 * 100 Toggle
213 * 101 Reset
214 * 110 Toggle/set
215 * 111 Reset/set */
216 CCIE_t CCIE; /*! Capture/compare interrupt enable. This bit enables the interrupt request of
217 * the corresponding CCIFG flag.
218 * 0 Interrupt disabled
219 * 1 Interrupt enabled */
220 CCI_t CCI; /*! Capture/compare input. The selected input signal can be read by this bit. */
221 OUT_t OUT; /*! Output. For output mode 0, this bit directly controls the state of the output.
222 * 0 Output low
223 * 1 Output high */
224 COV_t COV; /*! Capture overflow. This bit indicates a capture overflow occurred. COV must
225 * be reset with software.
226 * 0 No capture overflow occurred
227 * 1 Capture overflow occurred */
228 CCIFG_t CCIFG; /*! Capture/compare interrupt flag
229 * 0 No interrupt pending
230 * 1 Interrupt pending */
231 }
232
233 /*!
234 * ======== ForceSetDefaultRegister_t ========
235 * Force Set Default Register
236 *
237 * Type to store if each register needs to be forced initialized
238 * even if the register is in default state.
239 *
240 * @see #ForceSetDefaultRegister_t
241 */
242 struct ForceSetDefaultRegister_t {
243 String register;
244 Bool regForceSet;
245 }
246
247 create(IClock.Instance clock);
248
249 instance:
250 /*!
251 * ======== baseAddr ========
252 * Address of the peripheral's control register.
253 *
254 * A peripheral's registers are commonly accessed through a structure
255 * that defines the offsets of a particular register from the lowest
256 * address mapped to a peripheral. That lowest address is specified by
257 * this parameter.
258 */
259 config UInt baseAddr;
260
261 /*!
262 * ======== intNum ========
263 * Interrupt source number
264 *
265 */
266 config UInt intNum;
267
268 /*! Timer_B TBCLK */
269 config float TBCLK = 0;
270
271 /*! Timer_B INCLK */
272 config float INCLK = 0;
273
274
275 UChar getNumberOfTimers();
276
277 /*! @_nodoc */
278 config IClock.Instance clock;
279 }