2.6.2. TI Arm-Specific Pre-Defined Macro Symbols¶
2.6.2.1. TI Arm C Language Extensions (ACLE) Predefined Macro Symbols¶
The tiarmclang compiler supports ACLE pre-defined symbols that are relevant for Arm Cortex-M and Cortex-R series processors. The following table summarizes the ACLE pre-defined macros that are supported in the tiarmclang compiler.
Symbol |
Value Kind |
Value / Description |
|---|---|---|
|
<version> |
Identifies the Arm architecture version being compiled for. One of the following values:
|
|
<version> |
Identifies the version of ACLE specification that the compiler adheres to, where <version> = <major>*100 + <minor> The tiarmclang compiler adheres to version 2.00 of the ACLE specification (<version> = 200). |
|
<constant> |
Defined to 1 if the -mbig-endian option is specified on the tiarmclang command-line. By default, __ARM_BIG_ENDIAN is not defined. |
|
<constant> |
Defined to 1 to indicate Arm processor being compiled for supports ARM mode instructions (Cortex- R4/R5). |
|
<constant> |
Identifies the set of THUMB mode instructions supported by the Arm processor being compiled for. Value is:
|
|
<constant> |
Defined to 1 if the Arm architecture being compiled for is an AArch32 type. |
|
<char> |
Identifies the Arm architecture profile being compiled for:
|
|
<constant> |
Defined to 1 if Arm processor being compiled for supports unaligned memory accesses (i.e. if -munaligned-access is on). Defined to 1 by default for Cortex-M3/M4/M33/R4/ R5, but can be overridden for the processors using the -mno-unaligned-access compiler option. |
|
<bitmap> |
Identifies which access-widths are supported for LDREX/STREX instructions on the Arm processor being compiled for. <bitmap> values/width: * bit 0 - byte * bit 1 - half-word * bit 2 - word * bit 3 - double-word <bitmap> values supported: * 0x7 - Cortex-M3/M4 * 0xF - Cortex-M33/R4/R5 |
|
<constant> |
Defined to 1 if the CLZ instruction is available on the Arm processor being compiled for (including Cortex-M3/M4/M33/R4/R5). |
|
<constant> |
Defined to 1 if the Q saturation flag exists and relevant Q saturation arithmetic intrinsics are available on the Arm processor being compiled for (Cortex-M3/M4/M33/R4/ R5). |
|
<constant> |
Defined to 1 if DSP instructions are supported and relevant intrinsics are available on the Arm processor being compiled for (Cortex-M4/M33/R4/R5). |
|
<constant> |
Defined to 1 if the SSAT and USAT instructions are supported and the relevant intrinsics are available on the Arm processor being compiled for (Cortex-M3/ M4/M33/R4/R5). |
|
<constant> |
Defined to 1 if the 32-bit SIMD instructions are supported and the relevant intrinsics are available on the Arm processor being compiled for (Cortex-M4/ M33/R4/R5). |
|
<constant> |
Defined to 1 if hardware integer divide instructions are available on the Arm processor being compiled for (Cortex-M3/ M4/M33). |
|
<bitmap> |
Defined if floating-point hardware is available. The value assigned to __ARM_FP is a bitmap indicating what floating-point precisions are supported:
<bitmap> values supported: * 0x6 - Cortex-M4/M33 * 0xC - Cortex-R4/R5 |
|
<constant> |
Defined to 1 if floating- point hardware that supports fused multiply- and-accumulate operations is available on the Arm processor being compiled for (Cortex-M4/ M33). |
|
<constant> |
Defined to 1 if the directed rounding and conversion vector instructions are supported and the relevant intrinsics are available on the Arm processor being compiled for (Cortex-M33). |
|
<constant> |
Defined to 1 if the IEEE 754-2008 compliant floating-point maximum and minimum vector instructions are supported and the relevant intrinsics are available on the Arm processor being compiled for (Cortex-M33). |
|
<constant> |
Defined to 1 if the compiler conforms to the default procedure calling standard as defined in the Procedure Call Standard for the Arm Architecture (Cortex-M0/M0+/M3/M4/M33/ R4/R5). |
|
<constant> |
Defined to 1 if the compiler will pass floating-point arguments and return values in FPU registers according to the Procedure Call Standard for the Arm Architecture when floating-point hardware is available during compilation (Cortex-M4/M33/R4/R5). |
|
<bytes> |
Defined to <bytes>, where <bytes> is the minimum number of bytes used by the compiler to represent the value of a wchar_t type object. On Cortex-M0/ M0+M3/M4/M33/R4/R5, <bytes> = 4. |
|
<bytes> |
Defined to <bytes>, where <bytes> is the minimum number of bytes used by the compiler to represent the value of an enum object. Cortex-M0/M0+/M3/ M4/M33/R4/R5, <bytes> = 1. |
More details about ACLE pre-defined macro symbols can be found in the Arm C Language Extensions Documentation page.
2.6.2.2. Other Arm-Specific Predefined Macro Symbols¶
Symbol |
Value Kind |
Value / Description |
|---|---|---|
|
<constant> |
Defined to 1 if target of compile is an Arm processor. |
|
<constant> |
Defined to 1 if target of compile is an Arm processor. |
|
<constant> |
Defined to 1 if compiling for an Arm processor in Thumb mode. |
|
<constant> |
Defined to 1 if T32 (Thumb2) instructions are available when compiling for an Arm processor. |
|
<constant> |
Defined to 1 if compiling for an Arm processor based on the version 6M Arm architecture (Cortex-M0/M0+). |
|
<constant> |
Defined to 1 if compiling for an Arm processor based on the version 7M Arm architecture (Cortex-M3). |
|
<constant> |
Defined to 1 if compiling for an Arm processor based on the version 7EM Arm architecture (Cortex-M4). |
|
<constant> |
Defined to 1 if compiling for an Arm processor based on the version 8M- MAIN Arm architecture (Cortex-M33). |
|
<constant> |
Defined to 1 if compiling for an Arm processor based on the version 7R Arm architecture (Cortex-R4/R5). |
|
<constant> |
Defined to 1 if floating-point hardware use is enabled for a tiarmclang compilation. |
|
<constant> |
Defined to 1 if use of the VFPV2 floating-point hardware is enabled for a tiarmclang compilation. |
|
<constant> |
Defined to 1 if use of the VFPV3 floating-point hardware is enabled for a tiarmclang compilation. |
|
<constant> |
Defined to 1 if use of the VFPV4 floating-point hardware is enabled for a tiarmclang compilation. |
|
<constant> |
Defined to 1 if use of the FPV5 floating-point hardware is enabled for a tiarmclang compilation. |
|
<constant> |
Defined to 1 if compiler has been instructed to generate big-endian object code. |
|
<constant> |
Defined to 1 if compiler has been instructed to generate little-endian object code (default). |
|
<constant> |
Defined to 1 if compiling for a Cortex-M series Arm processor in big-endian mode. |
|
<constant> |
Defined to 1 if compiling for a Cortex-M series Arm processor in little-endian mode. |
Symbol |
Value Kind |
Value / Description |
|---|---|---|
|
<constant> |
Defined to 1 unless a different procedure calling convention is in effect for a given compilation. |
|
<constant> |
Defined to 1 if hardware integer divide instructions are available on the Arm processor being compiled for (Cortex-M3/M4/M33/R5). |
|
<constant> |
Defined to 1 if Cortex-M Security Extensions (CMSE) are supported on the Arm processor being compiled for (Cortex-M33). |
|
<constant> |
Defined to 1 if the -ffast-math or -ffp-mode=fast option is enabled (-ffast-math is implied when the deprecated -Ofast optimization level is specified on the compiler command-line). |