UART driver implementation for a MSP432E4 UART controller.
============================================================================
The UART header file should be included in an application as follows:
Refer to UART2.h for a complete description of APIs and examples of use.
|
#define | UART2MSP432E4_PIN_UNASSIGNED 0xFFFFFFFF |
| Indicates a pin is not being used. More...
|
|
#define | UART2MSP432E4_DMACH_UNASSIGNED 0xFF |
| Indicates a DMA channel is not being used. More...
|
|
#define | UART2MSP432E4_FLOWCTRL_NONE 0 |
| No hardware flow control. More...
|
|
#define | UART2MSP432E4_FLOWCTRL_HARDWARE 1 |
| Hardware flow control. More...
|
|
#define | UART2MSP432E4_PA0_U0RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 0, GPIO_PA0_U0RX) |
| PA0 is used for UART0 RX. More...
|
|
#define | UART2MSP432E4_PA1_U0TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 1, GPIO_PA1_U0TX) |
| PA1 is used for UART0 RX. More...
|
|
#define | UART2MSP432E4_PH1_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 1, GPIO_PH1_U0CTS) |
| PH1 is used for UART0 CTS. More...
|
|
#define | UART2MSP432E4_PM4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTM, 4, GPIO_PM4_U0CTS) |
| PM4 is used for UART0 CTS. More...
|
|
#define | UART2MSP432E4_PB4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 4, GPIO_PB4_U0CTS) |
| PB4 is used for UART0 CTS. More...
|
|
#define | UART2MSP432E4_PE6_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 6, GPIO_PE6_U0CTS) |
| PE6 is used for UART0 CTS. More...
|
|
#define | UART2MSP432E4_PG4_U0CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 4, GPIO_PG4_U0CTS) |
| PG4 is used for UART0 CTS. More...
|
|
#define | UART2MSP432E4_PH0_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 0, GPIO_PH0_U0RTS) |
| PH0 is used for UART0 RTS. More...
|
|
#define | UART2MSP432E4_PB5_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 5, GPIO_PB5_U0RTS) |
| PB5 is used for UART0 RTS. More...
|
|
#define | UART2MSP432E4_PE7_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 7, GPIO_PE7_U0RTS) |
| PE7 is used for UART0 RTS. More...
|
|
#define | UART2MSP432E4_PG5_U0RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 5, GPIO_PG5_U0RTS) |
| PG5 is used for UART0 RTS. More...
|
|
#define | UART2MSP432E4_PB0_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 0, GPIO_PB0_U1RX) |
| PB0 is used for UART1 RX. More...
|
|
#define | UART2MSP432E4_PQ4_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 4, GPIO_PQ4_U1RX) |
| PQ4 is used for UART1 RX. More...
|
|
#define | UART2MSP432E4_PR5_U1RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 5, GPIO_PR5_U1RX) |
| PR5 is used for UART1 RX. More...
|
|
#define | UART2MSP432E4_PB1_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 1, GPIO_PB1_U1TX) |
| PB1 is used for UART1 TX. More...
|
|
#define | UART2MSP432E4_PQ5_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 5, GPIO_PQ5_U1TX) |
| PQ5 is used for UART1 TX. More...
|
|
#define | UART2MSP432E4_PR6_U1TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 6, GPIO_PR6_U1TX) |
| PR6 is used for UART1 TX. More...
|
|
#define | UART2MSP432E4_PP3_U1CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 3, GPIO_PP3_U1CTS) |
| PP3 is used for UART1 CTS. More...
|
|
#define | UART2MSP432E4_PN1_U1CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 1, GPIO_PN1_U1CTS) |
| PN1 is used for UART1 CTS. More...
|
|
#define | UART2MSP432E4_PE0_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 0, GPIO_PE0_U1RTS) |
| PE0 is used for UART1 RTS. More...
|
|
#define | UART2MSP432E4_PN0_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 0, GPIO_PN0_U1RTS) |
| PN0 is used for UART1 RTS. More...
|
|
#define | UART2MSP432E4_PN7_U1RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 7, GPIO_PN7_U1RTS) |
| PN7 is used for UART1 RTS. More...
|
|
#define | UART2MSP432E4_PA6_U2RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 6, GPIO_PA6_U2RX) |
| PA6 is used for UART2 RX. More...
|
|
#define | UART2MSP432E4_PD4_U2RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 4, GPIO_PD4_U2RX) |
| PD4 is used for UART2 RX. More...
|
|
#define | UART2MSP432E4_PA7_U2TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 7, GPIO_PA7_U2TX) |
| PA7 is used for UART2 TX. More...
|
|
#define | UART2MSP432E4_PD5_U2TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 5, GPIO_PD5_U2TX) |
| PD5 is used for UART2 TX. More...
|
|
#define | UART2MSP432E4_PN3_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 3, GPIO_PN3_U2CTS) |
| PN3 is used for UART2 CTS. More...
|
|
#define | UART2MSP432E4_PD7_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 7, GPIO_PD7_U2CTS) |
| PD7 is used for UART2 CTS. More...
|
|
#define | UART2MSP432E4_PJ3_U2CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 3, GPIO_PJ3_U2CTS) |
| PJ3 is used for UART2 CTS. More...
|
|
#define | UART2MSP432E4_PN2_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 2, GPIO_PN2_U2RTS) |
| PN2 is used for UART2 RTS. More...
|
|
#define | UART2MSP432E4_PD6_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 6, GPIO_PD6_U2RTS) |
| PD6 is used for UART2 RTS. More...
|
|
#define | UART2MSP432E4_PJ2_U2RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 2, GPIO_PJ2_U2RTS) |
| PJ2 is used for UART2 RTS. More...
|
|
#define | UART2MSP432E4_PA4_U3RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 4, GPIO_PA4_U3RX) |
| PA4 is used for UART3 RX. More...
|
|
#define | UART2MSP432E4_PJ0_U3RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 0, GPIO_PJ0_U3RX) |
| PJ0 is used for UART3 RX. More...
|
|
#define | UART2MSP432E4_PA5_U3TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 5, GPIO_PA5_U3TX) |
| PA5 is used for UART3 TX. More...
|
|
#define | UART2MSP432E4_PJ1_U3TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 1, GPIO_PJ1_U3TX) |
| PJ1 is used for UART3 TX. More...
|
|
#define | UART2MSP432E4_PP5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 5, GPIO_PP5_U3CTS) |
| PP5 is used for UART3 CTS. More...
|
|
#define | UART2MSP432E4_PN5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 5, GPIO_PN5_U3CTS) |
| PN5 is used for UART3 CTS. More...
|
|
#define | UART2MSP432E4_PJ5_U3CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 5, GPIO_PJ5_U3CTS) |
| PJ5 is used for UART3 CTS. More...
|
|
#define | UART2MSP432E4_PP4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 4, GPIO_PP4_U3RTS) |
| PP4 is used for UART3 RTS. More...
|
|
#define | UART2MSP432E4_PN4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 4, GPIO_PN4_U3RTS) |
| PN4 is used for UART3 RTS. More...
|
|
#define | UART2MSP432E4_PJ4_U3RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 4, GPIO_PJ4_U3RTS) |
| PJ4 is used for UART3 RTS. More...
|
|
#define | UART2MSP432E4_PA2_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 2, GPIO_PA2_U4RX) |
| PA2 is used for UART4 RX. More...
|
|
#define | UART2MSP432E4_PK0_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 0, GPIO_PK0_U4RX) |
| PK0 is used for UART4 RX. More...
|
|
#define | UART2MSP432E4_PR1_U4RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 1, GPIO_PR1_U4RX) |
| PR1 is used for UART4 RX. More...
|
|
#define | UART2MSP432E4_PA3_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 3, GPIO_PA3_U4TX) |
| PA3 is used for UART4 TX. More...
|
|
#define | UART2MSP432E4_PK1_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 1, GPIO_PK1_U4TX) |
| PK1 is used for UART4 TX. More...
|
|
#define | UART2MSP432E4_PR0_U4TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTR, 0, GPIO_PR0_U4TX) |
| PR0 is used for UART4 TX. More...
|
|
#define | UART2MSP432E4_PK3_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 3, GPIO_PK3_U4CTS) |
| PK3 is used for UART4 CTS. More...
|
|
#define | UART2MSP432E4_PJ7_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 7, GPIO_PJ7_U4CTS) |
| PJ7 is used for UART4 CTS. More...
|
|
#define | UART2MSP432E4_PN7_U4CTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 7, GPIO_PN7_U4CTS) |
| PN7 is used for UART4 CTS. More...
|
|
#define | UART2MSP432E4_PK2_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTK, 2, GPIO_PK2_U4RTS) |
| PK2 is used for UART4 RTS. More...
|
|
#define | UART2MSP432E4_PJ6_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTJ, 6, GPIO_PJ6_U4RTS) |
| PJ6 is used for UART4 RTS. More...
|
|
#define | UART2MSP432E4_PN6_U4RTS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTN, 6, GPIO_PN6_U4RTS) |
| PN6 is used for UART4 RTS. More...
|
|
#define | UART2MSP432E4_PC6_U5RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 6, GPIO_PC6_U5RX) |
| PC6 is used for UART5 RX. More...
|
|
#define | UART2MSP432E4_PH6_U5RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 6, GPIO_PH6_U5RX) |
| PH6 is used for UART5 RX. More...
|
|
#define | UART2MSP432E4_PC7_U5TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 7, GPIO_PC7_U5TX) |
| PC7 is used for UART5 TX. More...
|
|
#define | UART2MSP432E4_PH7_U5TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 7, GPIO_PH7_U5TX) |
| PH7 is used for UART5 TX. More...
|
|
#define | UART2MSP432E4_PP0_U6RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 0, GPIO_PP0_U6RX) |
| PP0 is used for UART6 RX. More...
|
|
#define | UART2MSP432E4_PP1_U6TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTP, 1, GPIO_PP1_U6TX) |
| PP1 is used for UART6 TX. More...
|
|
#define | UART2MSP432E4_PC4_U7RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 4, GPIO_PC4_U7RX) |
| PC4 is used for UART7 RX. More...
|
|
#define | UART2MSP432E4_PH6_U7RX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 6, GPIO_PH6_U7RX) |
| PH6 is used for UART7 RX. More...
|
|
#define | UART2MSP432E4_PC5_U7TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTC, 5, GPIO_PC5_U7TX) |
| PC5 is used for UART7 TX. More...
|
|
#define | UART2MSP432E4_PH7_U7TX GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTH, 7, GPIO_PH7_U7TX) |
| PH7 is used for UART7 TX. More...
|
|