Data Fields
UART2MSP432E4_HWAttrs Struct Reference

UART2MSP432E4 Hardware attributes. More...

#include <UART2MSP432E4.h>

Data Fields

uint32_t baseAddr
 
int intNum
 
uint8_t intPriority
 
uint32_t flowControl
 
uint32_t rxPin
 
uint32_t txPin
 
uint32_t ctsPin
 
uint32_t rtsPin
 
uint32_t rxDmaChannel
 
uint32_t txDmaChannel
 

Detailed Description

UART2MSP432E4 Hardware attributes.

The fields, baseAddr and intNum are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:

intPriority is the UART peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). The MSP432E401Y uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).

  (7 << 5) will apply the lowest priority.
  (1 << 5) will apply the highest priority.

Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

A sample structure is shown below:

const UART2MSP432E4_HWAttrs uart2MSP432E4HWAttrs[] = {
{
.baseAddr = UART0_BASE,
.intNum = INT_UART0,
.intPriority = (~0),
.rxDmaChannel = UDMA_CH8_UART0RX,
.txDmaChannel = UDMA_CH9_UART0TX,
},
{
.baseAddr = UART3_BASE,
.intNum = INT_UART3,
.intPriority = (~0),
.rxDmaChannel = UDMA_CH16_UART3RX,
.txDmaChannel = UDMA_CH17_UART3TX,
},
};

To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2MSP432E4_FLOWCTL_HARDWARE.

Field Documentation

§ baseAddr

uint32_t UART2MSP432E4_HWAttrs::baseAddr

UART Peripheral's base address

§ intNum

int UART2MSP432E4_HWAttrs::intNum

UART Peripheral's interrupt vector

§ intPriority

uint8_t UART2MSP432E4_HWAttrs::intPriority

UART Peripheral's interrupt priority

§ flowControl

uint32_t UART2MSP432E4_HWAttrs::flowControl

Hardware flow control setting

§ rxPin

uint32_t UART2MSP432E4_HWAttrs::rxPin

UART RX pin assignment

§ txPin

uint32_t UART2MSP432E4_HWAttrs::txPin

UART TX pin assignment

§ ctsPin

uint32_t UART2MSP432E4_HWAttrs::ctsPin

UART clear to send (CTS) pin assignment

§ rtsPin

uint32_t UART2MSP432E4_HWAttrs::rtsPin

UART request to send (RTS) pin assignment

§ rxDmaChannel

uint32_t UART2MSP432E4_HWAttrs::rxDmaChannel

uDMA channel for RX data

§ txDmaChannel

uint32_t UART2MSP432E4_HWAttrs::txDmaChannel

uDMA channel for TX data


The documentation for this struct was generated from the following file:
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