J7200 Interrupt Management Device Descriptions

Introduction

This chapter provides information on the Interrupt Management devices in the J7200 SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.

Interrupt Router Device IDs

Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on J7200 Device IDs these are the valid Interrupt Router device IDs.

Interrupt Router Device Name Interrupt Router Device ID
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130
J7200_DEV_TIMESYNC_INTRTR0 136
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137
J7200_DEV_GPIOMUX_INTRTR0 131
J7200_DEV_CMPEVENT_INTRTR0 123
J7200_DEV_NAVSS0_INTR_ROUTER_0 213
J7200_DEV_MCU_NAVSS0_INTR_0 237

MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 0 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 1 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 2 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 3 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 4 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 5 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 6 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 7 J7200_DEV_ELM0 elm_porocpsinterrupt_lvl 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 8 J7200_DEV_GPMC0 gpmc_sinterrupt 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 9 J7200_DEV_DDR0 ddrss_pll_freq_change_req 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 10 J7200_DEV_DDR0 ddrss_controller 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 11 J7200_DEV_DDR0 ddrss_v2a_other_err_lvl 3
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 12 J7200_DEV_DDR0 ddrss_hs_phy_global_error 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 13 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 14 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 15 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 16 J7200_DEV_MCAN0 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 17 J7200_DEV_MCAN0 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 18 J7200_DEV_MCAN0 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 19 J7200_DEV_MCAN1 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 20 J7200_DEV_MCAN1 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 21 J7200_DEV_MCAN1 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 22 J7200_DEV_MCAN2 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 23 J7200_DEV_MCAN2 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 24 J7200_DEV_MCAN2 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 25 J7200_DEV_MCAN3 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 26 J7200_DEV_MCAN3 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 27 J7200_DEV_MCAN3 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 28 J7200_DEV_MMCSD0 emmcss_intr 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 29 J7200_DEV_MMCSD1 emmcsdss_intr 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 30 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 31 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 32 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 33 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 34 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 35 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 36 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 37 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 38 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 39 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 40 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 41 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 42 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 43 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 44 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 45 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 46 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 47 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 48 J7200_DEV_MCSPI0 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 49 J7200_DEV_MCSPI1 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 50 J7200_DEV_MCSPI2 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 51 J7200_DEV_MCSPI3 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 52 J7200_DEV_MCSPI4 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 53 J7200_DEV_MCSPI5 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 54 J7200_DEV_MCSPI6 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 55 J7200_DEV_MCSPI7 intr_spi 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 56 J7200_DEV_I2C0 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 57 J7200_DEV_I2C1 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 58 J7200_DEV_I2C2 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 59 J7200_DEV_I2C3 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 60 J7200_DEV_I2C4 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 61 J7200_DEV_I2C5 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 62 J7200_DEV_I2C6 pointrpend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 63 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 64 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 65 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 66 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 67 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 68 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 69 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 70 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 71 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 72 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 73 J7200_DEV_PCIE1 pcie_phy_level 13
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 74 J7200_DEV_PCIE1 pcie_local_level 12
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 75 J7200_DEV_PCIE1 pcie_cpts_pend 3
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 76 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 77 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 78 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 79 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 80 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 81 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 82 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 83 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 84 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 85 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 86 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 87 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 88 J7200_DEV_DCC0 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 89 J7200_DEV_DCC1 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 90 J7200_DEV_DCC2 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 91 J7200_DEV_DCC3 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 92 J7200_DEV_DCC4 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 93 J7200_DEV_DCC5 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 94 J7200_DEV_DCC6 intr_done_level 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 95 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 96 J7200_DEV_UART0 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 97 J7200_DEV_UART1 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 98 J7200_DEV_UART2 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 99 J7200_DEV_UART3 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 100 J7200_DEV_UART4 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 101 J7200_DEV_UART5 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 102 J7200_DEV_UART6 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 103 J7200_DEV_UART7 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 104 J7200_DEV_UART8 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 105 J7200_DEV_UART9 usart_irq 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 106 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 107 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 108 J7200_DEV_TIMER0 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 109 J7200_DEV_TIMER1 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 110 J7200_DEV_TIMER2 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 111 J7200_DEV_TIMER3 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 112 J7200_DEV_TIMER4 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 113 J7200_DEV_TIMER5 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 114 J7200_DEV_TIMER6 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 115 J7200_DEV_TIMER7 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 116 J7200_DEV_TIMER8 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 117 J7200_DEV_TIMER9 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 118 J7200_DEV_TIMER10 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 119 J7200_DEV_TIMER11 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 120 J7200_DEV_TIMER12 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 121 J7200_DEV_TIMER13 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 122 J7200_DEV_TIMER14 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 123 J7200_DEV_TIMER15 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 124 J7200_DEV_TIMER16 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 125 J7200_DEV_TIMER17 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 126 J7200_DEV_TIMER18 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 127 J7200_DEV_TIMER19 intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 128 J7200_DEV_USB0 irq 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 129 J7200_DEV_USB0 irq 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 130 J7200_DEV_USB0 irq 3
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 131 J7200_DEV_USB0 irq 4
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 132 J7200_DEV_USB0 irq 5
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 133 J7200_DEV_USB0 irq 6
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 134 J7200_DEV_USB0 irq 7
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 135 J7200_DEV_USB0 irq 8
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 136 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 137 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 138 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 139 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 140 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 141 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 142 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 143 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 144 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 145 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 146 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 147 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 148 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 149 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 150 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 151 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 152 J7200_DEV_USB0 otgirq 9
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 153 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 154 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 155 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 156 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 157 J7200_DEV_USB0 host_system_error 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 158 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 159 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 160 J7200_DEV_MCAN14 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 161 J7200_DEV_MCAN14 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 162 J7200_DEV_MCAN14 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 163 J7200_DEV_MCAN15 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 164 J7200_DEV_MCAN15 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 165 J7200_DEV_MCAN15 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 166 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 167 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 168 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 169 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 170 J7200_DEV_MCAN16 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 171 J7200_DEV_MCAN16 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 172 J7200_DEV_MCAN16 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 173 J7200_DEV_MCAN17 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 174 J7200_DEV_MCAN17 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 175 J7200_DEV_MCAN17 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 176 J7200_DEV_MCASP0 xmit_intr_pend 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 177 J7200_DEV_MCASP0 rec_intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 178 J7200_DEV_MCASP1 xmit_intr_pend 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 179 J7200_DEV_MCASP1 rec_intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 180 J7200_DEV_MCASP2 xmit_intr_pend 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 181 J7200_DEV_MCASP2 rec_intr_pend 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 182 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 183 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 184 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 185 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 186 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 187 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 188 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 189 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 190 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 191 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 192 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 193 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 194 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 195 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 196 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 197 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 198 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 199 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 200 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 201 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 202 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 203 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 204 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 205 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 206 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 207 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 208 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 209 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 210 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 211 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 212 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 213 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 214 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 215 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 216 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 217 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 218 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 219 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 220 J7200_DEV_I3C0 i3c__int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 221 J7200_DEV_CPSW0 stat_pend 6
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 222 J7200_DEV_CPSW0 mdio_pend 5
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 223 J7200_DEV_CPSW0 evnt_pend 4
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 224 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 225 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 226 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 227 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 228 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 229 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 230 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 231 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 232 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 233 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 234 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 235 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 236 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 237 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 238 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 239 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 240 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 241 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 242 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 243 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 244 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 245 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 246 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 247 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 248 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 249 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 250 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 251 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 252 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 253 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 254 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 255 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 256 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 257 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 258 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 259 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 260 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 261 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 262 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 263 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 264 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 265 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 266 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 267 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 268 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 269 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 270 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 271 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 272 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 273 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 274 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 275 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 276 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 277 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 278 J7200_DEV_MCAN4 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 279 J7200_DEV_MCAN4 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 280 J7200_DEV_MCAN4 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 281 J7200_DEV_MCAN5 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 282 J7200_DEV_MCAN5 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 283 J7200_DEV_MCAN5 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 284 J7200_DEV_MCAN6 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 285 J7200_DEV_MCAN6 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 286 J7200_DEV_MCAN6 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 287 J7200_DEV_MCAN7 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 288 J7200_DEV_MCAN7 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 289 J7200_DEV_MCAN7 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 290 J7200_DEV_MCAN8 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 291 J7200_DEV_MCAN8 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 292 J7200_DEV_MCAN8 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 293 J7200_DEV_MCAN9 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 294 J7200_DEV_MCAN9 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 295 J7200_DEV_MCAN9 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 296 J7200_DEV_MCAN10 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 297 J7200_DEV_MCAN10 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 298 J7200_DEV_MCAN10 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 299 J7200_DEV_MCAN11 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 300 J7200_DEV_MCAN11 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 301 J7200_DEV_MCAN11 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 302 J7200_DEV_MCAN12 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 303 J7200_DEV_MCAN12 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 304 J7200_DEV_MCAN12 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 305 J7200_DEV_MCAN13 mcanss_mcan_lvl_int 1
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 306 J7200_DEV_MCAN13 mcanss_mcan_lvl_int 2
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 307 J7200_DEV_MCAN13 mcanss_ext_ts_rollover_lvl_int 0
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 308 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 309 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 310 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 311 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 312 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 313 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 314 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 315 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 316 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 317 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 318 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 319 Use TRM - Not managed by TISCI    

MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 0 J7200_DEV_MCU_R5FSS0_CORE0 intr 160
      J7200_DEV_MCU_R5FSS0_CORE1 intr 160
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 1 J7200_DEV_MCU_R5FSS0_CORE0 intr 161
      J7200_DEV_MCU_R5FSS0_CORE1 intr 161
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 2 J7200_DEV_MCU_R5FSS0_CORE0 intr 162
      J7200_DEV_MCU_R5FSS0_CORE1 intr 162
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 3 J7200_DEV_MCU_R5FSS0_CORE0 intr 163
      J7200_DEV_MCU_R5FSS0_CORE1 intr 163
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 4 J7200_DEV_MCU_R5FSS0_CORE0 intr 164
      J7200_DEV_MCU_R5FSS0_CORE1 intr 164
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 5 J7200_DEV_MCU_R5FSS0_CORE0 intr 165
      J7200_DEV_MCU_R5FSS0_CORE1 intr 165
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 6 J7200_DEV_MCU_R5FSS0_CORE0 intr 166
      J7200_DEV_MCU_R5FSS0_CORE1 intr 166
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 7 J7200_DEV_MCU_R5FSS0_CORE0 intr 167
      J7200_DEV_MCU_R5FSS0_CORE1 intr 167
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 8 J7200_DEV_MCU_R5FSS0_CORE0 intr 168
      J7200_DEV_MCU_R5FSS0_CORE1 intr 168
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 9 J7200_DEV_MCU_R5FSS0_CORE0 intr 169
      J7200_DEV_MCU_R5FSS0_CORE1 intr 169
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 10 J7200_DEV_MCU_R5FSS0_CORE0 intr 170
      J7200_DEV_MCU_R5FSS0_CORE1 intr 170
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 11 J7200_DEV_MCU_R5FSS0_CORE0 intr 171
      J7200_DEV_MCU_R5FSS0_CORE1 intr 171
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 12 J7200_DEV_MCU_R5FSS0_CORE0 intr 172
      J7200_DEV_MCU_R5FSS0_CORE1 intr 172
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 13 J7200_DEV_MCU_R5FSS0_CORE0 intr 173
      J7200_DEV_MCU_R5FSS0_CORE1 intr 173
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 14 J7200_DEV_MCU_R5FSS0_CORE0 intr 174
      J7200_DEV_MCU_R5FSS0_CORE1 intr 174
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 15 J7200_DEV_MCU_R5FSS0_CORE0 intr 175
      J7200_DEV_MCU_R5FSS0_CORE1 intr 175
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 16 J7200_DEV_MCU_R5FSS0_CORE0 intr 176
      J7200_DEV_MCU_R5FSS0_CORE1 intr 176
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 17 J7200_DEV_MCU_R5FSS0_CORE0 intr 177
      J7200_DEV_MCU_R5FSS0_CORE1 intr 177
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 18 J7200_DEV_MCU_R5FSS0_CORE0 intr 178
      J7200_DEV_MCU_R5FSS0_CORE1 intr 178
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 19 J7200_DEV_MCU_R5FSS0_CORE0 intr 179
      J7200_DEV_MCU_R5FSS0_CORE1 intr 179
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 20 J7200_DEV_MCU_R5FSS0_CORE0 intr 180
      J7200_DEV_MCU_R5FSS0_CORE1 intr 180
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 21 J7200_DEV_MCU_R5FSS0_CORE0 intr 181
      J7200_DEV_MCU_R5FSS0_CORE1 intr 181
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 22 J7200_DEV_MCU_R5FSS0_CORE0 intr 182
      J7200_DEV_MCU_R5FSS0_CORE1 intr 182
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 23 J7200_DEV_MCU_R5FSS0_CORE0 intr 183
      J7200_DEV_MCU_R5FSS0_CORE1 intr 183
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 24 J7200_DEV_MCU_R5FSS0_CORE0 intr 184
      J7200_DEV_MCU_R5FSS0_CORE1 intr 184
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 25 J7200_DEV_MCU_R5FSS0_CORE0 intr 185
      J7200_DEV_MCU_R5FSS0_CORE1 intr 185
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 26 J7200_DEV_MCU_R5FSS0_CORE0 intr 186
      J7200_DEV_MCU_R5FSS0_CORE1 intr 186
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 27 J7200_DEV_MCU_R5FSS0_CORE0 intr 187
      J7200_DEV_MCU_R5FSS0_CORE1 intr 187
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 28 J7200_DEV_MCU_R5FSS0_CORE0 intr 188
      J7200_DEV_MCU_R5FSS0_CORE1 intr 188
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 29 J7200_DEV_MCU_R5FSS0_CORE0 intr 189
      J7200_DEV_MCU_R5FSS0_CORE1 intr 189
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 30 J7200_DEV_MCU_R5FSS0_CORE0 intr 190
      J7200_DEV_MCU_R5FSS0_CORE1 intr 190
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 31 J7200_DEV_MCU_R5FSS0_CORE0 intr 191
      J7200_DEV_MCU_R5FSS0_CORE1 intr 191
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 32 J7200_DEV_MCU_R5FSS0_CORE0 intr 192
      J7200_DEV_MCU_R5FSS0_CORE1 intr 192
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 33 J7200_DEV_MCU_R5FSS0_CORE0 intr 193
      J7200_DEV_MCU_R5FSS0_CORE1 intr 193
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 34 J7200_DEV_MCU_R5FSS0_CORE0 intr 194
      J7200_DEV_MCU_R5FSS0_CORE1 intr 194
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 35 J7200_DEV_MCU_R5FSS0_CORE0 intr 195
      J7200_DEV_MCU_R5FSS0_CORE1 intr 195
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 36 J7200_DEV_MCU_R5FSS0_CORE0 intr 196
      J7200_DEV_MCU_R5FSS0_CORE1 intr 196
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 37 J7200_DEV_MCU_R5FSS0_CORE0 intr 197
      J7200_DEV_MCU_R5FSS0_CORE1 intr 197
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 38 J7200_DEV_MCU_R5FSS0_CORE0 intr 198
      J7200_DEV_MCU_R5FSS0_CORE1 intr 198
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 39 J7200_DEV_MCU_R5FSS0_CORE0 intr 199
      J7200_DEV_MCU_R5FSS0_CORE1 intr 199
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 40 J7200_DEV_MCU_R5FSS0_CORE0 intr 200
      J7200_DEV_MCU_R5FSS0_CORE1 intr 200
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 41 J7200_DEV_MCU_R5FSS0_CORE0 intr 201
      J7200_DEV_MCU_R5FSS0_CORE1 intr 201
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 42 J7200_DEV_MCU_R5FSS0_CORE0 intr 202
      J7200_DEV_MCU_R5FSS0_CORE1 intr 202
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 43 J7200_DEV_MCU_R5FSS0_CORE0 intr 203
      J7200_DEV_MCU_R5FSS0_CORE1 intr 203
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 44 J7200_DEV_MCU_R5FSS0_CORE0 intr 204
      J7200_DEV_MCU_R5FSS0_CORE1 intr 204
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 45 J7200_DEV_MCU_R5FSS0_CORE0 intr 205
      J7200_DEV_MCU_R5FSS0_CORE1 intr 205
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 46 J7200_DEV_MCU_R5FSS0_CORE0 intr 206
      J7200_DEV_MCU_R5FSS0_CORE1 intr 206
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 47 J7200_DEV_MCU_R5FSS0_CORE0 intr 207
      J7200_DEV_MCU_R5FSS0_CORE1 intr 207
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 48 J7200_DEV_MCU_R5FSS0_CORE0 intr 208
      J7200_DEV_MCU_R5FSS0_CORE1 intr 208
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 49 J7200_DEV_MCU_R5FSS0_CORE0 intr 209
      J7200_DEV_MCU_R5FSS0_CORE1 intr 209
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 50 J7200_DEV_MCU_R5FSS0_CORE0 intr 210
      J7200_DEV_MCU_R5FSS0_CORE1 intr 210
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 51 J7200_DEV_MCU_R5FSS0_CORE0 intr 211
      J7200_DEV_MCU_R5FSS0_CORE1 intr 211
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 52 J7200_DEV_MCU_R5FSS0_CORE0 intr 212
      J7200_DEV_MCU_R5FSS0_CORE1 intr 212
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 53 J7200_DEV_MCU_R5FSS0_CORE0 intr 213
      J7200_DEV_MCU_R5FSS0_CORE1 intr 213
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 54 J7200_DEV_MCU_R5FSS0_CORE0 intr 214
      J7200_DEV_MCU_R5FSS0_CORE1 intr 214
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 55 J7200_DEV_MCU_R5FSS0_CORE0 intr 215
      J7200_DEV_MCU_R5FSS0_CORE1 intr 215
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 56 J7200_DEV_MCU_R5FSS0_CORE0 intr 216
      J7200_DEV_MCU_R5FSS0_CORE1 intr 216
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 57 J7200_DEV_MCU_R5FSS0_CORE0 intr 217
      J7200_DEV_MCU_R5FSS0_CORE1 intr 217
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 58 J7200_DEV_MCU_R5FSS0_CORE0 intr 218
      J7200_DEV_MCU_R5FSS0_CORE1 intr 218
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 59 J7200_DEV_MCU_R5FSS0_CORE0 intr 219
      J7200_DEV_MCU_R5FSS0_CORE1 intr 219
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 60 J7200_DEV_MCU_R5FSS0_CORE0 intr 220
      J7200_DEV_MCU_R5FSS0_CORE1 intr 220
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 61 J7200_DEV_MCU_R5FSS0_CORE0 intr 221
      J7200_DEV_MCU_R5FSS0_CORE1 intr 221
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 62 J7200_DEV_MCU_R5FSS0_CORE0 intr 222
      J7200_DEV_MCU_R5FSS0_CORE1 intr 222
J7200_DEV_MAIN2MCU_LVL_INTRTR0 128 63 J7200_DEV_MCU_R5FSS0_CORE0 intr 223
      J7200_DEV_MCU_R5FSS0_CORE1 intr 223

MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 0 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 1 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 2 J7200_DEV_EHRPWM0 epwm_etint 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 3 J7200_DEV_EHRPWM1 epwm_etint 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 4 J7200_DEV_EHRPWM2 epwm_etint 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 5 J7200_DEV_EHRPWM3 epwm_etint 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 6 J7200_DEV_EHRPWM4 epwm_etint 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 7 J7200_DEV_EHRPWM5 epwm_etint 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 8 J7200_DEV_EHRPWM0 epwm_tripzint 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 9 J7200_DEV_EHRPWM1 epwm_tripzint 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 10 J7200_DEV_EHRPWM2 epwm_tripzint 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 11 J7200_DEV_EHRPWM3 epwm_tripzint 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 12 J7200_DEV_EHRPWM4 epwm_tripzint 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 13 J7200_DEV_EHRPWM5 epwm_tripzint 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 14 J7200_DEV_EQEP0 eqep_int 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 15 J7200_DEV_EQEP1 eqep_int 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 16 J7200_DEV_EQEP2 eqep_int 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 17 J7200_DEV_ECAP0 ecap_int 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 18 J7200_DEV_ECAP1 ecap_int 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 19 J7200_DEV_ECAP2 ecap_int 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 20 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 21 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 22 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 23 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 24 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 25 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 26 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 27 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 28 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 29 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 30 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 31 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 32 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 33 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 34 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 35 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 36 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 37 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 38 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 39 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 40 J7200_DEV_PCIE1 pcie_legacy_pulse 10
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 41 J7200_DEV_PCIE1 pcie_downstream_pulse 5
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 42 J7200_DEV_PCIE1 pcie_flr_pulse 8
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 43 J7200_DEV_PCIE1 pcie_error_pulse 7
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 44 J7200_DEV_PCIE1 pcie_link_state_pulse 11
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 45 J7200_DEV_PCIE1 pcie_pwr_state_pulse 15
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 46 J7200_DEV_PCIE1 pcie_ptm_valid_pulse 14
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 47 J7200_DEV_PCIE1 pcie_hot_reset_pulse 9
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 48 J7200_DEV_PCIE1 pcie_dpa_pulse 6
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 49 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 50 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 51 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 52 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 53 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 54 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 55 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 56 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 57 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 58 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 59 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 60 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 61 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 62 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 63 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 64 J7200_DEV_GPIOMUX_INTRTR0 outp 0
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 65 J7200_DEV_GPIOMUX_INTRTR0 outp 1
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 66 J7200_DEV_GPIOMUX_INTRTR0 outp 2
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 67 J7200_DEV_GPIOMUX_INTRTR0 outp 3
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 68 J7200_DEV_GPIOMUX_INTRTR0 outp 4
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 69 J7200_DEV_GPIOMUX_INTRTR0 outp 5
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 70 J7200_DEV_GPIOMUX_INTRTR0 outp 6
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 71 J7200_DEV_GPIOMUX_INTRTR0 outp 7
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 72 J7200_DEV_GPIOMUX_INTRTR0 outp 8
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 73 J7200_DEV_GPIOMUX_INTRTR0 outp 9
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 74 J7200_DEV_GPIOMUX_INTRTR0 outp 10
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 75 J7200_DEV_GPIOMUX_INTRTR0 outp 11
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 76 J7200_DEV_GPIOMUX_INTRTR0 outp 12
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 77 J7200_DEV_GPIOMUX_INTRTR0 outp 13
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 78 J7200_DEV_GPIOMUX_INTRTR0 outp 14
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 79 J7200_DEV_GPIOMUX_INTRTR0 outp 15
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 80 J7200_DEV_GPIOMUX_INTRTR0 outp 16
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 81 J7200_DEV_GPIOMUX_INTRTR0 outp 17
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 82 J7200_DEV_GPIOMUX_INTRTR0 outp 18
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 83 J7200_DEV_GPIOMUX_INTRTR0 outp 19
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 84 J7200_DEV_GPIOMUX_INTRTR0 outp 20
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 85 J7200_DEV_GPIOMUX_INTRTR0 outp 21
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 86 J7200_DEV_GPIOMUX_INTRTR0 outp 22
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 87 J7200_DEV_GPIOMUX_INTRTR0 outp 23
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 88 J7200_DEV_GPIOMUX_INTRTR0 outp 24
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 89 J7200_DEV_GPIOMUX_INTRTR0 outp 25
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 90 J7200_DEV_GPIOMUX_INTRTR0 outp 26
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 91 J7200_DEV_GPIOMUX_INTRTR0 outp 27
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 92 J7200_DEV_GPIOMUX_INTRTR0 outp 28
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 93 J7200_DEV_GPIOMUX_INTRTR0 outp 29
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 94 J7200_DEV_GPIOMUX_INTRTR0 outp 30
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 95 J7200_DEV_GPIOMUX_INTRTR0 outp 31
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 96 J7200_DEV_CMPEVENT_INTRTR0 outp 4
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 97 J7200_DEV_CMPEVENT_INTRTR0 outp 5
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 98 J7200_DEV_CMPEVENT_INTRTR0 outp 6
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 99 J7200_DEV_CMPEVENT_INTRTR0 outp 7
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 100 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 101 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 102 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 103 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 104 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 105 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 106 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 107 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 108 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 109 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 110 Use TRM - Not managed by TISCI    
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 111 Use TRM - Not managed by TISCI    

MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 0 J7200_DEV_MCU_R5FSS0_CORE0 intr 224
      J7200_DEV_MCU_R5FSS0_CORE1 intr 224
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 1 J7200_DEV_MCU_R5FSS0_CORE0 intr 225
      J7200_DEV_MCU_R5FSS0_CORE1 intr 225
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 2 J7200_DEV_MCU_R5FSS0_CORE0 intr 226
      J7200_DEV_MCU_R5FSS0_CORE1 intr 226
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 3 J7200_DEV_MCU_R5FSS0_CORE0 intr 227
      J7200_DEV_MCU_R5FSS0_CORE1 intr 227
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 4 J7200_DEV_MCU_R5FSS0_CORE0 intr 228
      J7200_DEV_MCU_R5FSS0_CORE1 intr 228
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 5 J7200_DEV_MCU_R5FSS0_CORE0 intr 229
      J7200_DEV_MCU_R5FSS0_CORE1 intr 229
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 6 J7200_DEV_MCU_R5FSS0_CORE0 intr 230
      J7200_DEV_MCU_R5FSS0_CORE1 intr 230
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 7 J7200_DEV_MCU_R5FSS0_CORE0 intr 231
      J7200_DEV_MCU_R5FSS0_CORE1 intr 231
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 8 J7200_DEV_MCU_R5FSS0_CORE0 intr 232
      J7200_DEV_MCU_R5FSS0_CORE1 intr 232
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 9 J7200_DEV_MCU_R5FSS0_CORE0 intr 233
      J7200_DEV_MCU_R5FSS0_CORE1 intr 233
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 10 J7200_DEV_MCU_R5FSS0_CORE0 intr 234
      J7200_DEV_MCU_R5FSS0_CORE1 intr 234
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 11 J7200_DEV_MCU_R5FSS0_CORE0 intr 235
      J7200_DEV_MCU_R5FSS0_CORE1 intr 235
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 12 J7200_DEV_MCU_R5FSS0_CORE0 intr 236
      J7200_DEV_MCU_R5FSS0_CORE1 intr 236
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 13 J7200_DEV_MCU_R5FSS0_CORE0 intr 237
      J7200_DEV_MCU_R5FSS0_CORE1 intr 237
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 14 J7200_DEV_MCU_R5FSS0_CORE0 intr 238
      J7200_DEV_MCU_R5FSS0_CORE1 intr 238
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 15 J7200_DEV_MCU_R5FSS0_CORE0 intr 239
      J7200_DEV_MCU_R5FSS0_CORE1 intr 239
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 16 J7200_DEV_MCU_R5FSS0_CORE0 intr 240
      J7200_DEV_MCU_R5FSS0_CORE1 intr 240
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 17 J7200_DEV_MCU_R5FSS0_CORE0 intr 241
      J7200_DEV_MCU_R5FSS0_CORE1 intr 241
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 18 J7200_DEV_MCU_R5FSS0_CORE0 intr 242
      J7200_DEV_MCU_R5FSS0_CORE1 intr 242
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 19 J7200_DEV_MCU_R5FSS0_CORE0 intr 243
      J7200_DEV_MCU_R5FSS0_CORE1 intr 243
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 20 J7200_DEV_MCU_R5FSS0_CORE0 intr 244
      J7200_DEV_MCU_R5FSS0_CORE1 intr 244
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 21 J7200_DEV_MCU_R5FSS0_CORE0 intr 245
      J7200_DEV_MCU_R5FSS0_CORE1 intr 245
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 22 J7200_DEV_MCU_R5FSS0_CORE0 intr 246
      J7200_DEV_MCU_R5FSS0_CORE1 intr 246
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 23 J7200_DEV_MCU_R5FSS0_CORE0 intr 247
      J7200_DEV_MCU_R5FSS0_CORE1 intr 247
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 24 J7200_DEV_MCU_R5FSS0_CORE0 intr 248
      J7200_DEV_MCU_R5FSS0_CORE1 intr 248
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 25 J7200_DEV_MCU_R5FSS0_CORE0 intr 249
      J7200_DEV_MCU_R5FSS0_CORE1 intr 249
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 26 J7200_DEV_MCU_R5FSS0_CORE0 intr 250
      J7200_DEV_MCU_R5FSS0_CORE1 intr 250
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 27 J7200_DEV_MCU_R5FSS0_CORE0 intr 251
      J7200_DEV_MCU_R5FSS0_CORE1 intr 251
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 28 J7200_DEV_MCU_R5FSS0_CORE0 intr 252
      J7200_DEV_MCU_R5FSS0_CORE1 intr 252
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 29 J7200_DEV_MCU_R5FSS0_CORE0 intr 253
      J7200_DEV_MCU_R5FSS0_CORE1 intr 253
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 30 J7200_DEV_MCU_R5FSS0_CORE0 intr 254
      J7200_DEV_MCU_R5FSS0_CORE1 intr 254
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 31 J7200_DEV_MCU_R5FSS0_CORE0 intr 255
      J7200_DEV_MCU_R5FSS0_CORE1 intr 255
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 32 J7200_DEV_MCU_R5FSS0_CORE0 intr 256
      J7200_DEV_MCU_R5FSS0_CORE1 intr 256
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 33 J7200_DEV_MCU_R5FSS0_CORE0 intr 257
      J7200_DEV_MCU_R5FSS0_CORE1 intr 257
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 34 J7200_DEV_MCU_R5FSS0_CORE0 intr 258
      J7200_DEV_MCU_R5FSS0_CORE1 intr 258
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 35 J7200_DEV_MCU_R5FSS0_CORE0 intr 259
      J7200_DEV_MCU_R5FSS0_CORE1 intr 259
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 36 J7200_DEV_MCU_R5FSS0_CORE0 intr 260
      J7200_DEV_MCU_R5FSS0_CORE1 intr 260
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 37 J7200_DEV_MCU_R5FSS0_CORE0 intr 261
      J7200_DEV_MCU_R5FSS0_CORE1 intr 261
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 38 J7200_DEV_MCU_R5FSS0_CORE0 intr 262
      J7200_DEV_MCU_R5FSS0_CORE1 intr 262
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 39 J7200_DEV_MCU_R5FSS0_CORE0 intr 263
      J7200_DEV_MCU_R5FSS0_CORE1 intr 263
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 40 J7200_DEV_MCU_R5FSS0_CORE0 intr 264
      J7200_DEV_MCU_R5FSS0_CORE1 intr 264
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 41 J7200_DEV_MCU_R5FSS0_CORE0 intr 265
      J7200_DEV_MCU_R5FSS0_CORE1 intr 265
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 42 J7200_DEV_MCU_R5FSS0_CORE0 intr 266
      J7200_DEV_MCU_R5FSS0_CORE1 intr 266
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 43 J7200_DEV_MCU_R5FSS0_CORE0 intr 267
      J7200_DEV_MCU_R5FSS0_CORE1 intr 267
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 44 J7200_DEV_MCU_R5FSS0_CORE0 intr 268
      J7200_DEV_MCU_R5FSS0_CORE1 intr 268
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 45 J7200_DEV_MCU_R5FSS0_CORE0 intr 269
      J7200_DEV_MCU_R5FSS0_CORE1 intr 269
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 46 J7200_DEV_MCU_R5FSS0_CORE0 intr 270
      J7200_DEV_MCU_R5FSS0_CORE1 intr 270
J7200_DEV_MAIN2MCU_PLS_INTRTR0 130 47 J7200_DEV_MCU_R5FSS0_CORE0 intr 271
      J7200_DEV_MCU_R5FSS0_CORE1 intr 271

TIMESYNC_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_TIMESYNC_INTRTR0 136 0 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 1 J7200_DEV_GTC0 gtc_push_event 0
J7200_DEV_TIMESYNC_INTRTR0 136 2 J7200_DEV_TIMER14 timer_pwm 1
J7200_DEV_TIMESYNC_INTRTR0 136 3 J7200_DEV_TIMER15 timer_pwm 1
J7200_DEV_TIMESYNC_INTRTR0 136 4 J7200_DEV_NAVSS0 cpts0_genf0 1
J7200_DEV_TIMESYNC_INTRTR0 136 5 J7200_DEV_NAVSS0 cpts0_genf1 2
J7200_DEV_TIMESYNC_INTRTR0 136 6 J7200_DEV_NAVSS0 cpts0_genf2 3
J7200_DEV_TIMESYNC_INTRTR0 136 7 J7200_DEV_NAVSS0 cpts0_genf3 4
J7200_DEV_TIMESYNC_INTRTR0 136 8 J7200_DEV_NAVSS0 cpts0_genf4 5
J7200_DEV_TIMESYNC_INTRTR0 136 9 J7200_DEV_NAVSS0 cpts0_genf5 6
J7200_DEV_TIMESYNC_INTRTR0 136 10 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 11 J7200_DEV_PCIE1 pcie_cpts_genf0 1
J7200_DEV_TIMESYNC_INTRTR0 136 12 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 13 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 14 J7200_DEV_CPSW0 cpts_genf0 1
J7200_DEV_TIMESYNC_INTRTR0 136 15 J7200_DEV_CPSW0 cpts_genf1 2
J7200_DEV_TIMESYNC_INTRTR0 136 16 J7200_DEV_MCU_CPSW0 cpts_genf0 1
J7200_DEV_TIMESYNC_INTRTR0 136 17 J7200_DEV_MCU_CPSW0 cpts_genf1 2
J7200_DEV_TIMESYNC_INTRTR0 136 18 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 19 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 20 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 21 J7200_DEV_PCIE1 pcie_cpts_hw1_push 2
J7200_DEV_TIMESYNC_INTRTR0 136 22 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 23 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 24 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 25 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 26 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 27 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 28 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 29 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 30 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 31 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 32 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 33 J7200_DEV_PCIE1 pcie_cpts_sync 4
J7200_DEV_TIMESYNC_INTRTR0 136 34 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 35 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 36 J7200_DEV_NAVSS0 cpts0_sync 7
J7200_DEV_TIMESYNC_INTRTR0 136 37 J7200_DEV_CPSW0 cpts_sync 3
J7200_DEV_TIMESYNC_INTRTR0 136 38 J7200_DEV_MCU_CPSW0 cpts_sync 3
J7200_DEV_TIMESYNC_INTRTR0 136 39 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 40 J7200_DEV_TIMER16 timer_pwm 1
J7200_DEV_TIMESYNC_INTRTR0 136 41 J7200_DEV_TIMER17 timer_pwm 1
J7200_DEV_TIMESYNC_INTRTR0 136 42 J7200_DEV_TIMER18 timer_pwm 1
J7200_DEV_TIMESYNC_INTRTR0 136 43 J7200_DEV_TIMER19 timer_pwm 1
J7200_DEV_TIMESYNC_INTRTR0 136 44 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 45 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 46 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 47 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 48 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 49 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 50 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 51 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 52 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 53 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 54 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 55 Use TRM - Not managed by TISCI    

TIMESYNC_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_TIMESYNC_INTRTR0 136 0 J7200_DEV_NAVSS0 cpts0_hw1_push 0
J7200_DEV_TIMESYNC_INTRTR0 136 1 J7200_DEV_NAVSS0 cpts0_hw2_push 1
J7200_DEV_TIMESYNC_INTRTR0 136 2 J7200_DEV_NAVSS0 cpts0_hw3_push 2
J7200_DEV_TIMESYNC_INTRTR0 136 3 J7200_DEV_NAVSS0 cpts0_hw4_push 3
J7200_DEV_TIMESYNC_INTRTR0 136 4 J7200_DEV_NAVSS0 cpts0_hw5_push 4
J7200_DEV_TIMESYNC_INTRTR0 136 5 J7200_DEV_NAVSS0 cpts0_hw6_push 5
J7200_DEV_TIMESYNC_INTRTR0 136 6 J7200_DEV_NAVSS0 cpts0_hw7_push 6
J7200_DEV_TIMESYNC_INTRTR0 136 7 J7200_DEV_NAVSS0 cpts0_hw8_push 7
J7200_DEV_TIMESYNC_INTRTR0 136 8 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 9 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 10 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 11 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 12 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 13 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 14 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 15 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 16 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 17 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 18 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 19 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 20 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 21 J7200_DEV_PCIE1 pcie_cpts_hw2_push 0
J7200_DEV_TIMESYNC_INTRTR0 136 22 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 23 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 24 J7200_DEV_MCU_CPSW0 cpts_hw3_push 0
J7200_DEV_TIMESYNC_INTRTR0 136 25 J7200_DEV_MCU_CPSW0 cpts_hw4_push 1
J7200_DEV_TIMESYNC_INTRTR0 136 26 J7200_DEV_CPSW0 cpts_hw1_push 0
J7200_DEV_TIMESYNC_INTRTR0 136 27 J7200_DEV_CPSW0 cpts_hw2_push 1
J7200_DEV_TIMESYNC_INTRTR0 136 28 J7200_DEV_CPSW0 cpts_hw3_push 2
J7200_DEV_TIMESYNC_INTRTR0 136 29 J7200_DEV_CPSW0 cpts_hw4_push 3
J7200_DEV_TIMESYNC_INTRTR0 136 30 J7200_DEV_CPSW0 cpts_hw5_push 4
J7200_DEV_TIMESYNC_INTRTR0 136 31 J7200_DEV_CPSW0 cpts_hw6_push 5
J7200_DEV_TIMESYNC_INTRTR0 136 32 J7200_DEV_CPSW0 cpts_hw7_push 6
J7200_DEV_TIMESYNC_INTRTR0 136 33 J7200_DEV_CPSW0 cpts_hw8_push 7
J7200_DEV_TIMESYNC_INTRTR0 136 34 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 35 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 36 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 37 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 38 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 39 Use TRM - Not managed by TISCI    
J7200_DEV_TIMESYNC_INTRTR0 136 40 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 52
J7200_DEV_TIMESYNC_INTRTR0 136 41 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 53
J7200_DEV_TIMESYNC_INTRTR0 136 42 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 54
J7200_DEV_TIMESYNC_INTRTR0 136 43 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 55
J7200_DEV_TIMESYNC_INTRTR0 136 44 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 56
J7200_DEV_TIMESYNC_INTRTR0 136 45 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 57
J7200_DEV_TIMESYNC_INTRTR0 136 46 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 58
J7200_DEV_TIMESYNC_INTRTR0 136 47 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 59

WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 0 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 1 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 2 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 3 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 4 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 5 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 6 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 7 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 8 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 9 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 10 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 11 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 12 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 13 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 14 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 15 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 16 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 17 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 18 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 19 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 20 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 21 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 22 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 23 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 24 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 25 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 26 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 27 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 28 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 29 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 30 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 31 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 32 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 33 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 34 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 35 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 36 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 37 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 38 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 39 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 40 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 41 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 42 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 43 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 44 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 45 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 46 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 47 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 48 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 49 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 50 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 51 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 52 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 53 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 54 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 55 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 56 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 57 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 58 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 59 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 60 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 61 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 62 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 63 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 64 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 65 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 66 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 67 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 68 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 69 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 70 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 71 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 72 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 73 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 74 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 75 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 76 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 77 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 78 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 79 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 80 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 81 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 82 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 83 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 84 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 85 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 86 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 87 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 88 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 89 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 90 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 91 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 92 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 93 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 94 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 95 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 96 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 97 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 98 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 99 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 100 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 101 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 102 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 103 J7200_DEV_WKUP_GPIO0 gpio_bank 0
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 104 J7200_DEV_WKUP_GPIO0 gpio_bank 1
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 105 J7200_DEV_WKUP_GPIO0 gpio_bank 2
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 106 J7200_DEV_WKUP_GPIO0 gpio_bank 3
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 107 J7200_DEV_WKUP_GPIO0 gpio_bank 4
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 108 J7200_DEV_WKUP_GPIO0 gpio_bank 5
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 109 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 110 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 111 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 112 J7200_DEV_WKUP_GPIO1 gpio_bank 0
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 113 J7200_DEV_WKUP_GPIO1 gpio_bank 1
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 114 J7200_DEV_WKUP_GPIO1 gpio_bank 2
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 115 J7200_DEV_WKUP_GPIO1 gpio_bank 3
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 116 J7200_DEV_WKUP_GPIO1 gpio_bank 4
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 117 J7200_DEV_WKUP_GPIO1 gpio_bank 5
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 118 Use TRM - Not managed by TISCI    
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 119 Use TRM - Not managed by TISCI    

WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 0 J7200_DEV_MCU_R5FSS0_CORE0 intr 124
      J7200_DEV_MCU_R5FSS0_CORE1 intr 124
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 1 J7200_DEV_MCU_R5FSS0_CORE0 intr 125
      J7200_DEV_MCU_R5FSS0_CORE1 intr 125
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 2 J7200_DEV_MCU_R5FSS0_CORE0 intr 126
      J7200_DEV_MCU_R5FSS0_CORE1 intr 126
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 3 J7200_DEV_MCU_R5FSS0_CORE0 intr 127
      J7200_DEV_MCU_R5FSS0_CORE1 intr 127
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 4 J7200_DEV_MCU_R5FSS0_CORE0 intr 128
      J7200_DEV_MCU_R5FSS0_CORE1 intr 128
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 5 J7200_DEV_MCU_R5FSS0_CORE0 intr 129
      J7200_DEV_MCU_R5FSS0_CORE1 intr 129
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 6 J7200_DEV_MCU_R5FSS0_CORE0 intr 130
      J7200_DEV_MCU_R5FSS0_CORE1 intr 130
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 7 J7200_DEV_MCU_R5FSS0_CORE0 intr 131
      J7200_DEV_MCU_R5FSS0_CORE1 intr 131
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 8 J7200_DEV_WKUP_ESM0 esm_pls_event0 120
      J7200_DEV_WKUP_ESM0 esm_pls_event1 128
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 8 J7200_DEV_WKUP_ESM0 esm_pls_event2 136
      J7200_DEV_MCU_R5FSS0_CORE0 intr 132
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 8 J7200_DEV_MCU_R5FSS0_CORE1 intr 132
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 9 J7200_DEV_WKUP_ESM0 esm_pls_event0 121
      J7200_DEV_WKUP_ESM0 esm_pls_event1 129
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 9 J7200_DEV_WKUP_ESM0 esm_pls_event2 137
      J7200_DEV_MCU_R5FSS0_CORE0 intr 133
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 9 J7200_DEV_MCU_R5FSS0_CORE1 intr 133
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 10 J7200_DEV_WKUP_ESM0 esm_pls_event0 122
      J7200_DEV_WKUP_ESM0 esm_pls_event1 130
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 10 J7200_DEV_WKUP_ESM0 esm_pls_event2 138
      J7200_DEV_MCU_R5FSS0_CORE0 intr 134
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 10 J7200_DEV_MCU_R5FSS0_CORE1 intr 134
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 11 J7200_DEV_WKUP_ESM0 esm_pls_event0 123
      J7200_DEV_WKUP_ESM0 esm_pls_event1 131
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 11 J7200_DEV_WKUP_ESM0 esm_pls_event2 139
      J7200_DEV_MCU_R5FSS0_CORE0 intr 135
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 11 J7200_DEV_MCU_R5FSS0_CORE1 intr 135
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 12 J7200_DEV_WKUP_ESM0 esm_pls_event0 124
      J7200_DEV_WKUP_ESM0 esm_pls_event1 132
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 12 J7200_DEV_WKUP_ESM0 esm_pls_event2 140
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 4
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 12 J7200_DEV_MCU_R5FSS0_CORE0 intr 136
      J7200_DEV_MCU_R5FSS0_CORE1 intr 136
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 13 J7200_DEV_WKUP_ESM0 esm_pls_event0 125
      J7200_DEV_WKUP_ESM0 esm_pls_event1 133
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 13 J7200_DEV_WKUP_ESM0 esm_pls_event2 141
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 5
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 13 J7200_DEV_MCU_R5FSS0_CORE0 intr 137
      J7200_DEV_MCU_R5FSS0_CORE1 intr 137
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 14 J7200_DEV_WKUP_ESM0 esm_pls_event0 126
      J7200_DEV_WKUP_ESM0 esm_pls_event1 134
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 14 J7200_DEV_WKUP_ESM0 esm_pls_event2 142
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 6
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 14 J7200_DEV_MCU_R5FSS0_CORE0 intr 138
      J7200_DEV_MCU_R5FSS0_CORE1 intr 138
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 15 J7200_DEV_WKUP_ESM0 esm_pls_event0 127
      J7200_DEV_WKUP_ESM0 esm_pls_event1 135
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 15 J7200_DEV_WKUP_ESM0 esm_pls_event2 143
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 7
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 15 J7200_DEV_MCU_R5FSS0_CORE0 intr 139
      J7200_DEV_MCU_R5FSS0_CORE1 intr 139
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 16 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 960
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 8
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 16 J7200_DEV_R5FSS0_CORE0 intr 488
      J7200_DEV_R5FSS0_CORE1 intr 488
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 17 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 961
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 9
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 17 J7200_DEV_R5FSS0_CORE0 intr 489
      J7200_DEV_R5FSS0_CORE1 intr 489
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 18 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 962
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 10
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 18 J7200_DEV_R5FSS0_CORE0 intr 490
      J7200_DEV_R5FSS0_CORE1 intr 490
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 19 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 963
      J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 11
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 19 J7200_DEV_R5FSS0_CORE0 intr 491
      J7200_DEV_R5FSS0_CORE1 intr 491
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 20 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 964
      J7200_DEV_R5FSS0_CORE0 intr 492
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 20 J7200_DEV_R5FSS0_CORE1 intr 492
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 21 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 965
      J7200_DEV_R5FSS0_CORE0 intr 493
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 21 J7200_DEV_R5FSS0_CORE1 intr 493
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 22 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 966
      J7200_DEV_R5FSS0_CORE0 intr 494
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 22 J7200_DEV_R5FSS0_CORE1 intr 494
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 23 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 967
      J7200_DEV_R5FSS0_CORE0 intr 495
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 23 J7200_DEV_R5FSS0_CORE1 intr 495
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 24 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 968
      J7200_DEV_R5FSS0_CORE0 intr 496
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 24 J7200_DEV_R5FSS0_CORE1 intr 496
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 25 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 969
      J7200_DEV_R5FSS0_CORE0 intr 497
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 25 J7200_DEV_R5FSS0_CORE1 intr 497
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 26 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 970
      J7200_DEV_R5FSS0_CORE0 intr 498
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 26 J7200_DEV_R5FSS0_CORE1 intr 498
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 27 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 971
      J7200_DEV_R5FSS0_CORE0 intr 499
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 27 J7200_DEV_R5FSS0_CORE1 intr 499
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 28 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 972
      J7200_DEV_R5FSS0_CORE0 intr 500
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 28 J7200_DEV_R5FSS0_CORE1 intr 500
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 29 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 973
      J7200_DEV_R5FSS0_CORE0 intr 501
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 29 J7200_DEV_R5FSS0_CORE1 intr 501
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 30 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 974
      J7200_DEV_R5FSS0_CORE0 intr 502
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 30 J7200_DEV_R5FSS0_CORE1 intr 502
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 31 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 975
      J7200_DEV_R5FSS0_CORE0 intr 503
J7200_DEV_WKUP_GPIOMUX_INTRTR0 137 31 J7200_DEV_R5FSS0_CORE1 intr 503

GPIOMUX_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_GPIOMUX_INTRTR0 131 0 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 1 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 2 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 3 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 4 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 5 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 6 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 7 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 8 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 9 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 10 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 11 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 12 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 13 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 14 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 15 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 16 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 17 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 18 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 19 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 20 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 21 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 22 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 23 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 24 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 25 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 26 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 27 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 28 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 29 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 30 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 31 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 32 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 33 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 34 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 35 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 36 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 37 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 38 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 39 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 40 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 41 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 42 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 43 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 44 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 45 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 46 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 47 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 48 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 49 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 50 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 51 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 52 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 53 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 54 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 55 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 56 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 57 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 58 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 59 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 60 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 61 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 62 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 63 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 64 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 65 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 66 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 67 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 68 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 69 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 70 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 71 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 72 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 73 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 74 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 75 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 76 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 77 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 78 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 79 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 80 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 81 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 82 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 83 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 84 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 85 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 86 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 87 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 88 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 89 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 90 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 91 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 92 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 93 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 94 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 95 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 96 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 97 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 98 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 99 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 100 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 101 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 102 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 103 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 104 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 105 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 106 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 107 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 108 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 109 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 110 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 111 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 112 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 113 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 114 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 115 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 116 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 117 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 118 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 119 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 120 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 121 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 122 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 123 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 124 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 125 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 126 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 127 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 128 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 129 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 130 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 131 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 132 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 133 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 134 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 135 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 136 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 137 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 138 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 139 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 140 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 141 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 142 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 143 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 144 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 145 J7200_DEV_GPIO0 gpio_bank 0
J7200_DEV_GPIOMUX_INTRTR0 131 146 J7200_DEV_GPIO0 gpio_bank 1
J7200_DEV_GPIOMUX_INTRTR0 131 147 J7200_DEV_GPIO0 gpio_bank 2
J7200_DEV_GPIOMUX_INTRTR0 131 148 J7200_DEV_GPIO0 gpio_bank 3
J7200_DEV_GPIOMUX_INTRTR0 131 149 J7200_DEV_GPIO0 gpio_bank 4
J7200_DEV_GPIOMUX_INTRTR0 131 150 J7200_DEV_GPIO0 gpio_bank 5
J7200_DEV_GPIOMUX_INTRTR0 131 151 J7200_DEV_GPIO0 gpio_bank 6
J7200_DEV_GPIOMUX_INTRTR0 131 152 J7200_DEV_GPIO0 gpio_bank 7
J7200_DEV_GPIOMUX_INTRTR0 131 153 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 154 J7200_DEV_GPIO2 gpio_bank 0
J7200_DEV_GPIOMUX_INTRTR0 131 155 J7200_DEV_GPIO2 gpio_bank 1
J7200_DEV_GPIOMUX_INTRTR0 131 156 J7200_DEV_GPIO2 gpio_bank 2
J7200_DEV_GPIOMUX_INTRTR0 131 157 J7200_DEV_GPIO2 gpio_bank 3
J7200_DEV_GPIOMUX_INTRTR0 131 158 J7200_DEV_GPIO2 gpio_bank 4
J7200_DEV_GPIOMUX_INTRTR0 131 159 J7200_DEV_GPIO2 gpio_bank 5
J7200_DEV_GPIOMUX_INTRTR0 131 160 J7200_DEV_GPIO2 gpio_bank 6
J7200_DEV_GPIOMUX_INTRTR0 131 161 J7200_DEV_GPIO2 gpio_bank 7
J7200_DEV_GPIOMUX_INTRTR0 131 162 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 163 J7200_DEV_GPIO4 gpio_bank 0
J7200_DEV_GPIOMUX_INTRTR0 131 164 J7200_DEV_GPIO4 gpio_bank 1
J7200_DEV_GPIOMUX_INTRTR0 131 165 J7200_DEV_GPIO4 gpio_bank 2
J7200_DEV_GPIOMUX_INTRTR0 131 166 J7200_DEV_GPIO4 gpio_bank 3
J7200_DEV_GPIOMUX_INTRTR0 131 167 J7200_DEV_GPIO4 gpio_bank 4
J7200_DEV_GPIOMUX_INTRTR0 131 168 J7200_DEV_GPIO4 gpio_bank 5
J7200_DEV_GPIOMUX_INTRTR0 131 169 J7200_DEV_GPIO4 gpio_bank 6
J7200_DEV_GPIOMUX_INTRTR0 131 170 J7200_DEV_GPIO4 gpio_bank 7
J7200_DEV_GPIOMUX_INTRTR0 131 171 Use TRM - Not managed by TISCI    
J7200_DEV_GPIOMUX_INTRTR0 131 172 J7200_DEV_GPIO6 gpio_bank 0
J7200_DEV_GPIOMUX_INTRTR0 131 173 J7200_DEV_GPIO6 gpio_bank 1
J7200_DEV_GPIOMUX_INTRTR0 131 174 J7200_DEV_GPIO6 gpio_bank 2
J7200_DEV_GPIOMUX_INTRTR0 131 175 J7200_DEV_GPIO6 gpio_bank 3
J7200_DEV_GPIOMUX_INTRTR0 131 176 J7200_DEV_GPIO6 gpio_bank 4
J7200_DEV_GPIOMUX_INTRTR0 131 177 J7200_DEV_GPIO6 gpio_bank 5
J7200_DEV_GPIOMUX_INTRTR0 131 178 J7200_DEV_GPIO6 gpio_bank 6
J7200_DEV_GPIOMUX_INTRTR0 131 179 J7200_DEV_GPIO6 gpio_bank 7

GPIOMUX_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_GPIOMUX_INTRTR0 131 0 J7200_DEV_ESM0 esm_pls_event0 632
      J7200_DEV_ESM0 esm_pls_event1 640
J7200_DEV_GPIOMUX_INTRTR0 131 0 J7200_DEV_ESM0 esm_pls_event2 648
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 64
J7200_DEV_GPIOMUX_INTRTR0 131 0 J7200_DEV_R5FSS0_CORE0 intr 396
      J7200_DEV_R5FSS0_CORE1 intr 396
J7200_DEV_GPIOMUX_INTRTR0 131 1 J7200_DEV_ESM0 esm_pls_event0 633
      J7200_DEV_ESM0 esm_pls_event1 641
J7200_DEV_GPIOMUX_INTRTR0 131 1 J7200_DEV_ESM0 esm_pls_event2 649
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 65
J7200_DEV_GPIOMUX_INTRTR0 131 1 J7200_DEV_R5FSS0_CORE0 intr 397
      J7200_DEV_R5FSS0_CORE1 intr 397
J7200_DEV_GPIOMUX_INTRTR0 131 2 J7200_DEV_ESM0 esm_pls_event0 634
      J7200_DEV_ESM0 esm_pls_event1 642
J7200_DEV_GPIOMUX_INTRTR0 131 2 J7200_DEV_ESM0 esm_pls_event2 650
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 66
J7200_DEV_GPIOMUX_INTRTR0 131 2 J7200_DEV_R5FSS0_CORE0 intr 398
      J7200_DEV_R5FSS0_CORE1 intr 398
J7200_DEV_GPIOMUX_INTRTR0 131 3 J7200_DEV_ESM0 esm_pls_event0 635
      J7200_DEV_ESM0 esm_pls_event1 643
J7200_DEV_GPIOMUX_INTRTR0 131 3 J7200_DEV_ESM0 esm_pls_event2 651
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 67
J7200_DEV_GPIOMUX_INTRTR0 131 3 J7200_DEV_R5FSS0_CORE0 intr 399
      J7200_DEV_R5FSS0_CORE1 intr 399
J7200_DEV_GPIOMUX_INTRTR0 131 4 J7200_DEV_ESM0 esm_pls_event0 636
      J7200_DEV_ESM0 esm_pls_event1 644
J7200_DEV_GPIOMUX_INTRTR0 131 4 J7200_DEV_ESM0 esm_pls_event2 652
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 68
J7200_DEV_GPIOMUX_INTRTR0 131 4 J7200_DEV_R5FSS0_CORE0 intr 400
      J7200_DEV_R5FSS0_CORE1 intr 400
J7200_DEV_GPIOMUX_INTRTR0 131 5 J7200_DEV_ESM0 esm_pls_event0 637
      J7200_DEV_ESM0 esm_pls_event1 645
J7200_DEV_GPIOMUX_INTRTR0 131 5 J7200_DEV_ESM0 esm_pls_event2 653
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 69
J7200_DEV_GPIOMUX_INTRTR0 131 5 J7200_DEV_R5FSS0_CORE0 intr 401
      J7200_DEV_R5FSS0_CORE1 intr 401
J7200_DEV_GPIOMUX_INTRTR0 131 6 J7200_DEV_ESM0 esm_pls_event0 638
      J7200_DEV_ESM0 esm_pls_event1 646
J7200_DEV_GPIOMUX_INTRTR0 131 6 J7200_DEV_ESM0 esm_pls_event2 654
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 70
J7200_DEV_GPIOMUX_INTRTR0 131 6 J7200_DEV_R5FSS0_CORE0 intr 402
      J7200_DEV_R5FSS0_CORE1 intr 402
J7200_DEV_GPIOMUX_INTRTR0 131 7 J7200_DEV_ESM0 esm_pls_event0 639
      J7200_DEV_ESM0 esm_pls_event1 647
J7200_DEV_GPIOMUX_INTRTR0 131 7 J7200_DEV_ESM0 esm_pls_event2 655
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 71
J7200_DEV_GPIOMUX_INTRTR0 131 7 J7200_DEV_R5FSS0_CORE0 intr 403
      J7200_DEV_R5FSS0_CORE1 intr 403
J7200_DEV_GPIOMUX_INTRTR0 131 8 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 392
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 72
J7200_DEV_GPIOMUX_INTRTR0 131 8 J7200_DEV_R5FSS0_CORE0 intr 404
      J7200_DEV_R5FSS0_CORE1 intr 404
J7200_DEV_GPIOMUX_INTRTR0 131 9 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 393
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 73
J7200_DEV_GPIOMUX_INTRTR0 131 9 J7200_DEV_R5FSS0_CORE0 intr 405
      J7200_DEV_R5FSS0_CORE1 intr 405
J7200_DEV_GPIOMUX_INTRTR0 131 10 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 394
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 74
J7200_DEV_GPIOMUX_INTRTR0 131 10 J7200_DEV_R5FSS0_CORE0 intr 406
      J7200_DEV_R5FSS0_CORE1 intr 406
J7200_DEV_GPIOMUX_INTRTR0 131 11 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 395
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 75
J7200_DEV_GPIOMUX_INTRTR0 131 11 J7200_DEV_R5FSS0_CORE0 intr 407
      J7200_DEV_R5FSS0_CORE1 intr 407
J7200_DEV_GPIOMUX_INTRTR0 131 12 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 396
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 76
J7200_DEV_GPIOMUX_INTRTR0 131 12 J7200_DEV_R5FSS0_CORE0 intr 408
      J7200_DEV_R5FSS0_CORE1 intr 408
J7200_DEV_GPIOMUX_INTRTR0 131 13 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 397
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 77
J7200_DEV_GPIOMUX_INTRTR0 131 13 J7200_DEV_R5FSS0_CORE0 intr 409
      J7200_DEV_R5FSS0_CORE1 intr 409
J7200_DEV_GPIOMUX_INTRTR0 131 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 398
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 78
J7200_DEV_GPIOMUX_INTRTR0 131 14 J7200_DEV_R5FSS0_CORE0 intr 410
      J7200_DEV_R5FSS0_CORE1 intr 410
J7200_DEV_GPIOMUX_INTRTR0 131 15 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 399
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 79
J7200_DEV_GPIOMUX_INTRTR0 131 15 J7200_DEV_R5FSS0_CORE0 intr 411
      J7200_DEV_R5FSS0_CORE1 intr 411
J7200_DEV_GPIOMUX_INTRTR0 131 16 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 400
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 80
J7200_DEV_GPIOMUX_INTRTR0 131 16 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 68
      J7200_DEV_R5FSS0_CORE0 intr 176
J7200_DEV_GPIOMUX_INTRTR0 131 16 J7200_DEV_R5FSS0_CORE1 intr 176
J7200_DEV_GPIOMUX_INTRTR0 131 17 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 401
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 81
J7200_DEV_GPIOMUX_INTRTR0 131 17 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 69
      J7200_DEV_R5FSS0_CORE0 intr 177
J7200_DEV_GPIOMUX_INTRTR0 131 17 J7200_DEV_R5FSS0_CORE1 intr 177
J7200_DEV_GPIOMUX_INTRTR0 131 18 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 402
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 82
J7200_DEV_GPIOMUX_INTRTR0 131 18 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 70
      J7200_DEV_R5FSS0_CORE0 intr 178
J7200_DEV_GPIOMUX_INTRTR0 131 18 J7200_DEV_R5FSS0_CORE1 intr 178
J7200_DEV_GPIOMUX_INTRTR0 131 19 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 403
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 83
J7200_DEV_GPIOMUX_INTRTR0 131 19 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 71
      J7200_DEV_R5FSS0_CORE0 intr 179
J7200_DEV_GPIOMUX_INTRTR0 131 19 J7200_DEV_R5FSS0_CORE1 intr 179
J7200_DEV_GPIOMUX_INTRTR0 131 20 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 404
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 84
J7200_DEV_GPIOMUX_INTRTR0 131 20 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 72
      J7200_DEV_R5FSS0_CORE0 intr 180
J7200_DEV_GPIOMUX_INTRTR0 131 20 J7200_DEV_R5FSS0_CORE1 intr 180
J7200_DEV_GPIOMUX_INTRTR0 131 21 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 405
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 85
J7200_DEV_GPIOMUX_INTRTR0 131 21 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 73
      J7200_DEV_R5FSS0_CORE0 intr 181
J7200_DEV_GPIOMUX_INTRTR0 131 21 J7200_DEV_R5FSS0_CORE1 intr 181
J7200_DEV_GPIOMUX_INTRTR0 131 22 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 406
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 86
J7200_DEV_GPIOMUX_INTRTR0 131 22 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 74
      J7200_DEV_R5FSS0_CORE0 intr 182
J7200_DEV_GPIOMUX_INTRTR0 131 22 J7200_DEV_R5FSS0_CORE1 intr 182
J7200_DEV_GPIOMUX_INTRTR0 131 23 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 407
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 87
J7200_DEV_GPIOMUX_INTRTR0 131 23 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 75
      J7200_DEV_R5FSS0_CORE0 intr 183
J7200_DEV_GPIOMUX_INTRTR0 131 23 J7200_DEV_R5FSS0_CORE1 intr 183
J7200_DEV_GPIOMUX_INTRTR0 131 24 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 408
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 88
J7200_DEV_GPIOMUX_INTRTR0 131 24 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 76
      J7200_DEV_R5FSS0_CORE0 intr 184
J7200_DEV_GPIOMUX_INTRTR0 131 24 J7200_DEV_R5FSS0_CORE1 intr 184
J7200_DEV_GPIOMUX_INTRTR0 131 25 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 409
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 89
J7200_DEV_GPIOMUX_INTRTR0 131 25 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 77
      J7200_DEV_R5FSS0_CORE0 intr 185
J7200_DEV_GPIOMUX_INTRTR0 131 25 J7200_DEV_R5FSS0_CORE1 intr 185
J7200_DEV_GPIOMUX_INTRTR0 131 26 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 410
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 90
J7200_DEV_GPIOMUX_INTRTR0 131 26 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 78
      J7200_DEV_R5FSS0_CORE0 intr 186
J7200_DEV_GPIOMUX_INTRTR0 131 26 J7200_DEV_R5FSS0_CORE1 intr 186
J7200_DEV_GPIOMUX_INTRTR0 131 27 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 411
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 91
J7200_DEV_GPIOMUX_INTRTR0 131 27 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 79
      J7200_DEV_R5FSS0_CORE0 intr 187
J7200_DEV_GPIOMUX_INTRTR0 131 27 J7200_DEV_R5FSS0_CORE1 intr 187
J7200_DEV_GPIOMUX_INTRTR0 131 28 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 412
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 92
J7200_DEV_GPIOMUX_INTRTR0 131 28 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 80
      J7200_DEV_R5FSS0_CORE0 intr 188
J7200_DEV_GPIOMUX_INTRTR0 131 28 J7200_DEV_R5FSS0_CORE1 intr 188
J7200_DEV_GPIOMUX_INTRTR0 131 29 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 413
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 93
J7200_DEV_GPIOMUX_INTRTR0 131 29 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 81
      J7200_DEV_R5FSS0_CORE0 intr 189
J7200_DEV_GPIOMUX_INTRTR0 131 29 J7200_DEV_R5FSS0_CORE1 intr 189
J7200_DEV_GPIOMUX_INTRTR0 131 30 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 414
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 94
J7200_DEV_GPIOMUX_INTRTR0 131 30 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 82
      J7200_DEV_R5FSS0_CORE0 intr 190
J7200_DEV_GPIOMUX_INTRTR0 131 30 J7200_DEV_R5FSS0_CORE1 intr 190
J7200_DEV_GPIOMUX_INTRTR0 131 31 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 415
      J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 95
J7200_DEV_GPIOMUX_INTRTR0 131 31 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 83
      J7200_DEV_R5FSS0_CORE0 intr 191
J7200_DEV_GPIOMUX_INTRTR0 131 31 J7200_DEV_R5FSS0_CORE1 intr 191
J7200_DEV_GPIOMUX_INTRTR0 131 32 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 416
J7200_DEV_GPIOMUX_INTRTR0 131 33 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 417
J7200_DEV_GPIOMUX_INTRTR0 131 34 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 418
J7200_DEV_GPIOMUX_INTRTR0 131 35 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 419
J7200_DEV_GPIOMUX_INTRTR0 131 36 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 420
J7200_DEV_GPIOMUX_INTRTR0 131 37 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 421
J7200_DEV_GPIOMUX_INTRTR0 131 38 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 422
J7200_DEV_GPIOMUX_INTRTR0 131 39 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 423
J7200_DEV_GPIOMUX_INTRTR0 131 40 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 424
J7200_DEV_GPIOMUX_INTRTR0 131 41 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 425
J7200_DEV_GPIOMUX_INTRTR0 131 42 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 426
J7200_DEV_GPIOMUX_INTRTR0 131 43 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 427
J7200_DEV_GPIOMUX_INTRTR0 131 44 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 428
J7200_DEV_GPIOMUX_INTRTR0 131 45 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 429
J7200_DEV_GPIOMUX_INTRTR0 131 46 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 430
J7200_DEV_GPIOMUX_INTRTR0 131 47 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 431
J7200_DEV_GPIOMUX_INTRTR0 131 48 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 432
J7200_DEV_GPIOMUX_INTRTR0 131 49 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 433
J7200_DEV_GPIOMUX_INTRTR0 131 50 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 434
J7200_DEV_GPIOMUX_INTRTR0 131 51 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 435
J7200_DEV_GPIOMUX_INTRTR0 131 52 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 436
J7200_DEV_GPIOMUX_INTRTR0 131 53 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 437
J7200_DEV_GPIOMUX_INTRTR0 131 54 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 438
J7200_DEV_GPIOMUX_INTRTR0 131 55 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 439
J7200_DEV_GPIOMUX_INTRTR0 131 56 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 440
J7200_DEV_GPIOMUX_INTRTR0 131 57 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 441
J7200_DEV_GPIOMUX_INTRTR0 131 58 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 442
J7200_DEV_GPIOMUX_INTRTR0 131 59 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 443
J7200_DEV_GPIOMUX_INTRTR0 131 60 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 444
J7200_DEV_GPIOMUX_INTRTR0 131 61 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 445
J7200_DEV_GPIOMUX_INTRTR0 131 62 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 446
J7200_DEV_GPIOMUX_INTRTR0 131 63 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 447

CMPEVENT_INTRTR0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_CMPEVENT_INTRTR0 123 0 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 1 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 2 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 3 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 4 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 5 J7200_DEV_PCIE1 pcie_cpts_comp 0
J7200_DEV_CMPEVENT_INTRTR0 123 6 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 7 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 8 J7200_DEV_NAVSS0 cpts0_comp 0
J7200_DEV_CMPEVENT_INTRTR0 123 9 J7200_DEV_CPSW0 cpts_comp 0
J7200_DEV_CMPEVENT_INTRTR0 123 10 J7200_DEV_MCU_CPSW0 cpts_comp 0
J7200_DEV_CMPEVENT_INTRTR0 123 11 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 12 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 13 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 14 Use TRM - Not managed by TISCI    
J7200_DEV_CMPEVENT_INTRTR0 123 15 Use TRM - Not managed by TISCI    

CMPEVENT_INTRTR0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_CMPEVENT_INTRTR0 123 0 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 544
J7200_DEV_CMPEVENT_INTRTR0 123 1 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 545
J7200_DEV_CMPEVENT_INTRTR0 123 2 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 546
J7200_DEV_CMPEVENT_INTRTR0 123 3 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS spi 547
J7200_DEV_CMPEVENT_INTRTR0 123 4 J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 96
J7200_DEV_CMPEVENT_INTRTR0 123 5 J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 97
J7200_DEV_CMPEVENT_INTRTR0 123 6 J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 98
J7200_DEV_CMPEVENT_INTRTR0 123 7 J7200_DEV_MAIN2MCU_PLS_INTRTR0 in 99
J7200_DEV_CMPEVENT_INTRTR0 123 8 J7200_DEV_R5FSS0_CORE0 intr 326
      J7200_DEV_R5FSS0_CORE1 intr 326
J7200_DEV_CMPEVENT_INTRTR0 123 9 J7200_DEV_R5FSS0_CORE0 intr 327
      J7200_DEV_R5FSS0_CORE1 intr 327
J7200_DEV_CMPEVENT_INTRTR0 123 10 J7200_DEV_R5FSS0_CORE0 intr 328
      J7200_DEV_R5FSS0_CORE1 intr 328
J7200_DEV_CMPEVENT_INTRTR0 123 11 J7200_DEV_R5FSS0_CORE0 intr 329
      J7200_DEV_R5FSS0_CORE1 intr 329
J7200_DEV_CMPEVENT_INTRTR0 123 12 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 60
J7200_DEV_CMPEVENT_INTRTR0 123 13 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 61
J7200_DEV_CMPEVENT_INTRTR0 123 14 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 62
J7200_DEV_CMPEVENT_INTRTR0 123 15 J7200_DEV_NAVSS0_UDMASS_INTA_0 intaggr_levi_pend 63

MCU_NAVSS0_INTR_0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 0 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 0
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 1 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 1
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 2 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 2
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 3 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 3
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 4 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 4
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 5 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 5
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 6 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 6
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 7 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 7
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 8 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 8
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 9 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 9
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 10 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 10
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 11 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 11
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 12 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 12
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 13 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 13
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 14 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 14
J7200_DEV_MCU_NAVSS0_INTR_0 237 15 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 15
J7200_DEV_MCU_NAVSS0_INTR_0 237 16 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 16
J7200_DEV_MCU_NAVSS0_INTR_0 237 17 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 17
J7200_DEV_MCU_NAVSS0_INTR_0 237 18 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 18
J7200_DEV_MCU_NAVSS0_INTR_0 237 19 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 19
J7200_DEV_MCU_NAVSS0_INTR_0 237 20 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 20
J7200_DEV_MCU_NAVSS0_INTR_0 237 21 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 21
J7200_DEV_MCU_NAVSS0_INTR_0 237 22 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 22
J7200_DEV_MCU_NAVSS0_INTR_0 237 23 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 23
J7200_DEV_MCU_NAVSS0_INTR_0 237 24 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 24
J7200_DEV_MCU_NAVSS0_INTR_0 237 25 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 25
J7200_DEV_MCU_NAVSS0_INTR_0 237 26 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 26
J7200_DEV_MCU_NAVSS0_INTR_0 237 27 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 27
J7200_DEV_MCU_NAVSS0_INTR_0 237 28 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 28
J7200_DEV_MCU_NAVSS0_INTR_0 237 29 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 29
J7200_DEV_MCU_NAVSS0_INTR_0 237 30 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 30
J7200_DEV_MCU_NAVSS0_INTR_0 237 31 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 31
J7200_DEV_MCU_NAVSS0_INTR_0 237 32 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 32
J7200_DEV_MCU_NAVSS0_INTR_0 237 33 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 33
J7200_DEV_MCU_NAVSS0_INTR_0 237 34 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 34
J7200_DEV_MCU_NAVSS0_INTR_0 237 35 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 35
J7200_DEV_MCU_NAVSS0_INTR_0 237 36 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 36
J7200_DEV_MCU_NAVSS0_INTR_0 237 37 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 37
J7200_DEV_MCU_NAVSS0_INTR_0 237 38 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 38
J7200_DEV_MCU_NAVSS0_INTR_0 237 39 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 39
J7200_DEV_MCU_NAVSS0_INTR_0 237 40 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 40
J7200_DEV_MCU_NAVSS0_INTR_0 237 41 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 41
J7200_DEV_MCU_NAVSS0_INTR_0 237 42 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 42
J7200_DEV_MCU_NAVSS0_INTR_0 237 43 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 43
J7200_DEV_MCU_NAVSS0_INTR_0 237 44 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 44
J7200_DEV_MCU_NAVSS0_INTR_0 237 45 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 45
J7200_DEV_MCU_NAVSS0_INTR_0 237 46 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 46
J7200_DEV_MCU_NAVSS0_INTR_0 237 47 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 47
J7200_DEV_MCU_NAVSS0_INTR_0 237 48 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 48
J7200_DEV_MCU_NAVSS0_INTR_0 237 49 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 49
J7200_DEV_MCU_NAVSS0_INTR_0 237 50 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 50
J7200_DEV_MCU_NAVSS0_INTR_0 237 51 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 51
J7200_DEV_MCU_NAVSS0_INTR_0 237 52 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 52
J7200_DEV_MCU_NAVSS0_INTR_0 237 53 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 53
J7200_DEV_MCU_NAVSS0_INTR_0 237 54 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 54
J7200_DEV_MCU_NAVSS0_INTR_0 237 55 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 55
J7200_DEV_MCU_NAVSS0_INTR_0 237 56 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 56
J7200_DEV_MCU_NAVSS0_INTR_0 237 57 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 57
J7200_DEV_MCU_NAVSS0_INTR_0 237 58 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 58
J7200_DEV_MCU_NAVSS0_INTR_0 237 59 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 59
J7200_DEV_MCU_NAVSS0_INTR_0 237 60 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 60
J7200_DEV_MCU_NAVSS0_INTR_0 237 61 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 61
J7200_DEV_MCU_NAVSS0_INTR_0 237 62 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 62
J7200_DEV_MCU_NAVSS0_INTR_0 237 63 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 63
J7200_DEV_MCU_NAVSS0_INTR_0 237 64 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 64
J7200_DEV_MCU_NAVSS0_INTR_0 237 65 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 65
J7200_DEV_MCU_NAVSS0_INTR_0 237 66 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 66
J7200_DEV_MCU_NAVSS0_INTR_0 237 67 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 67
J7200_DEV_MCU_NAVSS0_INTR_0 237 68 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 68
J7200_DEV_MCU_NAVSS0_INTR_0 237 69 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 69
J7200_DEV_MCU_NAVSS0_INTR_0 237 70 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 70
J7200_DEV_MCU_NAVSS0_INTR_0 237 71 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 71
J7200_DEV_MCU_NAVSS0_INTR_0 237 72 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 72
J7200_DEV_MCU_NAVSS0_INTR_0 237 73 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 73
J7200_DEV_MCU_NAVSS0_INTR_0 237 74 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 74
J7200_DEV_MCU_NAVSS0_INTR_0 237 75 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 75
J7200_DEV_MCU_NAVSS0_INTR_0 237 76 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 76
J7200_DEV_MCU_NAVSS0_INTR_0 237 77 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 77
J7200_DEV_MCU_NAVSS0_INTR_0 237 78 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 78
J7200_DEV_MCU_NAVSS0_INTR_0 237 79 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 79
J7200_DEV_MCU_NAVSS0_INTR_0 237 80 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 80
J7200_DEV_MCU_NAVSS0_INTR_0 237 81 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 81
J7200_DEV_MCU_NAVSS0_INTR_0 237 82 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 82
J7200_DEV_MCU_NAVSS0_INTR_0 237 83 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 83
J7200_DEV_MCU_NAVSS0_INTR_0 237 84 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 84
J7200_DEV_MCU_NAVSS0_INTR_0 237 85 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 85
J7200_DEV_MCU_NAVSS0_INTR_0 237 86 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 86
J7200_DEV_MCU_NAVSS0_INTR_0 237 87 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 87
J7200_DEV_MCU_NAVSS0_INTR_0 237 88 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 88
J7200_DEV_MCU_NAVSS0_INTR_0 237 89 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 89
J7200_DEV_MCU_NAVSS0_INTR_0 237 90 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 90
J7200_DEV_MCU_NAVSS0_INTR_0 237 91 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 91
J7200_DEV_MCU_NAVSS0_INTR_0 237 92 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 92
J7200_DEV_MCU_NAVSS0_INTR_0 237 93 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 93
J7200_DEV_MCU_NAVSS0_INTR_0 237 94 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 94
J7200_DEV_MCU_NAVSS0_INTR_0 237 95 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 95
J7200_DEV_MCU_NAVSS0_INTR_0 237 96 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 96
J7200_DEV_MCU_NAVSS0_INTR_0 237 97 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 97
J7200_DEV_MCU_NAVSS0_INTR_0 237 98 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 98
J7200_DEV_MCU_NAVSS0_INTR_0 237 99 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 99
J7200_DEV_MCU_NAVSS0_INTR_0 237 100 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 100
J7200_DEV_MCU_NAVSS0_INTR_0 237 101 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 101
J7200_DEV_MCU_NAVSS0_INTR_0 237 102 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 102
J7200_DEV_MCU_NAVSS0_INTR_0 237 103 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 103
J7200_DEV_MCU_NAVSS0_INTR_0 237 104 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 104
J7200_DEV_MCU_NAVSS0_INTR_0 237 105 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 105
J7200_DEV_MCU_NAVSS0_INTR_0 237 106 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 106
J7200_DEV_MCU_NAVSS0_INTR_0 237 107 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 107
J7200_DEV_MCU_NAVSS0_INTR_0 237 108 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 108
J7200_DEV_MCU_NAVSS0_INTR_0 237 109 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 109
J7200_DEV_MCU_NAVSS0_INTR_0 237 110 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 110
J7200_DEV_MCU_NAVSS0_INTR_0 237 111 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 111
J7200_DEV_MCU_NAVSS0_INTR_0 237 112 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 112
J7200_DEV_MCU_NAVSS0_INTR_0 237 113 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 113
J7200_DEV_MCU_NAVSS0_INTR_0 237 114 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 114
J7200_DEV_MCU_NAVSS0_INTR_0 237 115 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 115
J7200_DEV_MCU_NAVSS0_INTR_0 237 116 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 116
J7200_DEV_MCU_NAVSS0_INTR_0 237 117 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 117
J7200_DEV_MCU_NAVSS0_INTR_0 237 118 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 118
J7200_DEV_MCU_NAVSS0_INTR_0 237 119 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 119
J7200_DEV_MCU_NAVSS0_INTR_0 237 120 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 120
J7200_DEV_MCU_NAVSS0_INTR_0 237 121 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 121
J7200_DEV_MCU_NAVSS0_INTR_0 237 122 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 122
J7200_DEV_MCU_NAVSS0_INTR_0 237 123 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 123
J7200_DEV_MCU_NAVSS0_INTR_0 237 124 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 124
J7200_DEV_MCU_NAVSS0_INTR_0 237 125 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 125
J7200_DEV_MCU_NAVSS0_INTR_0 237 126 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 126
J7200_DEV_MCU_NAVSS0_INTR_0 237 127 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 127
J7200_DEV_MCU_NAVSS0_INTR_0 237 128 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 128
J7200_DEV_MCU_NAVSS0_INTR_0 237 129 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 129
J7200_DEV_MCU_NAVSS0_INTR_0 237 130 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 130
J7200_DEV_MCU_NAVSS0_INTR_0 237 131 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 131
J7200_DEV_MCU_NAVSS0_INTR_0 237 132 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 132
J7200_DEV_MCU_NAVSS0_INTR_0 237 133 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 133
J7200_DEV_MCU_NAVSS0_INTR_0 237 134 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 134
J7200_DEV_MCU_NAVSS0_INTR_0 237 135 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 135
J7200_DEV_MCU_NAVSS0_INTR_0 237 136 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 136
J7200_DEV_MCU_NAVSS0_INTR_0 237 137 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 137
J7200_DEV_MCU_NAVSS0_INTR_0 237 138 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 138
J7200_DEV_MCU_NAVSS0_INTR_0 237 139 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 139
J7200_DEV_MCU_NAVSS0_INTR_0 237 140 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 140
J7200_DEV_MCU_NAVSS0_INTR_0 237 141 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 141
J7200_DEV_MCU_NAVSS0_INTR_0 237 142 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 142
J7200_DEV_MCU_NAVSS0_INTR_0 237 143 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 143
J7200_DEV_MCU_NAVSS0_INTR_0 237 144 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 144
J7200_DEV_MCU_NAVSS0_INTR_0 237 145 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 145
J7200_DEV_MCU_NAVSS0_INTR_0 237 146 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 146
J7200_DEV_MCU_NAVSS0_INTR_0 237 147 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 147
J7200_DEV_MCU_NAVSS0_INTR_0 237 148 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 148
J7200_DEV_MCU_NAVSS0_INTR_0 237 149 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 149
J7200_DEV_MCU_NAVSS0_INTR_0 237 150 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 150
J7200_DEV_MCU_NAVSS0_INTR_0 237 151 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 151
J7200_DEV_MCU_NAVSS0_INTR_0 237 152 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 152
J7200_DEV_MCU_NAVSS0_INTR_0 237 153 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 153
J7200_DEV_MCU_NAVSS0_INTR_0 237 154 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 154
J7200_DEV_MCU_NAVSS0_INTR_0 237 155 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 155
J7200_DEV_MCU_NAVSS0_INTR_0 237 156 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 156
J7200_DEV_MCU_NAVSS0_INTR_0 237 157 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 157
J7200_DEV_MCU_NAVSS0_INTR_0 237 158 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 158
J7200_DEV_MCU_NAVSS0_INTR_0 237 159 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 159
J7200_DEV_MCU_NAVSS0_INTR_0 237 160 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 160
J7200_DEV_MCU_NAVSS0_INTR_0 237 161 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 161
J7200_DEV_MCU_NAVSS0_INTR_0 237 162 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 162
J7200_DEV_MCU_NAVSS0_INTR_0 237 163 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 163
J7200_DEV_MCU_NAVSS0_INTR_0 237 164 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 164
J7200_DEV_MCU_NAVSS0_INTR_0 237 165 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 165
J7200_DEV_MCU_NAVSS0_INTR_0 237 166 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 166
J7200_DEV_MCU_NAVSS0_INTR_0 237 167 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 167
J7200_DEV_MCU_NAVSS0_INTR_0 237 168 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 168
J7200_DEV_MCU_NAVSS0_INTR_0 237 169 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 169
J7200_DEV_MCU_NAVSS0_INTR_0 237 170 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 170
J7200_DEV_MCU_NAVSS0_INTR_0 237 171 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 171
J7200_DEV_MCU_NAVSS0_INTR_0 237 172 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 172
J7200_DEV_MCU_NAVSS0_INTR_0 237 173 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 173
J7200_DEV_MCU_NAVSS0_INTR_0 237 174 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 174
J7200_DEV_MCU_NAVSS0_INTR_0 237 175 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 175
J7200_DEV_MCU_NAVSS0_INTR_0 237 176 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 176
J7200_DEV_MCU_NAVSS0_INTR_0 237 177 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 177
J7200_DEV_MCU_NAVSS0_INTR_0 237 178 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 178
J7200_DEV_MCU_NAVSS0_INTR_0 237 179 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 179
J7200_DEV_MCU_NAVSS0_INTR_0 237 180 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 180
J7200_DEV_MCU_NAVSS0_INTR_0 237 181 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 181
J7200_DEV_MCU_NAVSS0_INTR_0 237 182 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 182
J7200_DEV_MCU_NAVSS0_INTR_0 237 183 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 183
J7200_DEV_MCU_NAVSS0_INTR_0 237 184 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 184
J7200_DEV_MCU_NAVSS0_INTR_0 237 185 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 185
J7200_DEV_MCU_NAVSS0_INTR_0 237 186 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 186
J7200_DEV_MCU_NAVSS0_INTR_0 237 187 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 187
J7200_DEV_MCU_NAVSS0_INTR_0 237 188 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 188
J7200_DEV_MCU_NAVSS0_INTR_0 237 189 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 189
J7200_DEV_MCU_NAVSS0_INTR_0 237 190 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 190
J7200_DEV_MCU_NAVSS0_INTR_0 237 191 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 191
J7200_DEV_MCU_NAVSS0_INTR_0 237 192 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 192
J7200_DEV_MCU_NAVSS0_INTR_0 237 193 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 193
J7200_DEV_MCU_NAVSS0_INTR_0 237 194 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 194
J7200_DEV_MCU_NAVSS0_INTR_0 237 195 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 195
J7200_DEV_MCU_NAVSS0_INTR_0 237 196 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 196
J7200_DEV_MCU_NAVSS0_INTR_0 237 197 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 197
J7200_DEV_MCU_NAVSS0_INTR_0 237 198 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 198
J7200_DEV_MCU_NAVSS0_INTR_0 237 199 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 199
J7200_DEV_MCU_NAVSS0_INTR_0 237 200 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 200
J7200_DEV_MCU_NAVSS0_INTR_0 237 201 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 201
J7200_DEV_MCU_NAVSS0_INTR_0 237 202 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 202
J7200_DEV_MCU_NAVSS0_INTR_0 237 203 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 203
J7200_DEV_MCU_NAVSS0_INTR_0 237 204 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 204
J7200_DEV_MCU_NAVSS0_INTR_0 237 205 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 205
J7200_DEV_MCU_NAVSS0_INTR_0 237 206 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 206
J7200_DEV_MCU_NAVSS0_INTR_0 237 207 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 207
J7200_DEV_MCU_NAVSS0_INTR_0 237 208 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 208
J7200_DEV_MCU_NAVSS0_INTR_0 237 209 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 209
J7200_DEV_MCU_NAVSS0_INTR_0 237 210 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 210
J7200_DEV_MCU_NAVSS0_INTR_0 237 211 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 211
J7200_DEV_MCU_NAVSS0_INTR_0 237 212 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 212
J7200_DEV_MCU_NAVSS0_INTR_0 237 213 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 213
J7200_DEV_MCU_NAVSS0_INTR_0 237 214 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 214
J7200_DEV_MCU_NAVSS0_INTR_0 237 215 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 215
J7200_DEV_MCU_NAVSS0_INTR_0 237 216 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 216
J7200_DEV_MCU_NAVSS0_INTR_0 237 217 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 217
J7200_DEV_MCU_NAVSS0_INTR_0 237 218 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 218
J7200_DEV_MCU_NAVSS0_INTR_0 237 219 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 219
J7200_DEV_MCU_NAVSS0_INTR_0 237 220 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 220
J7200_DEV_MCU_NAVSS0_INTR_0 237 221 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 221
J7200_DEV_MCU_NAVSS0_INTR_0 237 222 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 222
J7200_DEV_MCU_NAVSS0_INTR_0 237 223 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 223
J7200_DEV_MCU_NAVSS0_INTR_0 237 224 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 224
J7200_DEV_MCU_NAVSS0_INTR_0 237 225 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 225
J7200_DEV_MCU_NAVSS0_INTR_0 237 226 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 226
J7200_DEV_MCU_NAVSS0_INTR_0 237 227 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 227
J7200_DEV_MCU_NAVSS0_INTR_0 237 228 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 228
J7200_DEV_MCU_NAVSS0_INTR_0 237 229 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 229
J7200_DEV_MCU_NAVSS0_INTR_0 237 230 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 230
J7200_DEV_MCU_NAVSS0_INTR_0 237 231 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 231
J7200_DEV_MCU_NAVSS0_INTR_0 237 232 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 232
J7200_DEV_MCU_NAVSS0_INTR_0 237 233 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 233
J7200_DEV_MCU_NAVSS0_INTR_0 237 234 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 234
J7200_DEV_MCU_NAVSS0_INTR_0 237 235 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 235
J7200_DEV_MCU_NAVSS0_INTR_0 237 236 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 236
J7200_DEV_MCU_NAVSS0_INTR_0 237 237 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 237
J7200_DEV_MCU_NAVSS0_INTR_0 237 238 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 238
J7200_DEV_MCU_NAVSS0_INTR_0 237 239 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 239
J7200_DEV_MCU_NAVSS0_INTR_0 237 240 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 240
J7200_DEV_MCU_NAVSS0_INTR_0 237 241 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 241
J7200_DEV_MCU_NAVSS0_INTR_0 237 242 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 242
J7200_DEV_MCU_NAVSS0_INTR_0 237 243 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 243
J7200_DEV_MCU_NAVSS0_INTR_0 237 244 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 244
J7200_DEV_MCU_NAVSS0_INTR_0 237 245 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 245
J7200_DEV_MCU_NAVSS0_INTR_0 237 246 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 246
J7200_DEV_MCU_NAVSS0_INTR_0 237 247 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 247
J7200_DEV_MCU_NAVSS0_INTR_0 237 248 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 248
J7200_DEV_MCU_NAVSS0_INTR_0 237 249 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 249
J7200_DEV_MCU_NAVSS0_INTR_0 237 250 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 250
J7200_DEV_MCU_NAVSS0_INTR_0 237 251 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 251
J7200_DEV_MCU_NAVSS0_INTR_0 237 252 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 252
J7200_DEV_MCU_NAVSS0_INTR_0 237 253 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 253
J7200_DEV_MCU_NAVSS0_INTR_0 237 254 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 254
J7200_DEV_MCU_NAVSS0_INTR_0 237 255 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 intaggr_vintr_pend 255
J7200_DEV_MCU_NAVSS0_INTR_0 237 256 J7200_DEV_MCU_NAVSS0_MCRC_0 dma_event_intr 0
J7200_DEV_MCU_NAVSS0_INTR_0 237 257 J7200_DEV_MCU_NAVSS0_MCRC_0 dma_event_intr 1
J7200_DEV_MCU_NAVSS0_INTR_0 237 258 J7200_DEV_MCU_NAVSS0_MCRC_0 dma_event_intr 2
J7200_DEV_MCU_NAVSS0_INTR_0 237 259 J7200_DEV_MCU_NAVSS0_MCRC_0 dma_event_intr 3
J7200_DEV_MCU_NAVSS0_INTR_0 237 260 J7200_DEV_MCU_NAVSS0_MCRC_0 intaggr_vintr_pend 4

MCU_NAVSS0_INTR_0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 0 J7200_DEV_MCU_R5FSS0_CORE0 intr 64
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 1 J7200_DEV_MCU_R5FSS0_CORE0 intr 65
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 2 J7200_DEV_MCU_R5FSS0_CORE0 intr 66
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 3 J7200_DEV_MCU_R5FSS0_CORE0 intr 67
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 4 J7200_DEV_MCU_R5FSS0_CORE0 intr 68
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 5 J7200_DEV_MCU_R5FSS0_CORE0 intr 69
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 6 J7200_DEV_MCU_R5FSS0_CORE0 intr 70
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 7 J7200_DEV_MCU_R5FSS0_CORE0 intr 71
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 8 J7200_DEV_MCU_R5FSS0_CORE0 intr 72
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 9 J7200_DEV_MCU_R5FSS0_CORE0 intr 73
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 10 J7200_DEV_MCU_R5FSS0_CORE0 intr 74
J7200_DEV_MCU_NAVSS0_INTR_0 237 11 J7200_DEV_MCU_R5FSS0_CORE0 intr 75
J7200_DEV_MCU_NAVSS0_INTR_0 237 12 J7200_DEV_MCU_R5FSS0_CORE0 intr 76
J7200_DEV_MCU_NAVSS0_INTR_0 237 13 J7200_DEV_MCU_R5FSS0_CORE0 intr 77
J7200_DEV_MCU_NAVSS0_INTR_0 237 14 J7200_DEV_MCU_R5FSS0_CORE0 intr 78
J7200_DEV_MCU_NAVSS0_INTR_0 237 15 J7200_DEV_MCU_R5FSS0_CORE0 intr 79
J7200_DEV_MCU_NAVSS0_INTR_0 237 16 J7200_DEV_MCU_R5FSS0_CORE0 intr 80
J7200_DEV_MCU_NAVSS0_INTR_0 237 17 J7200_DEV_MCU_R5FSS0_CORE0 intr 81
J7200_DEV_MCU_NAVSS0_INTR_0 237 18 J7200_DEV_MCU_R5FSS0_CORE0 intr 82
J7200_DEV_MCU_NAVSS0_INTR_0 237 19 J7200_DEV_MCU_R5FSS0_CORE0 intr 83
J7200_DEV_MCU_NAVSS0_INTR_0 237 20 J7200_DEV_MCU_R5FSS0_CORE0 intr 84
J7200_DEV_MCU_NAVSS0_INTR_0 237 21 J7200_DEV_MCU_R5FSS0_CORE0 intr 85
J7200_DEV_MCU_NAVSS0_INTR_0 237 22 J7200_DEV_MCU_R5FSS0_CORE0 intr 86
J7200_DEV_MCU_NAVSS0_INTR_0 237 23 J7200_DEV_MCU_R5FSS0_CORE0 intr 87
J7200_DEV_MCU_NAVSS0_INTR_0 237 24 J7200_DEV_MCU_R5FSS0_CORE0 intr 88
J7200_DEV_MCU_NAVSS0_INTR_0 237 25 J7200_DEV_MCU_R5FSS0_CORE0 intr 89
J7200_DEV_MCU_NAVSS0_INTR_0 237 26 J7200_DEV_MCU_R5FSS0_CORE0 intr 90
J7200_DEV_MCU_NAVSS0_INTR_0 237 27 J7200_DEV_MCU_R5FSS0_CORE0 intr 91
J7200_DEV_MCU_NAVSS0_INTR_0 237 28 J7200_DEV_MCU_R5FSS0_CORE0 intr 92
J7200_DEV_MCU_NAVSS0_INTR_0 237 29 J7200_DEV_MCU_R5FSS0_CORE0 intr 93
J7200_DEV_MCU_NAVSS0_INTR_0 237 30 J7200_DEV_MCU_R5FSS0_CORE0 intr 94
J7200_DEV_MCU_NAVSS0_INTR_0 237 31 J7200_DEV_MCU_R5FSS0_CORE0 intr 95
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 32 J7200_DEV_MCU_R5FSS0_CORE1 intr 64
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 33 J7200_DEV_MCU_R5FSS0_CORE1 intr 65
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 34 J7200_DEV_MCU_R5FSS0_CORE1 intr 66
J7200_DEV_MCU_NAVSS0_INTR_0 (Reserved by System Firmware) 237 35 J7200_DEV_MCU_R5FSS0_CORE1 intr 67
J7200_DEV_MCU_NAVSS0_INTR_0 237 36 J7200_DEV_MCU_R5FSS0_CORE1 intr 68
J7200_DEV_MCU_NAVSS0_INTR_0 237 37 J7200_DEV_MCU_R5FSS0_CORE1 intr 69
J7200_DEV_MCU_NAVSS0_INTR_0 237 38 J7200_DEV_MCU_R5FSS0_CORE1 intr 70
J7200_DEV_MCU_NAVSS0_INTR_0 237 39 J7200_DEV_MCU_R5FSS0_CORE1 intr 71
J7200_DEV_MCU_NAVSS0_INTR_0 237 40 J7200_DEV_MCU_R5FSS0_CORE1 intr 72
J7200_DEV_MCU_NAVSS0_INTR_0 237 41 J7200_DEV_MCU_R5FSS0_CORE1 intr 73
J7200_DEV_MCU_NAVSS0_INTR_0 237 42 J7200_DEV_MCU_R5FSS0_CORE1 intr 74
J7200_DEV_MCU_NAVSS0_INTR_0 237 43 J7200_DEV_MCU_R5FSS0_CORE1 intr 75
J7200_DEV_MCU_NAVSS0_INTR_0 237 44 J7200_DEV_MCU_R5FSS0_CORE1 intr 76
J7200_DEV_MCU_NAVSS0_INTR_0 237 45 J7200_DEV_MCU_R5FSS0_CORE1 intr 77
J7200_DEV_MCU_NAVSS0_INTR_0 237 46 J7200_DEV_MCU_R5FSS0_CORE1 intr 78
J7200_DEV_MCU_NAVSS0_INTR_0 237 47 J7200_DEV_MCU_R5FSS0_CORE1 intr 79
J7200_DEV_MCU_NAVSS0_INTR_0 237 48 J7200_DEV_MCU_R5FSS0_CORE1 intr 80
J7200_DEV_MCU_NAVSS0_INTR_0 237 49 J7200_DEV_MCU_R5FSS0_CORE1 intr 81
J7200_DEV_MCU_NAVSS0_INTR_0 237 50 J7200_DEV_MCU_R5FSS0_CORE1 intr 82
J7200_DEV_MCU_NAVSS0_INTR_0 237 51 J7200_DEV_MCU_R5FSS0_CORE1 intr 83
J7200_DEV_MCU_NAVSS0_INTR_0 237 52 J7200_DEV_MCU_R5FSS0_CORE1 intr 84
J7200_DEV_MCU_NAVSS0_INTR_0 237 53 J7200_DEV_MCU_R5FSS0_CORE1 intr 85
J7200_DEV_MCU_NAVSS0_INTR_0 237 54 J7200_DEV_MCU_R5FSS0_CORE1 intr 86
J7200_DEV_MCU_NAVSS0_INTR_0 237 55 J7200_DEV_MCU_R5FSS0_CORE1 intr 87
J7200_DEV_MCU_NAVSS0_INTR_0 237 56 J7200_DEV_MCU_R5FSS0_CORE1 intr 88
J7200_DEV_MCU_NAVSS0_INTR_0 237 57 J7200_DEV_MCU_R5FSS0_CORE1 intr 89
J7200_DEV_MCU_NAVSS0_INTR_0 237 58 J7200_DEV_MCU_R5FSS0_CORE1 intr 90
J7200_DEV_MCU_NAVSS0_INTR_0 237 59 J7200_DEV_MCU_R5FSS0_CORE1 intr 91
J7200_DEV_MCU_NAVSS0_INTR_0 237 60 J7200_DEV_MCU_R5FSS0_CORE1 intr 92
J7200_DEV_MCU_NAVSS0_INTR_0 237 61 J7200_DEV_MCU_R5FSS0_CORE1 intr 93
J7200_DEV_MCU_NAVSS0_INTR_0 237 62 J7200_DEV_MCU_R5FSS0_CORE1 intr 94
J7200_DEV_MCU_NAVSS0_INTR_0 237 63 J7200_DEV_MCU_R5FSS0_CORE1 intr 95

Interrupt Aggregator Device IDs

Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on J7200 Device IDs these are the valid Interrupt Aggregator device IDs.

Interrupt Aggregator Device Name Interrupt Aggregator Device ID
J7200_DEV_NAVSS0_MODSS_INTA_0 207
J7200_DEV_NAVSS0_MODSS_INTA_1 208
J7200_DEV_NAVSS0_UDMASS_INTA_0 209
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233

Interrupt Aggregator Virtual Interrupts

This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

Interrupt Aggregator Name Virtual Interrupt Range
J7200_DEV_NAVSS0_MODSS_INTA_0 0 to 63
J7200_DEV_NAVSS0_MODSS_INTA_1 0 to 63
J7200_DEV_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) 0 to 17
J7200_DEV_NAVSS0_UDMASS_INTA_0 18 to 255
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) 0 to 14
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 15 to 255

MCU_NAVSS0_UDMASS_INTA_0 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name IA Device ID IA VINT Index Destination Name Destination Interface Destination Index
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 0 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 0
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 1 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 1
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 2 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 2
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 3 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 3
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 4 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 4
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 5 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 5
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 6 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 6
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 7 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 7
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 8 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 8
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 9 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 9
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 10 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 10
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 11 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 11
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 12 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 12
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 13 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 13
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (Reserved by System Firmware) 233 14 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 14
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 15 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 15
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 16 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 16
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 17 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 17
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 18 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 18
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 19 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 19
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 20 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 20
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 21 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 21
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 22 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 22
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 23 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 23
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 24 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 24
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 25 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 25
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 26 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 26
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 27 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 27
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 28 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 28
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 29 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 29
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 30 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 30
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 31 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 31
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 32 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 32
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 33 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 33
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 34 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 34
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 35 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 35
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 36 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 36
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 37 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 37
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 38 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 38
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 39 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 39
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 40 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 40
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 41 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 41
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 42 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 42
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 43 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 43
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 44 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 44
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 45 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 45
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 46 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 46
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 47 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 47
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 48 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 48
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 49 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 49
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 50 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 50
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 51 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 51
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 52 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 52
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 53 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 53
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 54 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 54
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 55 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 55
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 56 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 56
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 57 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 57
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 58 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 58
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 59 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 59
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 60 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 60
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 61 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 61
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 62 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 62
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 63 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 63
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 64 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 64
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 65 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 65
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 66 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 66
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 67 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 67
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 68 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 68
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 69 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 69
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 70 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 70
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 71 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 71
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 72 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 72
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 73 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 73
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 74 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 74
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 75 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 75
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 76 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 76
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 77 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 77
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 78 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 78
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 79 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 79
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 80 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 80
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 81 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 81
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 82 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 82
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 83 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 83
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 84 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 84
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 85 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 85
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 86 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 86
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 87 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 87
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 88 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 88
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 89 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 89
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 90 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 90
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 91 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 91
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 92 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 92
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 93 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 93
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 94 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 94
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 95 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 95
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 96 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 96
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 97 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 97
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 98 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 98
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 99 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 99
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 100 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 100
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 101 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 101
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 102 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 102
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 103 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 103
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 104 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 104
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 105 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 105
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 106 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 106
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 107 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 107
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 108 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 108
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 109 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 109
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 110 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 110
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 111 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 111
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 112 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 112
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 113 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 113
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 114 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 114
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 115 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 115
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 116 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 116
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 117 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 117
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 118 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 118
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 119 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 119
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 120 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 120
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 121 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 121
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 122 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 122
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 123 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 123
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 124 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 124
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 125 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 125
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 126 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 126
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 127 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 127
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 128 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 128
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 129 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 129
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 130 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 130
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 131 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 131
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 132 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 132
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 133 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 133
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 134 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 134
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 135 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 135
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 136 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 136
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 137 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 137
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 138 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 138
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 139 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 139
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 140 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 140
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 141 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 141
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 142 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 142
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 143 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 143
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 144 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 144
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 145 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 145
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 146 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 146
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 147 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 147
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 148 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 148
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 149 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 149
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 150 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 150
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 151 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 151
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 152 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 152
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 153 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 153
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 154 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 154
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 155 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 155
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 156 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 156
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 157 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 157
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 158 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 158
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 159 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 159
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 160 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 160
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 161 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 161
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 162 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 162
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 163 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 163
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 164 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 164
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 165 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 165
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 166 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 166
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 167 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 167
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 168 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 168
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 169 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 169
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 170 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 170
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 171 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 171
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 172 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 172
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 173 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 173
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 174 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 174
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 175 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 175
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 176 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 176
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 177 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 177
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 178 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 178
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 179 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 179
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 180 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 180
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 181 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 181
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 182 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 182
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 183 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 183
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 184 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 184
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 185 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 185
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 186 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 186
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 187 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 187
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 188 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 188
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 189 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 189
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 190 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 190
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 191 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 191
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 192 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 192
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 193 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 193
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 194 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 194
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 195 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 195
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 196 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 196
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 197 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 197
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 198 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 198
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 199 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 199
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 200 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 200
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 201 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 201
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 202 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 202
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 203 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 203
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 204 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 204
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 205 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 205
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 206 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 206
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 207 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 207
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 208 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 208
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 209 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 209
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 210 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 210
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 211 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 211
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 212 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 212
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 213 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 213
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 214 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 214
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 215 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 215
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 216 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 216
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 217 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 217
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 218 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 218
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 219 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 219
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 220 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 220
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 221 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 221
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 222 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 222
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 223 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 223
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 224 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 224
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 225 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 225
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 226 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 226
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 227 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 227
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 228 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 228
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 229 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 229
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 230 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 230
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 231 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 231
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 232 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 232
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 233 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 233
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 234 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 234
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 235 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 235
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 236 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 236
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 237 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 237
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 238 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 238
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 239 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 239
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 240 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 240
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 241 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 241
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 242 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 242
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 243 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 243
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 244 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 244
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 245 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 245
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 246 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 246
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 247 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 247
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 248 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 248
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 249 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 249
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 250 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 250
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 251 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 251
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 252 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 252
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 253 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 253
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 254 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 254
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 255 J7200_DEV_MCU_NAVSS0_INTR_0 in_intr 255

Global Events

This section describes J7200 global events. The global events are used in interrupt management based TISCI messages.

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

Global Event Name Global Event Range
NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) 0 to 17
NAVSS0_UDMASS_INTA_0 SEVT 18 to 4607
MCU_NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) 16384 to 16398
MCU_NAVSS0_UDMASS_INTA_0 SEVT 16399 to 17919
NAVSS0_MODSS_INTA_0 SEVT 20480 to 21503
NAVSS0_MODSS_INTA_1 SEVT 22528 to 23551
NAVSS0_UDMASS_INTA_0 MEVT 32768 to 33279
MCU_NAVSS0_UDMASS_INTA_0 MEVT 34816 to 34943
NAVSS0_UDMASS_INTA_0 GEVT 36864 to 37375
MCU_NAVSS0_UDMASS_INTA_0 GEVT 39936 to 40191
NAVSS0_UDMAP_0 TRIGGER 49152 to 50175
MCU_NAVSS0_UDMAP_0 TRIGGER 56320 to 56575

Event-Based Interrupt Source IDs

Device Name Device ID Interrupt Source Name Interrupt Source Index
J7200_DEV_NAVSS0_RINGACC_0 211 Ring events 0 to 973
J7200_DEV_MCU_NAVSS0_RINGACC0 235 Ring events 0 to 255
J7200_DEV_NAVSS0_RINGACC_0 211 Ring monitor events 1024 to 1055
J7200_DEV_MCU_NAVSS0_RINGACC0 235 Ring monitor events 1024 to 1055
J7200_DEV_NAVSS0_RINGACC_0 211 Ring global error event 2048
J7200_DEV_MCU_NAVSS0_RINGACC0 235 Ring global error event 2048
J7200_DEV_NAVSS0_UDMAP_0 212 UDMA transmit channel OES events 0 to 59
J7200_DEV_NAVSS0_UDMAP_0 212 UDMA transmit channel EOES events 64 to 123
J7200_DEV_NAVSS0_UDMAP_0 212 UDMA receive channel OES events 128 to 187
J7200_DEV_NAVSS0_UDMAP_0 212 UDMA receive channel EOES events 192 to 251
J7200_DEV_NAVSS0_UDMAP_0 212 UDMA global configuration invalid flow event 256
J7200_DEV_MCU_NAVSS0_UDMAP_0 236 UDMA transmit channel OES events 0 to 47
J7200_DEV_MCU_NAVSS0_UDMAP_0 236 UDMA transmit channel EOES events 64 to 111
J7200_DEV_MCU_NAVSS0_UDMAP_0 236 UDMA receive channel OES events 128 to 175
J7200_DEV_MCU_NAVSS0_UDMAP_0 236 UDMA receive channel EOES events 192 to 239
J7200_DEV_MCU_NAVSS0_UDMAP_0 236 UDMA global configuration invalid flow event 256