J7200 Interrupt Management Device Descriptions¶
Introduction¶
This chapter provides information on the Interrupt Management devices in the J7200 SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.
Interrupt Router Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on J7200 Device IDs these are the valid Interrupt Router device IDs.
| Interrupt Router Device Name | Interrupt Router Device ID |
|---|---|
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 |
| J7200_DEV_NAVSS0_INTR_ROUTER_0 | 213 |
| J7200_DEV_MCU_NAVSS0_INTR_0 | 237 |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 0 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 1 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 2 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 3 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 4 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 5 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 6 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 7 | J7200_DEV_ELM0 | elm_porocpsinterrupt_lvl | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 8 | J7200_DEV_GPMC0 | gpmc_sinterrupt | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 9 | J7200_DEV_DDR0 | ddrss_pll_freq_change_req | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 10 | J7200_DEV_DDR0 | ddrss_controller | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 11 | J7200_DEV_DDR0 | ddrss_v2a_other_err_lvl | 3 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 12 | J7200_DEV_DDR0 | ddrss_hs_phy_global_error | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 13 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 14 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 15 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 16 | J7200_DEV_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 17 | J7200_DEV_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 18 | J7200_DEV_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 19 | J7200_DEV_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 20 | J7200_DEV_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 21 | J7200_DEV_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 22 | J7200_DEV_MCAN2 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 23 | J7200_DEV_MCAN2 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 24 | J7200_DEV_MCAN2 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 25 | J7200_DEV_MCAN3 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 26 | J7200_DEV_MCAN3 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 27 | J7200_DEV_MCAN3 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 28 | J7200_DEV_MMCSD0 | emmcss_intr | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 29 | J7200_DEV_MMCSD1 | emmcsdss_intr | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 30 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 31 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 32 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 33 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 34 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 35 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 36 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 37 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 38 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 39 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 40 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 41 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 42 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 43 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 44 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 45 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 46 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 47 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 48 | J7200_DEV_MCSPI0 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 49 | J7200_DEV_MCSPI1 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 50 | J7200_DEV_MCSPI2 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 51 | J7200_DEV_MCSPI3 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 52 | J7200_DEV_MCSPI4 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 53 | J7200_DEV_MCSPI5 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 54 | J7200_DEV_MCSPI6 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 55 | J7200_DEV_MCSPI7 | intr_spi | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 56 | J7200_DEV_I2C0 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 57 | J7200_DEV_I2C1 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 58 | J7200_DEV_I2C2 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 59 | J7200_DEV_I2C3 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 60 | J7200_DEV_I2C4 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 61 | J7200_DEV_I2C5 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 62 | J7200_DEV_I2C6 | pointrpend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 63 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 64 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 65 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 66 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 67 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 68 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 69 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 70 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 71 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 72 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 73 | J7200_DEV_PCIE1 | pcie_phy_level | 13 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 74 | J7200_DEV_PCIE1 | pcie_local_level | 12 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 75 | J7200_DEV_PCIE1 | pcie_cpts_pend | 3 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 76 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 77 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 78 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 79 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 80 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 81 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 82 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 83 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 84 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 85 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 86 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 87 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 88 | J7200_DEV_DCC0 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 89 | J7200_DEV_DCC1 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 90 | J7200_DEV_DCC2 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 91 | J7200_DEV_DCC3 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 92 | J7200_DEV_DCC4 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 93 | J7200_DEV_DCC5 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 94 | J7200_DEV_DCC6 | intr_done_level | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 95 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 96 | J7200_DEV_UART0 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 97 | J7200_DEV_UART1 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 98 | J7200_DEV_UART2 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 99 | J7200_DEV_UART3 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 100 | J7200_DEV_UART4 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 101 | J7200_DEV_UART5 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 102 | J7200_DEV_UART6 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 103 | J7200_DEV_UART7 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 104 | J7200_DEV_UART8 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 105 | J7200_DEV_UART9 | usart_irq | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 106 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 107 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 108 | J7200_DEV_TIMER0 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 109 | J7200_DEV_TIMER1 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 110 | J7200_DEV_TIMER2 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 111 | J7200_DEV_TIMER3 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 112 | J7200_DEV_TIMER4 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 113 | J7200_DEV_TIMER5 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 114 | J7200_DEV_TIMER6 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 115 | J7200_DEV_TIMER7 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 116 | J7200_DEV_TIMER8 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 117 | J7200_DEV_TIMER9 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 118 | J7200_DEV_TIMER10 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 119 | J7200_DEV_TIMER11 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 120 | J7200_DEV_TIMER12 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 121 | J7200_DEV_TIMER13 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 122 | J7200_DEV_TIMER14 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 123 | J7200_DEV_TIMER15 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 124 | J7200_DEV_TIMER16 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 125 | J7200_DEV_TIMER17 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 126 | J7200_DEV_TIMER18 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 127 | J7200_DEV_TIMER19 | intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 128 | J7200_DEV_USB0 | irq | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 129 | J7200_DEV_USB0 | irq | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 130 | J7200_DEV_USB0 | irq | 3 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 131 | J7200_DEV_USB0 | irq | 4 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 132 | J7200_DEV_USB0 | irq | 5 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 133 | J7200_DEV_USB0 | irq | 6 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 134 | J7200_DEV_USB0 | irq | 7 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 135 | J7200_DEV_USB0 | irq | 8 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 136 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 137 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 138 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 139 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 140 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 141 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 142 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 143 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 144 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 145 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 146 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 147 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 148 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 149 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 150 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 151 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 152 | J7200_DEV_USB0 | otgirq | 9 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 153 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 154 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 155 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 156 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 157 | J7200_DEV_USB0 | host_system_error | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 158 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 159 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 160 | J7200_DEV_MCAN14 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 161 | J7200_DEV_MCAN14 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 162 | J7200_DEV_MCAN14 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 163 | J7200_DEV_MCAN15 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 164 | J7200_DEV_MCAN15 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 165 | J7200_DEV_MCAN15 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 166 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 167 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 168 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 169 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 170 | J7200_DEV_MCAN16 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 171 | J7200_DEV_MCAN16 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 172 | J7200_DEV_MCAN16 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 173 | J7200_DEV_MCAN17 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 174 | J7200_DEV_MCAN17 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 175 | J7200_DEV_MCAN17 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 176 | J7200_DEV_MCASP0 | xmit_intr_pend | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 177 | J7200_DEV_MCASP0 | rec_intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 178 | J7200_DEV_MCASP1 | xmit_intr_pend | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 179 | J7200_DEV_MCASP1 | rec_intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 180 | J7200_DEV_MCASP2 | xmit_intr_pend | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 181 | J7200_DEV_MCASP2 | rec_intr_pend | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 182 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 183 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 184 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 185 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 186 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 187 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 188 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 189 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 190 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 191 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 192 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 193 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 194 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 195 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 196 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 197 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 198 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 199 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 200 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 201 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 202 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 203 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 204 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 205 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 206 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 207 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 208 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 209 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 210 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 211 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 212 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 213 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 214 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 215 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 216 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 217 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 218 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 219 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 220 | J7200_DEV_I3C0 | i3c__int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 221 | J7200_DEV_CPSW0 | stat_pend | 6 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 222 | J7200_DEV_CPSW0 | mdio_pend | 5 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 223 | J7200_DEV_CPSW0 | evnt_pend | 4 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 224 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 225 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 226 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 227 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 228 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 229 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 230 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 231 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 232 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 233 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 234 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 235 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 236 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 237 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 238 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 239 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 240 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 241 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 242 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 243 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 244 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 245 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 246 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 247 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 248 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 249 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 250 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 251 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 252 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 253 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 254 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 255 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 256 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 257 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 258 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 259 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 260 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 261 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 262 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 263 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 264 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 265 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 266 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 267 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 268 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 269 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 270 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 271 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 272 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 273 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 274 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 275 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 276 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 277 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 278 | J7200_DEV_MCAN4 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 279 | J7200_DEV_MCAN4 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 280 | J7200_DEV_MCAN4 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 281 | J7200_DEV_MCAN5 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 282 | J7200_DEV_MCAN5 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 283 | J7200_DEV_MCAN5 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 284 | J7200_DEV_MCAN6 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 285 | J7200_DEV_MCAN6 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 286 | J7200_DEV_MCAN6 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 287 | J7200_DEV_MCAN7 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 288 | J7200_DEV_MCAN7 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 289 | J7200_DEV_MCAN7 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 290 | J7200_DEV_MCAN8 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 291 | J7200_DEV_MCAN8 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 292 | J7200_DEV_MCAN8 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 293 | J7200_DEV_MCAN9 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 294 | J7200_DEV_MCAN9 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 295 | J7200_DEV_MCAN9 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 296 | J7200_DEV_MCAN10 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 297 | J7200_DEV_MCAN10 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 298 | J7200_DEV_MCAN10 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 299 | J7200_DEV_MCAN11 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 300 | J7200_DEV_MCAN11 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 301 | J7200_DEV_MCAN11 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 302 | J7200_DEV_MCAN12 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 303 | J7200_DEV_MCAN12 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 304 | J7200_DEV_MCAN12 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 305 | J7200_DEV_MCAN13 | mcanss_mcan_lvl_int | 1 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 306 | J7200_DEV_MCAN13 | mcanss_mcan_lvl_int | 2 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 307 | J7200_DEV_MCAN13 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 308 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 309 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 310 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 311 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 312 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 313 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 314 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 315 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 316 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 317 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 318 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 319 | Use TRM - Not managed by TISCI |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 0 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 160 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 160 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 1 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 161 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 161 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 2 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 162 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 162 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 3 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 163 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 163 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 4 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 164 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 164 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 5 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 165 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 165 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 6 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 166 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 166 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 7 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 167 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 167 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 8 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 168 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 168 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 9 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 169 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 169 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 10 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 170 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 170 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 11 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 171 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 171 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 12 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 172 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 172 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 13 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 173 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 173 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 14 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 174 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 174 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 15 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 175 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 175 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 16 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 176 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 176 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 17 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 177 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 177 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 18 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 178 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 178 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 19 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 179 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 179 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 20 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 180 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 180 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 21 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 181 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 181 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 22 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 182 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 182 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 23 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 183 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 183 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 24 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 184 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 184 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 25 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 185 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 185 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 26 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 186 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 186 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 27 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 187 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 187 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 28 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 188 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 188 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 29 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 189 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 189 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 30 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 190 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 190 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 31 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 191 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 191 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 32 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 192 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 192 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 33 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 193 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 193 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 34 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 194 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 194 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 35 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 195 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 195 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 36 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 196 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 196 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 37 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 197 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 197 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 38 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 198 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 198 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 39 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 199 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 199 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 40 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 200 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 200 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 41 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 201 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 201 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 42 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 202 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 202 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 43 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 203 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 203 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 44 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 204 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 204 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 45 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 205 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 205 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 46 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 206 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 206 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 47 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 207 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 207 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 48 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 208 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 208 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 49 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 209 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 209 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 50 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 210 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 210 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 51 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 211 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 211 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 52 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 212 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 212 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 53 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 213 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 213 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 54 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 214 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 214 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 55 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 215 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 215 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 56 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 216 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 216 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 57 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 217 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 217 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 58 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 218 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 218 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 59 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 219 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 219 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 60 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 220 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 220 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 61 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 221 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 221 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 62 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 222 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 222 | |||
| J7200_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 63 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 223 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 223 |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 0 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 1 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 2 | J7200_DEV_EHRPWM0 | epwm_etint | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 3 | J7200_DEV_EHRPWM1 | epwm_etint | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 4 | J7200_DEV_EHRPWM2 | epwm_etint | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 5 | J7200_DEV_EHRPWM3 | epwm_etint | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 6 | J7200_DEV_EHRPWM4 | epwm_etint | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 7 | J7200_DEV_EHRPWM5 | epwm_etint | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 8 | J7200_DEV_EHRPWM0 | epwm_tripzint | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 9 | J7200_DEV_EHRPWM1 | epwm_tripzint | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 10 | J7200_DEV_EHRPWM2 | epwm_tripzint | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 11 | J7200_DEV_EHRPWM3 | epwm_tripzint | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 12 | J7200_DEV_EHRPWM4 | epwm_tripzint | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 13 | J7200_DEV_EHRPWM5 | epwm_tripzint | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 14 | J7200_DEV_EQEP0 | eqep_int | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 15 | J7200_DEV_EQEP1 | eqep_int | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 16 | J7200_DEV_EQEP2 | eqep_int | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 17 | J7200_DEV_ECAP0 | ecap_int | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 18 | J7200_DEV_ECAP1 | ecap_int | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 19 | J7200_DEV_ECAP2 | ecap_int | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 20 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 21 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 22 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 23 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 24 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 25 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 26 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 27 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 28 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 29 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 30 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 31 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 32 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 33 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 34 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 35 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 36 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 37 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 38 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 39 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 40 | J7200_DEV_PCIE1 | pcie_legacy_pulse | 10 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 41 | J7200_DEV_PCIE1 | pcie_downstream_pulse | 5 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 42 | J7200_DEV_PCIE1 | pcie_flr_pulse | 8 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 43 | J7200_DEV_PCIE1 | pcie_error_pulse | 7 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 44 | J7200_DEV_PCIE1 | pcie_link_state_pulse | 11 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 45 | J7200_DEV_PCIE1 | pcie_pwr_state_pulse | 15 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 46 | J7200_DEV_PCIE1 | pcie_ptm_valid_pulse | 14 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 47 | J7200_DEV_PCIE1 | pcie_hot_reset_pulse | 9 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 48 | J7200_DEV_PCIE1 | pcie_dpa_pulse | 6 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 49 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 50 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 51 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 52 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 53 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 54 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 55 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 56 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 57 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 58 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 59 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 60 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 61 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 62 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 63 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 64 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 0 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 65 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 1 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 66 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 2 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 67 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 3 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 68 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 4 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 69 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 5 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 70 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 6 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 71 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 7 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 72 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 8 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 73 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 9 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 74 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 10 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 75 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 11 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 76 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 12 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 77 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 13 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 78 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 14 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 79 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 15 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 80 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 16 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 81 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 17 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 82 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 18 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 83 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 19 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 84 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 20 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 85 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 21 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 86 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 22 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 87 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 23 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 88 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 24 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 89 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 25 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 90 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 26 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 91 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 27 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 92 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 28 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 93 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 29 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 94 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 30 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 95 | J7200_DEV_GPIOMUX_INTRTR0 | outp | 31 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 96 | J7200_DEV_CMPEVENT_INTRTR0 | outp | 4 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 97 | J7200_DEV_CMPEVENT_INTRTR0 | outp | 5 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 98 | J7200_DEV_CMPEVENT_INTRTR0 | outp | 6 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 99 | J7200_DEV_CMPEVENT_INTRTR0 | outp | 7 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 100 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 101 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 102 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 103 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 104 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 105 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 106 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 107 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 108 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 109 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 110 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 111 | Use TRM - Not managed by TISCI |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 0 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 224 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 224 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 1 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 225 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 225 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 2 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 226 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 226 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 3 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 227 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 227 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 4 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 228 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 228 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 5 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 229 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 229 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 6 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 230 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 230 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 7 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 231 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 231 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 8 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 232 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 232 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 9 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 233 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 233 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 10 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 234 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 234 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 11 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 235 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 235 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 12 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 236 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 236 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 13 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 237 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 237 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 14 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 238 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 238 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 15 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 239 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 239 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 16 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 240 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 240 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 17 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 241 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 241 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 18 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 242 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 242 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 19 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 243 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 243 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 20 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 244 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 244 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 21 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 245 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 245 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 22 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 246 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 246 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 23 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 247 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 247 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 24 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 248 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 248 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 25 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 249 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 249 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 26 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 250 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 250 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 27 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 251 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 251 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 28 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 252 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 252 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 29 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 253 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 253 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 30 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 254 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 254 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 31 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 255 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 255 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 32 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 256 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 256 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 33 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 257 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 257 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 34 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 258 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 258 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 35 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 259 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 259 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 36 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 260 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 260 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 37 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 261 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 261 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 38 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 262 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 262 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 39 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 263 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 263 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 40 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 264 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 264 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 41 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 265 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 265 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 42 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 266 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 266 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 43 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 267 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 267 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 44 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 268 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 268 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 45 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 269 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 269 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 46 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 270 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 270 | |||
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 47 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 271 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 271 |
TIMESYNC_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 0 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 1 | J7200_DEV_GTC0 | gtc_push_event | 0 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 2 | J7200_DEV_TIMER14 | timer_pwm | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 3 | J7200_DEV_TIMER15 | timer_pwm | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 4 | J7200_DEV_NAVSS0 | cpts0_genf0 | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 5 | J7200_DEV_NAVSS0 | cpts0_genf1 | 2 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 6 | J7200_DEV_NAVSS0 | cpts0_genf2 | 3 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 7 | J7200_DEV_NAVSS0 | cpts0_genf3 | 4 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 8 | J7200_DEV_NAVSS0 | cpts0_genf4 | 5 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 9 | J7200_DEV_NAVSS0 | cpts0_genf5 | 6 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 10 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 11 | J7200_DEV_PCIE1 | pcie_cpts_genf0 | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 12 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 13 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 14 | J7200_DEV_CPSW0 | cpts_genf0 | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 15 | J7200_DEV_CPSW0 | cpts_genf1 | 2 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 16 | J7200_DEV_MCU_CPSW0 | cpts_genf0 | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 17 | J7200_DEV_MCU_CPSW0 | cpts_genf1 | 2 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 18 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 19 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 20 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 21 | J7200_DEV_PCIE1 | pcie_cpts_hw1_push | 2 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 22 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 23 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 24 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 25 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 26 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 27 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 28 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 29 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 30 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 31 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 32 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 33 | J7200_DEV_PCIE1 | pcie_cpts_sync | 4 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 34 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 35 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 36 | J7200_DEV_NAVSS0 | cpts0_sync | 7 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 37 | J7200_DEV_CPSW0 | cpts_sync | 3 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 38 | J7200_DEV_MCU_CPSW0 | cpts_sync | 3 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 39 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 40 | J7200_DEV_TIMER16 | timer_pwm | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 41 | J7200_DEV_TIMER17 | timer_pwm | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 42 | J7200_DEV_TIMER18 | timer_pwm | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 43 | J7200_DEV_TIMER19 | timer_pwm | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 44 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 45 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 46 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 47 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 48 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 49 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 50 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 51 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 52 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 53 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 54 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 55 | Use TRM - Not managed by TISCI |
TIMESYNC_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 0 | J7200_DEV_NAVSS0 | cpts0_hw1_push | 0 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 1 | J7200_DEV_NAVSS0 | cpts0_hw2_push | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 2 | J7200_DEV_NAVSS0 | cpts0_hw3_push | 2 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 3 | J7200_DEV_NAVSS0 | cpts0_hw4_push | 3 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 4 | J7200_DEV_NAVSS0 | cpts0_hw5_push | 4 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 5 | J7200_DEV_NAVSS0 | cpts0_hw6_push | 5 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 6 | J7200_DEV_NAVSS0 | cpts0_hw7_push | 6 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 7 | J7200_DEV_NAVSS0 | cpts0_hw8_push | 7 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 8 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 9 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 10 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 11 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 12 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 13 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 14 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 15 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 16 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 17 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 18 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 19 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 20 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 21 | J7200_DEV_PCIE1 | pcie_cpts_hw2_push | 0 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 22 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 23 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 24 | J7200_DEV_MCU_CPSW0 | cpts_hw3_push | 0 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 25 | J7200_DEV_MCU_CPSW0 | cpts_hw4_push | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 26 | J7200_DEV_CPSW0 | cpts_hw1_push | 0 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 27 | J7200_DEV_CPSW0 | cpts_hw2_push | 1 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 28 | J7200_DEV_CPSW0 | cpts_hw3_push | 2 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 29 | J7200_DEV_CPSW0 | cpts_hw4_push | 3 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 30 | J7200_DEV_CPSW0 | cpts_hw5_push | 4 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 31 | J7200_DEV_CPSW0 | cpts_hw6_push | 5 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 32 | J7200_DEV_CPSW0 | cpts_hw7_push | 6 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 33 | J7200_DEV_CPSW0 | cpts_hw8_push | 7 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 34 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 35 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 36 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 37 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 38 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 39 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 40 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 52 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 41 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 53 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 42 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 54 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 43 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 55 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 44 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 56 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 45 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 57 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 46 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 58 |
| J7200_DEV_TIMESYNC_INTRTR0 | 136 | 47 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 59 |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 0 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 1 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 2 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 3 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 4 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 5 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 6 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 7 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 20 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 21 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 22 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 23 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 24 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 25 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 26 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 27 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 28 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 29 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 30 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 31 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 32 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 33 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 34 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 35 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 36 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 37 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 38 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 39 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 40 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 41 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 42 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 43 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 44 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 45 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 46 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 47 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 48 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 49 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 50 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 51 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 52 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 53 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 54 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 55 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 56 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 57 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 58 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 59 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 60 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 61 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 62 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 63 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 64 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 65 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 66 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 67 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 68 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 69 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 70 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 71 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 72 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 73 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 74 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 75 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 76 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 77 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 78 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 79 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 80 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 81 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 82 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 83 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 84 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 85 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 86 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 87 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 88 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 89 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 90 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 91 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 92 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 93 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 94 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 95 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 96 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 97 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 98 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 99 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 100 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 101 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 102 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 103 | J7200_DEV_WKUP_GPIO0 | gpio_bank | 0 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 104 | J7200_DEV_WKUP_GPIO0 | gpio_bank | 1 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 105 | J7200_DEV_WKUP_GPIO0 | gpio_bank | 2 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 106 | J7200_DEV_WKUP_GPIO0 | gpio_bank | 3 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 107 | J7200_DEV_WKUP_GPIO0 | gpio_bank | 4 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 108 | J7200_DEV_WKUP_GPIO0 | gpio_bank | 5 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 109 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 110 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 111 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 112 | J7200_DEV_WKUP_GPIO1 | gpio_bank | 0 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 113 | J7200_DEV_WKUP_GPIO1 | gpio_bank | 1 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 114 | J7200_DEV_WKUP_GPIO1 | gpio_bank | 2 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 115 | J7200_DEV_WKUP_GPIO1 | gpio_bank | 3 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 116 | J7200_DEV_WKUP_GPIO1 | gpio_bank | 4 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 117 | J7200_DEV_WKUP_GPIO1 | gpio_bank | 5 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 118 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 119 | Use TRM - Not managed by TISCI |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 0 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 124 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 124 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 1 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 125 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 125 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 2 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 126 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 126 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 3 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 127 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 127 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 4 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 128 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 128 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 5 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 129 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 129 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 6 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 130 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 130 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 7 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 131 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 131 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 120 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 128 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 136 |
| J7200_DEV_MCU_R5FSS0_CORE0 | intr | 132 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | J7200_DEV_MCU_R5FSS0_CORE1 | intr | 132 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 121 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 129 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 137 |
| J7200_DEV_MCU_R5FSS0_CORE0 | intr | 133 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | J7200_DEV_MCU_R5FSS0_CORE1 | intr | 133 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 122 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 130 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 138 |
| J7200_DEV_MCU_R5FSS0_CORE0 | intr | 134 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | J7200_DEV_MCU_R5FSS0_CORE1 | intr | 134 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 123 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 131 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 139 |
| J7200_DEV_MCU_R5FSS0_CORE0 | intr | 135 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | J7200_DEV_MCU_R5FSS0_CORE1 | intr | 135 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 124 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 132 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 140 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 4 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 136 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 136 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 125 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 133 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 141 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 5 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 137 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 137 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 126 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 134 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 142 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 6 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 138 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 138 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | J7200_DEV_WKUP_ESM0 | esm_pls_event0 | 127 |
| J7200_DEV_WKUP_ESM0 | esm_pls_event1 | 135 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | J7200_DEV_WKUP_ESM0 | esm_pls_event2 | 143 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 7 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | J7200_DEV_MCU_R5FSS0_CORE0 | intr | 139 |
| J7200_DEV_MCU_R5FSS0_CORE1 | intr | 139 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 960 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 8 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | J7200_DEV_R5FSS0_CORE0 | intr | 488 |
| J7200_DEV_R5FSS0_CORE1 | intr | 488 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 961 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 9 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | J7200_DEV_R5FSS0_CORE0 | intr | 489 |
| J7200_DEV_R5FSS0_CORE1 | intr | 489 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 962 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 10 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | J7200_DEV_R5FSS0_CORE0 | intr | 490 |
| J7200_DEV_R5FSS0_CORE1 | intr | 490 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 963 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 11 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | J7200_DEV_R5FSS0_CORE0 | intr | 491 |
| J7200_DEV_R5FSS0_CORE1 | intr | 491 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 20 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 964 |
| J7200_DEV_R5FSS0_CORE0 | intr | 492 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 20 | J7200_DEV_R5FSS0_CORE1 | intr | 492 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 21 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 965 |
| J7200_DEV_R5FSS0_CORE0 | intr | 493 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 21 | J7200_DEV_R5FSS0_CORE1 | intr | 493 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 22 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 966 |
| J7200_DEV_R5FSS0_CORE0 | intr | 494 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 22 | J7200_DEV_R5FSS0_CORE1 | intr | 494 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 23 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 967 |
| J7200_DEV_R5FSS0_CORE0 | intr | 495 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 23 | J7200_DEV_R5FSS0_CORE1 | intr | 495 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 24 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 968 |
| J7200_DEV_R5FSS0_CORE0 | intr | 496 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 24 | J7200_DEV_R5FSS0_CORE1 | intr | 496 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 25 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 969 |
| J7200_DEV_R5FSS0_CORE0 | intr | 497 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 25 | J7200_DEV_R5FSS0_CORE1 | intr | 497 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 26 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 970 |
| J7200_DEV_R5FSS0_CORE0 | intr | 498 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 26 | J7200_DEV_R5FSS0_CORE1 | intr | 498 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 27 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 971 |
| J7200_DEV_R5FSS0_CORE0 | intr | 499 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 27 | J7200_DEV_R5FSS0_CORE1 | intr | 499 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 28 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 972 |
| J7200_DEV_R5FSS0_CORE0 | intr | 500 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 28 | J7200_DEV_R5FSS0_CORE1 | intr | 500 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 29 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 973 |
| J7200_DEV_R5FSS0_CORE0 | intr | 501 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 29 | J7200_DEV_R5FSS0_CORE1 | intr | 501 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 30 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 974 |
| J7200_DEV_R5FSS0_CORE0 | intr | 502 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 30 | J7200_DEV_R5FSS0_CORE1 | intr | 502 |
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 31 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 975 |
| J7200_DEV_R5FSS0_CORE0 | intr | 503 | |||
| J7200_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 31 | J7200_DEV_R5FSS0_CORE1 | intr | 503 |
GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 0 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 1 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 2 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 3 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 4 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 5 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 6 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 7 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 8 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 9 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 10 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 11 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 12 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 13 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 14 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 15 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 16 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 17 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 18 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 19 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 20 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 21 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 22 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 23 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 24 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 25 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 26 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 27 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 28 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 29 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 30 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 31 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 32 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 33 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 34 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 35 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 36 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 37 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 38 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 39 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 40 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 41 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 42 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 43 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 44 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 45 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 46 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 47 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 48 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 49 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 50 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 51 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 52 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 53 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 54 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 55 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 56 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 57 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 58 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 59 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 60 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 61 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 62 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 63 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 64 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 65 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 66 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 67 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 68 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 69 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 70 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 71 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 72 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 73 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 74 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 75 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 76 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 77 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 78 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 79 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 80 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 81 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 82 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 83 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 84 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 85 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 86 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 87 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 88 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 89 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 90 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 91 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 92 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 93 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 94 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 95 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 96 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 97 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 98 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 99 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 100 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 101 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 102 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 103 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 104 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 105 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 106 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 107 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 108 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 109 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 110 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 111 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 112 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 113 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 114 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 115 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 116 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 117 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 118 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 119 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 120 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 121 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 122 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 123 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 124 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 125 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 126 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 127 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 128 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 129 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 130 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 131 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 132 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 133 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 134 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 135 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 136 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 137 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 138 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 139 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 140 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 141 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 142 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 143 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 144 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 145 | J7200_DEV_GPIO0 | gpio_bank | 0 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 146 | J7200_DEV_GPIO0 | gpio_bank | 1 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 147 | J7200_DEV_GPIO0 | gpio_bank | 2 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 148 | J7200_DEV_GPIO0 | gpio_bank | 3 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 149 | J7200_DEV_GPIO0 | gpio_bank | 4 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 150 | J7200_DEV_GPIO0 | gpio_bank | 5 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 151 | J7200_DEV_GPIO0 | gpio_bank | 6 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 152 | J7200_DEV_GPIO0 | gpio_bank | 7 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 153 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 154 | J7200_DEV_GPIO2 | gpio_bank | 0 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 155 | J7200_DEV_GPIO2 | gpio_bank | 1 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 156 | J7200_DEV_GPIO2 | gpio_bank | 2 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 157 | J7200_DEV_GPIO2 | gpio_bank | 3 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 158 | J7200_DEV_GPIO2 | gpio_bank | 4 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 159 | J7200_DEV_GPIO2 | gpio_bank | 5 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 160 | J7200_DEV_GPIO2 | gpio_bank | 6 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 161 | J7200_DEV_GPIO2 | gpio_bank | 7 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 162 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 163 | J7200_DEV_GPIO4 | gpio_bank | 0 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 164 | J7200_DEV_GPIO4 | gpio_bank | 1 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 165 | J7200_DEV_GPIO4 | gpio_bank | 2 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 166 | J7200_DEV_GPIO4 | gpio_bank | 3 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 167 | J7200_DEV_GPIO4 | gpio_bank | 4 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 168 | J7200_DEV_GPIO4 | gpio_bank | 5 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 169 | J7200_DEV_GPIO4 | gpio_bank | 6 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 170 | J7200_DEV_GPIO4 | gpio_bank | 7 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 171 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 172 | J7200_DEV_GPIO6 | gpio_bank | 0 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 173 | J7200_DEV_GPIO6 | gpio_bank | 1 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 174 | J7200_DEV_GPIO6 | gpio_bank | 2 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 175 | J7200_DEV_GPIO6 | gpio_bank | 3 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 176 | J7200_DEV_GPIO6 | gpio_bank | 4 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 177 | J7200_DEV_GPIO6 | gpio_bank | 5 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 178 | J7200_DEV_GPIO6 | gpio_bank | 6 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 179 | J7200_DEV_GPIO6 | gpio_bank | 7 |
GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 0 | J7200_DEV_ESM0 | esm_pls_event0 | 632 |
| J7200_DEV_ESM0 | esm_pls_event1 | 640 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 0 | J7200_DEV_ESM0 | esm_pls_event2 | 648 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 64 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 0 | J7200_DEV_R5FSS0_CORE0 | intr | 396 |
| J7200_DEV_R5FSS0_CORE1 | intr | 396 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 1 | J7200_DEV_ESM0 | esm_pls_event0 | 633 |
| J7200_DEV_ESM0 | esm_pls_event1 | 641 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 1 | J7200_DEV_ESM0 | esm_pls_event2 | 649 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 65 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 1 | J7200_DEV_R5FSS0_CORE0 | intr | 397 |
| J7200_DEV_R5FSS0_CORE1 | intr | 397 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 2 | J7200_DEV_ESM0 | esm_pls_event0 | 634 |
| J7200_DEV_ESM0 | esm_pls_event1 | 642 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 2 | J7200_DEV_ESM0 | esm_pls_event2 | 650 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 66 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 2 | J7200_DEV_R5FSS0_CORE0 | intr | 398 |
| J7200_DEV_R5FSS0_CORE1 | intr | 398 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 3 | J7200_DEV_ESM0 | esm_pls_event0 | 635 |
| J7200_DEV_ESM0 | esm_pls_event1 | 643 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 3 | J7200_DEV_ESM0 | esm_pls_event2 | 651 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 67 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 3 | J7200_DEV_R5FSS0_CORE0 | intr | 399 |
| J7200_DEV_R5FSS0_CORE1 | intr | 399 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 4 | J7200_DEV_ESM0 | esm_pls_event0 | 636 |
| J7200_DEV_ESM0 | esm_pls_event1 | 644 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 4 | J7200_DEV_ESM0 | esm_pls_event2 | 652 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 68 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 4 | J7200_DEV_R5FSS0_CORE0 | intr | 400 |
| J7200_DEV_R5FSS0_CORE1 | intr | 400 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 5 | J7200_DEV_ESM0 | esm_pls_event0 | 637 |
| J7200_DEV_ESM0 | esm_pls_event1 | 645 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 5 | J7200_DEV_ESM0 | esm_pls_event2 | 653 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 69 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 5 | J7200_DEV_R5FSS0_CORE0 | intr | 401 |
| J7200_DEV_R5FSS0_CORE1 | intr | 401 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 6 | J7200_DEV_ESM0 | esm_pls_event0 | 638 |
| J7200_DEV_ESM0 | esm_pls_event1 | 646 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 6 | J7200_DEV_ESM0 | esm_pls_event2 | 654 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 70 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 6 | J7200_DEV_R5FSS0_CORE0 | intr | 402 |
| J7200_DEV_R5FSS0_CORE1 | intr | 402 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 7 | J7200_DEV_ESM0 | esm_pls_event0 | 639 |
| J7200_DEV_ESM0 | esm_pls_event1 | 647 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 7 | J7200_DEV_ESM0 | esm_pls_event2 | 655 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 71 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 7 | J7200_DEV_R5FSS0_CORE0 | intr | 403 |
| J7200_DEV_R5FSS0_CORE1 | intr | 403 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 8 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 392 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 72 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 8 | J7200_DEV_R5FSS0_CORE0 | intr | 404 |
| J7200_DEV_R5FSS0_CORE1 | intr | 404 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 9 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 393 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 73 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 9 | J7200_DEV_R5FSS0_CORE0 | intr | 405 |
| J7200_DEV_R5FSS0_CORE1 | intr | 405 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 10 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 394 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 74 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 10 | J7200_DEV_R5FSS0_CORE0 | intr | 406 |
| J7200_DEV_R5FSS0_CORE1 | intr | 406 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 11 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 395 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 75 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 11 | J7200_DEV_R5FSS0_CORE0 | intr | 407 |
| J7200_DEV_R5FSS0_CORE1 | intr | 407 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 12 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 396 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 76 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 12 | J7200_DEV_R5FSS0_CORE0 | intr | 408 |
| J7200_DEV_R5FSS0_CORE1 | intr | 408 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 13 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 397 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 77 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 13 | J7200_DEV_R5FSS0_CORE0 | intr | 409 |
| J7200_DEV_R5FSS0_CORE1 | intr | 409 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 14 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 398 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 78 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 14 | J7200_DEV_R5FSS0_CORE0 | intr | 410 |
| J7200_DEV_R5FSS0_CORE1 | intr | 410 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 15 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 399 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 79 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 15 | J7200_DEV_R5FSS0_CORE0 | intr | 411 |
| J7200_DEV_R5FSS0_CORE1 | intr | 411 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 400 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 80 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 68 |
| J7200_DEV_R5FSS0_CORE0 | intr | 176 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J7200_DEV_R5FSS0_CORE1 | intr | 176 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 401 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 81 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 69 |
| J7200_DEV_R5FSS0_CORE0 | intr | 177 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J7200_DEV_R5FSS0_CORE1 | intr | 177 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 402 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 82 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 70 |
| J7200_DEV_R5FSS0_CORE0 | intr | 178 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J7200_DEV_R5FSS0_CORE1 | intr | 178 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 403 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 83 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 71 |
| J7200_DEV_R5FSS0_CORE0 | intr | 179 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J7200_DEV_R5FSS0_CORE1 | intr | 179 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 404 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 84 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 72 |
| J7200_DEV_R5FSS0_CORE0 | intr | 180 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J7200_DEV_R5FSS0_CORE1 | intr | 180 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 405 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 85 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 73 |
| J7200_DEV_R5FSS0_CORE0 | intr | 181 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J7200_DEV_R5FSS0_CORE1 | intr | 181 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 406 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 86 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 74 |
| J7200_DEV_R5FSS0_CORE0 | intr | 182 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J7200_DEV_R5FSS0_CORE1 | intr | 182 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 407 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 87 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 75 |
| J7200_DEV_R5FSS0_CORE0 | intr | 183 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J7200_DEV_R5FSS0_CORE1 | intr | 183 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 408 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 88 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 76 |
| J7200_DEV_R5FSS0_CORE0 | intr | 184 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J7200_DEV_R5FSS0_CORE1 | intr | 184 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 409 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 89 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 77 |
| J7200_DEV_R5FSS0_CORE0 | intr | 185 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J7200_DEV_R5FSS0_CORE1 | intr | 185 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 410 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 90 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 78 |
| J7200_DEV_R5FSS0_CORE0 | intr | 186 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J7200_DEV_R5FSS0_CORE1 | intr | 186 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 411 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 91 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 79 |
| J7200_DEV_R5FSS0_CORE0 | intr | 187 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J7200_DEV_R5FSS0_CORE1 | intr | 187 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 412 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 92 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 80 |
| J7200_DEV_R5FSS0_CORE0 | intr | 188 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J7200_DEV_R5FSS0_CORE1 | intr | 188 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 413 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 93 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 81 |
| J7200_DEV_R5FSS0_CORE0 | intr | 189 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J7200_DEV_R5FSS0_CORE1 | intr | 189 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 414 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 94 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 82 |
| J7200_DEV_R5FSS0_CORE0 | intr | 190 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J7200_DEV_R5FSS0_CORE1 | intr | 190 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 415 |
| J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 95 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 83 |
| J7200_DEV_R5FSS0_CORE0 | intr | 191 | |||
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J7200_DEV_R5FSS0_CORE1 | intr | 191 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 32 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 416 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 33 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 417 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 34 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 418 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 35 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 419 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 36 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 420 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 37 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 421 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 38 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 422 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 39 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 423 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 40 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 424 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 41 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 425 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 42 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 426 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 43 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 427 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 44 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 428 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 45 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 429 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 46 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 430 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 47 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 431 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 48 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 432 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 49 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 433 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 50 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 434 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 51 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 435 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 52 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 436 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 53 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 437 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 54 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 438 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 55 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 439 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 56 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 440 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 57 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 441 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 58 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 442 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 59 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 443 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 60 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 444 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 61 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 445 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 62 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 446 |
| J7200_DEV_GPIOMUX_INTRTR0 | 131 | 63 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 447 |
CMPEVENT_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 0 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 1 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 2 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 3 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 4 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 5 | J7200_DEV_PCIE1 | pcie_cpts_comp | 0 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 6 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 7 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 8 | J7200_DEV_NAVSS0 | cpts0_comp | 0 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 9 | J7200_DEV_CPSW0 | cpts_comp | 0 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 10 | J7200_DEV_MCU_CPSW0 | cpts_comp | 0 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 11 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 12 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 13 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 14 | Use TRM - Not managed by TISCI | ||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 15 | Use TRM - Not managed by TISCI |
CMPEVENT_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 0 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 544 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 1 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 545 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 2 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 546 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 3 | J7200_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 547 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 4 | J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 96 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 5 | J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 97 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 6 | J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 98 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 7 | J7200_DEV_MAIN2MCU_PLS_INTRTR0 | in | 99 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 8 | J7200_DEV_R5FSS0_CORE0 | intr | 326 |
| J7200_DEV_R5FSS0_CORE1 | intr | 326 | |||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 9 | J7200_DEV_R5FSS0_CORE0 | intr | 327 |
| J7200_DEV_R5FSS0_CORE1 | intr | 327 | |||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 10 | J7200_DEV_R5FSS0_CORE0 | intr | 328 |
| J7200_DEV_R5FSS0_CORE1 | intr | 328 | |||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 11 | J7200_DEV_R5FSS0_CORE0 | intr | 329 |
| J7200_DEV_R5FSS0_CORE1 | intr | 329 | |||
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 12 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 60 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 13 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 61 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 14 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 62 |
| J7200_DEV_CMPEVENT_INTRTR0 | 123 | 15 | J7200_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 63 |
Interrupt Aggregator Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on J7200 Device IDs these are the valid Interrupt Aggregator device IDs.
| Interrupt Aggregator Device Name | Interrupt Aggregator Device ID |
|---|---|
| J7200_DEV_NAVSS0_MODSS_INTA_0 | 207 |
| J7200_DEV_NAVSS0_MODSS_INTA_1 | 208 |
| J7200_DEV_NAVSS0_UDMASS_INTA_0 | 209 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 233 |
Interrupt Aggregator Virtual Interrupts¶
This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Interrupt Aggregator Name | Virtual Interrupt Range |
|---|---|
| J7200_DEV_NAVSS0_MODSS_INTA_0 | 0 to 63 |
| J7200_DEV_NAVSS0_MODSS_INTA_1 | 0 to 63 |
| J7200_DEV_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 17 |
| J7200_DEV_NAVSS0_UDMASS_INTA_0 | 18 to 255 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 14 |
| J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 15 to 255 |
Global Events¶
This section describes J7200 global events. The global events are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Global Event Name | Global Event Range |
|---|---|
| NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 0 to 17 |
| NAVSS0_UDMASS_INTA_0 SEVT | 18 to 4607 |
| MCU_NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 16384 to 16398 |
| MCU_NAVSS0_UDMASS_INTA_0 SEVT | 16399 to 17919 |
| NAVSS0_MODSS_INTA_0 SEVT | 20480 to 21503 |
| NAVSS0_MODSS_INTA_1 SEVT | 22528 to 23551 |
| NAVSS0_UDMASS_INTA_0 MEVT | 32768 to 33279 |
| MCU_NAVSS0_UDMASS_INTA_0 MEVT | 34816 to 34943 |
| NAVSS0_UDMASS_INTA_0 GEVT | 36864 to 37375 |
| MCU_NAVSS0_UDMASS_INTA_0 GEVT | 39936 to 40191 |
| NAVSS0_UDMAP_0 TRIGGER | 49152 to 50175 |
| MCU_NAVSS0_UDMAP_0 TRIGGER | 56320 to 56575 |
Event-Based Interrupt Source IDs¶
| Device Name | Device ID | Interrupt Source Name | Interrupt Source Index |
|---|---|---|---|
| J7200_DEV_NAVSS0_RINGACC_0 | 211 | Ring events | 0 to 973 |
| J7200_DEV_MCU_NAVSS0_RINGACC0 | 235 | Ring events | 0 to 255 |
| J7200_DEV_NAVSS0_RINGACC_0 | 211 | Ring monitor events | 1024 to 1055 |
| J7200_DEV_MCU_NAVSS0_RINGACC0 | 235 | Ring monitor events | 1024 to 1055 |
| J7200_DEV_NAVSS0_RINGACC_0 | 211 | Ring global error event | 2048 |
| J7200_DEV_MCU_NAVSS0_RINGACC0 | 235 | Ring global error event | 2048 |
| J7200_DEV_NAVSS0_UDMAP_0 | 212 | UDMA transmit channel OES events | 0 to 59 |
| J7200_DEV_NAVSS0_UDMAP_0 | 212 | UDMA transmit channel EOES events | 64 to 123 |
| J7200_DEV_NAVSS0_UDMAP_0 | 212 | UDMA receive channel OES events | 128 to 187 |
| J7200_DEV_NAVSS0_UDMAP_0 | 212 | UDMA receive channel EOES events | 192 to 251 |
| J7200_DEV_NAVSS0_UDMAP_0 | 212 | UDMA global configuration invalid flow event | 256 |
| J7200_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA transmit channel OES events | 0 to 47 |
| J7200_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA transmit channel EOES events | 64 to 111 |
| J7200_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA receive channel OES events | 128 to 175 |
| J7200_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA receive channel EOES events | 192 to 239 |
| J7200_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA global configuration invalid flow event | 256 |