J7200 Clock Identifiers

Clock for J7200 Device

This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in J7200 SoC.

TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.

Device wise clock ID list for J7200 SoC

This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs

The following table describes functions implemented by clocks

Function Description
Input clock Clock input to the SoC subsystem
Output clock Clock output from the SoC subsystem
Input muxed clock Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source
Parent input clock option to XYZ One of the parent clocks that can be used as a source clock to a input muxed clock

Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:

This device has no defined clocks.

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

Clocks for A72SS0_CORE0 Device

Device: J7200_DEV_A72SS0_CORE0 (ID = 4)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A72SS0_CORE0_ARM_CLK_CLK Input clock
1 DEV_A72SS0_CORE0_MSMC_CLK Input clock
2 DEV_A72SS0_CORE0_PLL_CTRL_CLK Input clock

Clocks for A72SS0_CORE0_0 Device

Device: J7200_DEV_A72SS0_CORE0_0 (ID = 202)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_A72SS0_CORE0_0_ARM_CLK_CLK Input clock

Clocks for A72SS0_CORE0_1 Device

Device: J7200_DEV_A72SS0_CORE0_1 (ID = 203)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A72SS0_CORE0_1_ARM_CLK_CLK Input clock

Clocks for ATL0 Device

Device: J7200_DEV_ATL0 (ID = 2)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ATL0_VBUS_CLK Input clock
1 DEV_ATL0_ATL_CLK Input muxed clock
2 DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK Parent input clock option to DEV_ATL0_ATL_CLK
3 DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_ATL0_ATL_CLK
6 DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_ATL0_ATL_CLK
7 DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_ATL0_ATL_CLK
8 DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_ATL0_ATL_CLK
10 DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 Output clock
11 DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 Output clock
12 DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 Output clock
13 DEV_ATL0_ATL_IO_PORT_ATCLK_OUT Output clock

Clocks for BOARD0 Device

Device: J7200_DEV_BOARD0 (ID = 157)

Note

BOARD0 is a special device that represents the board on which the SoC is mounted.

Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.

Function documented here implies:

Function Description
Input clock Clock is supplied from SoC to the board (It is an output of the SoC)
Output clock Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)

NOTE: Clocks which can be bi-directional are listed as Output clock

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_BOARD0_I2C1_SCL_OUT Output clock
2 DEV_BOARD0_MCASP0_ACLKR_OUT Output clock
3 DEV_BOARD0_SPI2_CLK_IN Input clock
4 DEV_BOARD0_I2C3_SCL_OUT Output clock
5 DEV_BOARD0_OBSCLK2_IN Input clock
6 DEV_BOARD0_MCU_I3C0_SCL_IN Input clock
7 DEV_BOARD0_MCU_HYPERBUS0_CKN_IN Input clock
8 DEV_BOARD0_I2C4_SCL_OUT Output clock
9 DEV_BOARD0_RGMII3_TXC_IN Input clock
11 DEV_BOARD0_EXT_REFCLK1_OUT Output clock
12 DEV_BOARD0_SPI1_CLK_IN Input clock
13 DEV_BOARD0_GPMC0_CLKOUT_IN Input clock
14 DEV_BOARD0_MCU_OBSCLK0_IN Input muxed clock
15 DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
16 DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
31 DEV_BOARD0_MCU_I3C0_SCL_OUT Output clock
32 DEV_BOARD0_SPI3_CLK_IN Input clock
33 DEV_BOARD0_MCASP0_ACLKX_OUT Output clock
34 DEV_BOARD0_MCASP1_ACLKR_IN Input clock
35 DEV_BOARD0_CLKOUT_IN Input muxed clock
36 DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5 Parent input clock option to DEV_BOARD0_CLKOUT_IN
37 DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10 Parent input clock option to DEV_BOARD0_CLKOUT_IN
38 DEV_BOARD0_OBSCLK1_IN Input clock
39 DEV_BOARD0_MCU_RMII1_REF_CLK_OUT Output clock
40 DEV_BOARD0_GPMC0_CLK_OUT Output clock
41 DEV_BOARD0_I3C0_SCL_OUT Output clock
43 DEV_BOARD0_TCK_OUT Output clock
44 DEV_BOARD0_HFOSC1_CLK_OUT Output clock
45 DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT Output clock
46 DEV_BOARD0_I2C6_SCL_OUT Output clock
48 DEV_BOARD0_I2C5_SCL_OUT Output clock
49 DEV_BOARD0_MCU_OSPI0_DQS_OUT Output clock
52 DEV_BOARD0_RGMII2_RXC_OUT Output clock
53 DEV_BOARD0_MCASP2_ACLKX_IN Input clock
54 DEV_BOARD0_I2C0_SCL_OUT Output clock
57 DEV_BOARD0_MCU_HYPERBUS0_CK_IN Input clock
59 DEV_BOARD0_MCASP1_ACLKX_OUT Output clock
61 DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT Output clock
62 DEV_BOARD0_MDIO0_MDC_IN Input clock
63 DEV_BOARD0_RGMII1_TXC_IN Input clock
65 DEV_BOARD0_MMC1_CLK_IN Input clock
66 DEV_BOARD0_MCASP2_ACLKR_IN Input clock
68 DEV_BOARD0_WKUP_I2C0_SCL_OUT Output clock
69 DEV_BOARD0_MCU_CLKOUT0_IN Input muxed clock
70 DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN
71 DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN
73 DEV_BOARD0_MCASP0_ACLKR_IN Input clock
74 DEV_BOARD0_MCU_MDIO0_MDC_IN Input clock
77 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN Input muxed clock
78 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
79 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
80 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
90 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
91 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
92 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
102 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
103 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
104 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
105 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
106 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
110 DEV_BOARD0_MCU_OSPI0_CLK_IN Input clock
114 DEV_BOARD0_MCU_SYSCLKOUT0_IN Input clock
115 DEV_BOARD0_RGMII1_RXC_OUT Output clock
116 DEV_BOARD0_LED_CLK_OUT Output clock
118 DEV_BOARD0_RGMII2_TXC_IN Input clock
119 DEV_BOARD0_I3C0_SCL_IN Input clock
120 DEV_BOARD0_MCU_I2C0_SCL_OUT Output clock
122 DEV_BOARD0_SPI6_CLK_IN Input clock
123 DEV_BOARD0_WKUP_I2C0_SCL_IN Input clock
124 DEV_BOARD0_WKUP_LF_CLKIN_OUT Output clock
126 DEV_BOARD0_MCU_SPI1_CLK_IN Input clock
127 DEV_BOARD0_MCASP0_ACLKX_IN Input clock
128 DEV_BOARD0_MCASP1_ACLKX_IN Input clock
130 DEV_BOARD0_MCU_SPI0_CLK_IN Input clock
131 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN Input muxed clock
132 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
133 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
134 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
144 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
145 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
146 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
156 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
157 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
158 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
159 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
160 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
164 DEV_BOARD0_MCU_RGMII1_TXC_IN Input clock
165 DEV_BOARD0_CPTS0_RFT_CLK_OUT Output clock
166 DEV_BOARD0_MCU_I2C1_SCL_OUT Output clock
168 DEV_BOARD0_MCASP2_ACLKR_OUT Output clock
169 DEV_BOARD0_MCU_I2C0_SCL_IN Input clock
170 DEV_BOARD0_RMII_REF_CLK_OUT Output clock
171 DEV_BOARD0_GPMC0_CLK_IN Input clock
172 DEV_BOARD0_TRC_CLK_IN Input clock
174 DEV_BOARD0_MCASP2_ACLKX_OUT Output clock
176 DEV_BOARD0_RGMII4_RXC_OUT Output clock
177 DEV_BOARD0_SYSCLKOUT0_IN Input clock
178 DEV_BOARD0_MCASP1_ACLKR_OUT Output clock
179 DEV_BOARD0_SPI5_CLK_IN Input clock
180 DEV_BOARD0_MCU_RGMII1_RXC_OUT Output clock
181 DEV_BOARD0_RGMII3_RXC_OUT Output clock
183 DEV_BOARD0_SPI0_CLK_IN Input clock
184 DEV_BOARD0_GPMC0_FCLK_MUX_IN Input clock
185 DEV_BOARD0_I2C2_SCL_OUT Output clock
186 DEV_BOARD0_MCU_EXT_REFCLK0_OUT Output clock
187 DEV_BOARD0_MCU_OSPI0_LBCLKO_IN Input clock
189 DEV_BOARD0_SPI7_CLK_IN Input clock
190 DEV_BOARD0_RGMII4_TXC_IN Input clock
191 DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT Output clock
192 DEV_BOARD0_OBSCLK0_IN Input clock
193 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
194 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
195 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
196 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
197 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
205 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
206 DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
207 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
219 DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
220 DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
221 DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_BOARD0_OBSCLK0_IN
222 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
223 DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_BOARD0_OBSCLK0_IN
224 DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_OBSCLK0_IN

Clocks for CMPEVENT_INTRTR0 Device

Device: J7200_DEV_CMPEVENT_INTRTR0 (ID = 123)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CMPEVENT_INTRTR0_INTR_CLK Input clock

Clocks for COMPUTE_CLUSTER0 Device

Device: J7200_DEV_COMPUTE_CLUSTER0 (ID = 3)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK Input clock
2 DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK Input clock
3 DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK Input clock
4 DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK Input clock
5 DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK Input clock
6 DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK Input clock

Clocks for COMPUTE_CLUSTER0_CFG_WRAP Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_CLEC Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_CORE_CORE Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DEBUG_WRAP Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_DMSC_WRAP Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_EN_MSMC_DOMAIN Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_GIC500SS Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_PBIST_WRAP Device

Device: J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP (ID = 17)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
4 DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK Input clock

Clocks for CPSW0 Device

Device: J7200_DEV_CPSW0 (ID = 19)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPSW0_MDIO_MDCLK_O Output clock
1 DEV_CPSW0_GMII3_MT_CLK Input clock
2 DEV_CPSW0_GMII2_MR_CLK Input clock
3 DEV_CPSW0_SERDES4_RXCLK Input clock
4 DEV_CPSW0_CPTS_GENF0 Output clock
5 DEV_CPSW0_PRE_RGMII4_TCLK Output clock
6 DEV_CPSW0_RGMII3_RXC_I Input clock
7 DEV_CPSW0_RGMII4_RXC_I Input clock
8 DEV_CPSW0_PRE_RGMII3_TCLK Output clock
9 DEV_CPSW0_RGMII1_RXC_I Input clock
10 DEV_CPSW0_RGMII_MHZ_250_CLK Input clock
11 DEV_CPSW0_GMII4_MT_CLK Input clock
13 DEV_CPSW0_GMII3_MR_CLK Input clock
14 DEV_CPSW0_SERDES4_RXFCLK Input clock
15 DEV_CPSW0_CPTS_RFT_CLK Input muxed clock
16 DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
17 DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
18 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
19 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
20 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
21 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
22 DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
23 DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
24 DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
25 DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
30 DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
31 DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
32 DEV_CPSW0_SERDES1_TXCLK Output clock
33 DEV_CPSW0_CPPI_CLK_CLK Input clock
34 DEV_CPSW0_SERDES2_RXCLK Input clock
35 DEV_CPSW0_SERDES1_RXFCLK Input clock
36 DEV_CPSW0_GMII_RFT_CLK Input clock
37 DEV_CPSW0_SERDES1_TXMCLK Input clock
38 DEV_CPSW0_SERDES1_REFCLK Input clock
39 DEV_CPSW0_RMII_MHZ_50_CLK Input clock
40 DEV_CPSW0_GMII4_MR_CLK Input clock
41 DEV_CPSW0_RGMII_MHZ_50_CLK Input clock
42 DEV_CPSW0_SERDES3_TXFCLK Input clock
43 DEV_CPSW0_SERDES3_RXFCLK Input clock
45 DEV_CPSW0_PRE_RGMII2_TCLK Output clock
46 DEV_CPSW0_SERDES2_TXCLK Output clock
47 DEV_CPSW0_SERDES1_RXCLK Input clock
48 DEV_CPSW0_SERDES1_TXFCLK Input clock
49 DEV_CPSW0_RGMII2_RXC_I Input clock
50 DEV_CPSW0_SERDES2_TXFCLK Input clock
51 DEV_CPSW0_PRE_RGMII1_TCLK Output clock
52 DEV_CPSW0_RGMII_MHZ_5_CLK Input clock
53 DEV_CPSW0_GMII2_MT_CLK Input clock
54 DEV_CPSW0_SERDES4_TXMCLK Input clock
55 DEV_CPSW0_SERDES3_TXCLK Output clock
56 DEV_CPSW0_SERDES2_TXMCLK Input clock
57 DEV_CPSW0_GMII1_MR_CLK Input clock
58 DEV_CPSW0_SERDES4_REFCLK Input clock
59 DEV_CPSW0_SERDES3_TXMCLK Input clock
60 DEV_CPSW0_SERDES2_REFCLK Input clock
61 DEV_CPSW0_SERDES3_REFCLK Input clock
62 DEV_CPSW0_SERDES3_RXCLK Input clock
63 DEV_CPSW0_GMII1_MT_CLK Input clock
64 DEV_CPSW0_SERDES2_RXFCLK Input clock
66 DEV_CPSW0_SERDES4_TXCLK Output clock
67 DEV_CPSW0_SERDES4_TXFCLK Input clock

Clocks for CPSW_TX_RGMII0 Device

Device: J7200_DEV_CPSW_TX_RGMII0 (ID = 26)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A Output clock
1 DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A Output clock
2 DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A Output clock
3 DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A Output clock
4 DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK Input clock
5 DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK Input clock
6 DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK Input clock
7 DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK Input clock

Clocks for CPT2_AGGR0 Device

Device: J7200_DEV_CPT2_AGGR0 (ID = 20)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR0_VCLK_CLK Input clock

Clocks for CPT2_AGGR1 Device

Device: J7200_DEV_CPT2_AGGR1 (ID = 21)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR1_VCLK_CLK Input clock

Clocks for CPT2_AGGR2 Device

Device: J7200_DEV_CPT2_AGGR2 (ID = 23)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR2_VCLK_CLK Input clock

Clocks for CPT2_AGGR3 Device

Device: J7200_DEV_CPT2_AGGR3 (ID = 25)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR3_VCLK_CLK Input clock

Clocks for DCC0 Device

Device: J7200_DEV_DCC0 (ID = 30)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC0_DCC_INPUT10_CLK Input clock
1 DEV_DCC0_DCC_INPUT01_CLK Input clock
2 DEV_DCC0_DCC_CLKSRC2_CLK Input clock
4 DEV_DCC0_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC0_VBUS_CLK Input clock
6 DEV_DCC0_DCC_CLKSRC4_CLK Input clock
7 DEV_DCC0_DCC_CLKSRC1_CLK Input clock
8 DEV_DCC0_DCC_CLKSRC3_CLK Input clock
9 DEV_DCC0_DCC_INPUT00_CLK Input clock
10 DEV_DCC0_DCC_CLKSRC5_CLK Input clock
11 DEV_DCC0_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC0_DCC_INPUT02_CLK Input clock

Clocks for DCC1 Device

Device: J7200_DEV_DCC1 (ID = 31)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC1_DCC_INPUT10_CLK Input clock
1 DEV_DCC1_DCC_INPUT01_CLK Input clock
2 DEV_DCC1_DCC_CLKSRC2_CLK Input clock
4 DEV_DCC1_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC1_VBUS_CLK Input clock
6 DEV_DCC1_DCC_CLKSRC4_CLK Input clock
7 DEV_DCC1_DCC_CLKSRC1_CLK Input clock
8 DEV_DCC1_DCC_CLKSRC3_CLK Input clock
9 DEV_DCC1_DCC_INPUT00_CLK Input clock
10 DEV_DCC1_DCC_CLKSRC5_CLK Input clock
11 DEV_DCC1_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC1_DCC_INPUT02_CLK Input clock

Clocks for DCC2 Device

Device: J7200_DEV_DCC2 (ID = 32)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC2_DCC_INPUT10_CLK Input clock
1 DEV_DCC2_DCC_INPUT01_CLK Input clock
2 DEV_DCC2_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC2_DCC_CLKSRC7_CLK Input clock
4 DEV_DCC2_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC2_VBUS_CLK Input clock
6 DEV_DCC2_DCC_CLKSRC4_CLK Input clock
8 DEV_DCC2_DCC_CLKSRC3_CLK Input clock
9 DEV_DCC2_DCC_INPUT00_CLK Input clock
10 DEV_DCC2_DCC_CLKSRC5_CLK Input clock
11 DEV_DCC2_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC2_DCC_INPUT02_CLK Input clock

Clocks for DCC3 Device

Device: J7200_DEV_DCC3 (ID = 33)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC3_DCC_INPUT10_CLK Input clock
1 DEV_DCC3_DCC_INPUT01_CLK Input clock
2 DEV_DCC3_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC3_DCC_CLKSRC7_CLK Input clock
4 DEV_DCC3_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC3_VBUS_CLK Input clock
6 DEV_DCC3_DCC_CLKSRC4_CLK Input clock
8 DEV_DCC3_DCC_CLKSRC3_CLK Input clock
9 DEV_DCC3_DCC_INPUT00_CLK Input clock
10 DEV_DCC3_DCC_CLKSRC5_CLK Input clock
11 DEV_DCC3_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC3_DCC_INPUT02_CLK Input clock

Clocks for DCC4 Device

Device: J7200_DEV_DCC4 (ID = 34)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC4_DCC_INPUT10_CLK Input clock
1 DEV_DCC4_DCC_INPUT01_CLK Input clock
2 DEV_DCC4_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC4_DCC_CLKSRC7_CLK Input clock
4 DEV_DCC4_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC4_VBUS_CLK Input clock
6 DEV_DCC4_DCC_CLKSRC4_CLK Input clock
7 DEV_DCC4_DCC_CLKSRC1_CLK Input clock
8 DEV_DCC4_DCC_CLKSRC3_CLK Input clock
9 DEV_DCC4_DCC_INPUT00_CLK Input clock
10 DEV_DCC4_DCC_CLKSRC5_CLK Input clock
11 DEV_DCC4_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC4_DCC_INPUT02_CLK Input clock

Clocks for DCC5 Device

Device: J7200_DEV_DCC5 (ID = 36)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC5_DCC_INPUT10_CLK Input clock
1 DEV_DCC5_DCC_INPUT01_CLK Input clock
4 DEV_DCC5_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC5_VBUS_CLK Input clock
6 DEV_DCC5_DCC_CLKSRC4_CLK Input clock
7 DEV_DCC5_DCC_CLKSRC1_CLK Input clock
9 DEV_DCC5_DCC_INPUT00_CLK Input clock
11 DEV_DCC5_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC5_DCC_INPUT02_CLK Input clock

Clocks for DCC6 Device

Device: J7200_DEV_DCC6 (ID = 37)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC6_DCC_INPUT10_CLK Input clock
1 DEV_DCC6_DCC_INPUT01_CLK Input clock
2 DEV_DCC6_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC6_DCC_CLKSRC7_CLK Input clock
4 DEV_DCC6_DCC_CLKSRC0_CLK Input clock
5 DEV_DCC6_VBUS_CLK Input clock
6 DEV_DCC6_DCC_CLKSRC4_CLK Input clock
7 DEV_DCC6_DCC_CLKSRC1_CLK Input clock
8 DEV_DCC6_DCC_CLKSRC3_CLK Input clock
9 DEV_DCC6_DCC_INPUT00_CLK Input clock
10 DEV_DCC6_DCC_CLKSRC5_CLK Input clock
11 DEV_DCC6_DCC_CLKSRC6_CLK Input clock
12 DEV_DCC6_DCC_INPUT02_CLK Input clock

Clocks for DDR0 Device

Device: J7200_DEV_DDR0 (ID = 8)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DDR0_PLL_CTRL_CLK Input clock
5 DEV_DDR0_DDRSS_DDR_PLL_CLK Input clock

Clocks for DEBUGSS_WRAP0 Device

Device: J7200_DEV_DEBUGSS_WRAP0 (ID = 304)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
5 DEV_DEBUGSS_WRAP0_TREXPT_CLK Input clock
9 DEV_DEBUGSS_WRAP0_CORE_CLK Input clock
25 DEV_DEBUGSS_WRAP0_JTAG_TCK Input clock
34 DEV_DEBUGSS_WRAP0_ATB_CLK Input clock
49 DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK Output clock

Clocks for ECAP0 Device

Device: J7200_DEV_ECAP0 (ID = 80)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP0_VBUS_CLK Input clock

Clocks for ECAP1 Device

Device: J7200_DEV_ECAP1 (ID = 81)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP1_VBUS_CLK Input clock

Clocks for ECAP2 Device

Device: J7200_DEV_ECAP2 (ID = 82)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP2_VBUS_CLK Input clock

Clocks for EHRPWM0 Device

Device: J7200_DEV_EHRPWM0 (ID = 83)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EHRPWM0_VBUSP_CLK Input clock

Clocks for EHRPWM1 Device

Device: J7200_DEV_EHRPWM1 (ID = 84)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EHRPWM1_VBUSP_CLK Input clock

Clocks for EHRPWM2 Device

Device: J7200_DEV_EHRPWM2 (ID = 85)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EHRPWM2_VBUSP_CLK Input clock

Clocks for EHRPWM3 Device

Device: J7200_DEV_EHRPWM3 (ID = 86)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EHRPWM3_VBUSP_CLK Input clock

Clocks for EHRPWM4 Device

Device: J7200_DEV_EHRPWM4 (ID = 87)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EHRPWM4_VBUSP_CLK Input clock

Clocks for EHRPWM5 Device

Device: J7200_DEV_EHRPWM5 (ID = 88)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EHRPWM5_VBUSP_CLK Input clock

Clocks for ELM0 Device

Device: J7200_DEV_ELM0 (ID = 89)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ELM0_VBUSP_CLK Input clock

Clocks for EMIF_DATA_0_VD Device

This device has no defined clocks.

Clocks for EQEP0 Device

Device: J7200_DEV_EQEP0 (ID = 94)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP0_VBUS_CLK Input clock

Clocks for EQEP1 Device

Device: J7200_DEV_EQEP1 (ID = 95)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP1_VBUS_CLK Input clock

Clocks for EQEP2 Device

Device: J7200_DEV_EQEP2 (ID = 96)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP2_VBUS_CLK Input clock

Clocks for ESM0 Device

Device: J7200_DEV_ESM0 (ID = 97)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ESM0_CLK Input clock

Clocks for FFI_MAIN_INFRA_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_IP_CBASS_VD Device

This device has no defined clocks.

Clocks for FFI_MAIN_RC_CBASS_VD Device

This device has no defined clocks.

Clocks for GPIO0 Device

Device: J7200_DEV_GPIO0 (ID = 105)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO0_MMR_CLK Input clock

Clocks for GPIO2 Device

Device: J7200_DEV_GPIO2 (ID = 107)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO2_MMR_CLK Input clock

Clocks for GPIO4 Device

Device: J7200_DEV_GPIO4 (ID = 109)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO4_MMR_CLK Input clock

Clocks for GPIO6 Device

Device: J7200_DEV_GPIO6 (ID = 111)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO6_MMR_CLK Input clock

Clocks for GPIOMUX_INTRTR0 Device

Device: J7200_DEV_GPIOMUX_INTRTR0 (ID = 131)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIOMUX_INTRTR0_INTR_CLK Input clock

Clocks for GPMC0 Device

Device: J7200_DEV_GPMC0 (ID = 115)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPMC0_FUNC_CLK Input muxed clock
1 DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK Parent input clock option to DEV_GPMC0_FUNC_CLK
2 DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 Parent input clock option to DEV_GPMC0_FUNC_CLK
3 DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 Parent input clock option to DEV_GPMC0_FUNC_CLK
4 DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_GPMC0_FUNC_CLK
5 DEV_GPMC0_VBUSP_CLK Input clock
6 DEV_GPMC0_PO_GPMC_DEV_CLK Output clock
7 DEV_GPMC0_PI_GPMC_RET_CLK Input clock

Clocks for GTC0 Device

Device: J7200_DEV_GTC0 (ID = 61)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GTC0_VBUSP_CLK Input clock
1 DEV_GTC0_GTC_CLK Input muxed clock
2 DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK Parent input clock option to DEV_GTC0_GTC_CLK
3 DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_GTC0_GTC_CLK
4 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_GTC0_GTC_CLK
5 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_GTC0_GTC_CLK
6 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_GTC0_GTC_CLK
7 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_GTC0_GTC_CLK
8 DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK Parent input clock option to DEV_GTC0_GTC_CLK
9 DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK Parent input clock option to DEV_GTC0_GTC_CLK
10 DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK Parent input clock option to DEV_GTC0_GTC_CLK
11 DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK Parent input clock option to DEV_GTC0_GTC_CLK
16 DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK Parent input clock option to DEV_GTC0_GTC_CLK
17 DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_GTC0_GTC_CLK

Clocks for I2C0 Device

Device: J7200_DEV_I2C0 (ID = 187)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C0_PISCL Input clock
1 DEV_I2C0_PISYS_CLK Input clock
2 DEV_I2C0_CLK Input clock
3 DEV_I2C0_PORSCL Output clock

Clocks for I2C1 Device

Device: J7200_DEV_I2C1 (ID = 188)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C1_PISCL Input clock
1 DEV_I2C1_PISYS_CLK Input clock
2 DEV_I2C1_CLK Input clock
3 DEV_I2C1_PORSCL Output clock

Clocks for I2C2 Device

Device: J7200_DEV_I2C2 (ID = 189)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C2_PISCL Input clock
1 DEV_I2C2_PISYS_CLK Input clock
2 DEV_I2C2_CLK Input clock
3 DEV_I2C2_PORSCL Output clock

Clocks for I2C3 Device

Device: J7200_DEV_I2C3 (ID = 190)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C3_PISCL Input clock
1 DEV_I2C3_PISYS_CLK Input clock
2 DEV_I2C3_CLK Input clock
3 DEV_I2C3_PORSCL Output clock

Clocks for I2C4 Device

Device: J7200_DEV_I2C4 (ID = 191)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C4_PISCL Input clock
1 DEV_I2C4_PISYS_CLK Input clock
2 DEV_I2C4_CLK Input clock
3 DEV_I2C4_PORSCL Output clock

Clocks for I2C5 Device

Device: J7200_DEV_I2C5 (ID = 192)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C5_PISCL Input clock
1 DEV_I2C5_PISYS_CLK Input clock
2 DEV_I2C5_CLK Input clock
3 DEV_I2C5_PORSCL Output clock

Clocks for I2C6 Device

Device: J7200_DEV_I2C6 (ID = 193)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C6_PISCL Input clock
1 DEV_I2C6_PISYS_CLK Input clock
2 DEV_I2C6_CLK Input clock
3 DEV_I2C6_PORSCL Output clock

Clocks for I3C0 Device

Device: J7200_DEV_I3C0 (ID = 116)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I3C0_I3C_SCL_DI Input clock
1 DEV_I3C0_I3C_SCL_DO Output clock
2 DEV_I3C0_I3C_PCLK_CLK Input clock
4 DEV_I3C0_I3C_SCLK_CLK Input clock

Clocks for LED0 Device

Device: J7200_DEV_LED0 (ID = 127)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_LED0_LED_CLK Input clock
1 DEV_LED0_VBUS_CLK Input clock

Clocks for MAIN0 Device

This device has no defined clocks.

Clocks for MAIN2MCU_LVL_INTRTR0 Device

This device has no defined clocks.

Clocks for MAIN2MCU_PLS_INTRTR0 Device

This device has no defined clocks.

Clocks for MAIN2WKUPMCU_VD Device

This device has no defined clocks.

Clocks for MAIN_PLL8_SEL_EXTWAVE_VD Device

Device: J7200_DEV_MAIN_PLL8_SEL_EXTWAVE_VD (ID = 323)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK Input muxed clock
1 DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_PLLFRACF_SSMOD_16FFT_MAIN_8_FOUTVCOP_CLK Parent input clock option to DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK
2 DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK Parent input clock option to DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK

Clocks for MCAN0 Device

Device: J7200_DEV_MCAN0 (ID = 156)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN0_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN0_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
4 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
5 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
6 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK

Clocks for MCAN1 Device

Device: J7200_DEV_MCAN1 (ID = 158)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN1_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN1_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
4 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
5 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
6 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK

Clocks for MCAN10 Device

Device: J7200_DEV_MCAN10 (ID = 168)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN10_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN10_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
4 DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
5 DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK
6 DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK

Clocks for MCAN11 Device

Device: J7200_DEV_MCAN11 (ID = 169)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN11_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN11_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
4 DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
5 DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK
6 DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK

Clocks for MCAN12 Device

Device: J7200_DEV_MCAN12 (ID = 170)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN12_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN12_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
4 DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
5 DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK
6 DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK

Clocks for MCAN13 Device

Device: J7200_DEV_MCAN13 (ID = 171)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN13_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN13_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
4 DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
5 DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK
6 DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK

Clocks for MCAN14 Device

Device: J7200_DEV_MCAN14 (ID = 150)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN14_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN14_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
4 DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
5 DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK
6 DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK

Clocks for MCAN15 Device

Device: J7200_DEV_MCAN15 (ID = 151)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN15_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN15_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
4 DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
5 DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK
6 DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK

Clocks for MCAN16 Device

Device: J7200_DEV_MCAN16 (ID = 152)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN16_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN16_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
4 DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
5 DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK
6 DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK

Clocks for MCAN17 Device

Device: J7200_DEV_MCAN17 (ID = 153)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN17_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN17_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
4 DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
5 DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK
6 DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK

Clocks for MCAN2 Device

Device: J7200_DEV_MCAN2 (ID = 160)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN2_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN2_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
4 DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
5 DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK
6 DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK

Clocks for MCAN3 Device

Device: J7200_DEV_MCAN3 (ID = 161)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN3_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN3_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
4 DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
5 DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK
6 DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK

Clocks for MCAN4 Device

Device: J7200_DEV_MCAN4 (ID = 162)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN4_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN4_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
4 DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
5 DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK
6 DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK

Clocks for MCAN5 Device

Device: J7200_DEV_MCAN5 (ID = 163)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN5_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN5_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
4 DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
5 DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK
6 DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK

Clocks for MCAN6 Device

Device: J7200_DEV_MCAN6 (ID = 164)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN6_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN6_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
4 DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
5 DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK
6 DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK

Clocks for MCAN7 Device

Device: J7200_DEV_MCAN7 (ID = 165)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN7_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN7_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
4 DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
5 DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK
6 DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK

Clocks for MCAN8 Device

Device: J7200_DEV_MCAN8 (ID = 166)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN8_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN8_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
4 DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
5 DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK
6 DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK

Clocks for MCAN9 Device

Device: J7200_DEV_MCAN9 (ID = 167)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN9_MCANSS_HCLK_CLK Input clock
2 DEV_MCAN9_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
4 DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
5 DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK
6 DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK

Clocks for MCASP0 Device

Device: J7200_DEV_MCASP0 (ID = 174)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCASP0_MCASP_AHCLKX_POUT Output clock
2 DEV_MCASP0_MCASP_AHCLKR_PIN Input muxed clock
3 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
4 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
5 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
6 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
11 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
12 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
13 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
14 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
19 DEV_MCASP0_MCASP_ACLKR_PIN Input clock
21 DEV_MCASP0_MCASP_AHCLKX_PIN Input muxed clock
22 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
23 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
24 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
25 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
30 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
31 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
32 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
33 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
38 DEV_MCASP0_MCASP_AHCLKR_POUT Output clock
39 DEV_MCASP0_MCASP_ACLKX_PIN Input clock
40 DEV_MCASP0_AUX_CLK Input muxed clock
41 DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK Parent input clock option to DEV_MCASP0_AUX_CLK
42 DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCASP0_AUX_CLK
45 DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP0_AUX_CLK
46 DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP0_AUX_CLK
47 DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP0_AUX_CLK
48 DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP0_AUX_CLK
49 DEV_MCASP0_VBUSP_CLK Input clock
50 DEV_MCASP0_MCASP_ACLKR_POUT Output clock
51 DEV_MCASP0_MCASP_ACLKX_POUT Output clock

Clocks for MCASP1 Device

Device: J7200_DEV_MCASP1 (ID = 175)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCASP1_MCASP_AHCLKX_POUT Output clock
2 DEV_MCASP1_MCASP_AHCLKR_PIN Input muxed clock
3 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
4 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
5 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
6 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
11 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
12 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
13 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
14 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
19 DEV_MCASP1_MCASP_ACLKR_PIN Input clock
21 DEV_MCASP1_MCASP_AHCLKX_PIN Input muxed clock
22 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
23 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
24 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
25 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
30 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
31 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
32 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
33 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
38 DEV_MCASP1_MCASP_AHCLKR_POUT Output clock
39 DEV_MCASP1_MCASP_ACLKX_PIN Input clock
40 DEV_MCASP1_AUX_CLK Input muxed clock
41 DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK Parent input clock option to DEV_MCASP1_AUX_CLK
42 DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCASP1_AUX_CLK
45 DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP1_AUX_CLK
46 DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP1_AUX_CLK
47 DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP1_AUX_CLK
48 DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP1_AUX_CLK
49 DEV_MCASP1_VBUSP_CLK Input clock
50 DEV_MCASP1_MCASP_ACLKR_POUT Output clock
51 DEV_MCASP1_MCASP_ACLKX_POUT Output clock

Clocks for MCASP2 Device

Device: J7200_DEV_MCASP2 (ID = 176)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCASP2_MCASP_AHCLKX_POUT Output clock
2 DEV_MCASP2_MCASP_AHCLKR_PIN Input muxed clock
3 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
4 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
5 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
6 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
11 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
12 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
13 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
14 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
19 DEV_MCASP2_MCASP_ACLKR_PIN Input clock
21 DEV_MCASP2_MCASP_AHCLKX_PIN Input muxed clock
22 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
23 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
24 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
25 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
30 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
31 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
32 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
33 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
38 DEV_MCASP2_MCASP_AHCLKR_POUT Output clock
39 DEV_MCASP2_MCASP_ACLKX_PIN Input clock
40 DEV_MCASP2_AUX_CLK Input muxed clock
41 DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK Parent input clock option to DEV_MCASP2_AUX_CLK
42 DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCASP2_AUX_CLK
45 DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT Parent input clock option to DEV_MCASP2_AUX_CLK
46 DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 Parent input clock option to DEV_MCASP2_AUX_CLK
47 DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 Parent input clock option to DEV_MCASP2_AUX_CLK
48 DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 Parent input clock option to DEV_MCASP2_AUX_CLK
49 DEV_MCASP2_VBUSP_CLK Input clock
50 DEV_MCASP2_MCASP_ACLKR_POUT Output clock
51 DEV_MCASP2_MCASP_ACLKX_POUT Output clock

Clocks for MCSPI0 Device

Device: J7200_DEV_MCSPI0 (ID = 266)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCSPI0_VBUSP_CLK Input clock
4 DEV_MCSPI0_CLKSPIREF_CLK Input clock
5 DEV_MCSPI0_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI1 Device

Device: J7200_DEV_MCSPI1 (ID = 267)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCSPI1_VBUSP_CLK Input clock
4 DEV_MCSPI1_CLKSPIREF_CLK Input clock
5 DEV_MCSPI1_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI2 Device

Device: J7200_DEV_MCSPI2 (ID = 268)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCSPI2_VBUSP_CLK Input clock
4 DEV_MCSPI2_CLKSPIREF_CLK Input clock
5 DEV_MCSPI2_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI3 Device

Device: J7200_DEV_MCSPI3 (ID = 269)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI3_IO_CLKSPII_CLK Input muxed clock
1 DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK
3 DEV_MCSPI3_VBUSP_CLK Input clock
4 DEV_MCSPI3_CLKSPIREF_CLK Input clock
5 DEV_MCSPI3_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI4 Device

Device: J7200_DEV_MCSPI4 (ID = 270)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI4_IO_CLKSPII_CLK Input clock
1 DEV_MCSPI4_VBUSP_CLK Input clock
2 DEV_MCSPI4_CLKSPIREF_CLK Input clock
3 DEV_MCSPI4_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI5 Device

Device: J7200_DEV_MCSPI5 (ID = 271)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCSPI5_VBUSP_CLK Input clock
4 DEV_MCSPI5_CLKSPIREF_CLK Input clock
5 DEV_MCSPI5_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI6 Device

Device: J7200_DEV_MCSPI6 (ID = 272)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCSPI6_VBUSP_CLK Input clock
4 DEV_MCSPI6_CLKSPIREF_CLK Input clock
5 DEV_MCSPI6_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI7 Device

Device: J7200_DEV_MCSPI7 (ID = 273)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCSPI7_VBUSP_CLK Input clock
4 DEV_MCSPI7_CLKSPIREF_CLK Input clock
5 DEV_MCSPI7_IO_CLKSPIO_CLK Output clock

Clocks for MCU_ADC0 Device

Device: J7200_DEV_MCU_ADC0 (ID = 0)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_ADC0_SYS_CLK Input clock
1 DEV_MCU_ADC0_ADC_CLK Input muxed clock
2 DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_ADC0_ADC_CLK
3 DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK Parent input clock option to DEV_MCU_ADC0_ADC_CLK
4 DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK Parent input clock option to DEV_MCU_ADC0_ADC_CLK
5 DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_ADC0_ADC_CLK
6 DEV_MCU_ADC0_VBUS_CLK Input clock

Clocks for MCU_ADC1 Device

Device: J7200_DEV_MCU_ADC1 (ID = 1)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_ADC1_SYS_CLK Input clock
1 DEV_MCU_ADC1_ADC_CLK Input muxed clock
2 DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_ADC1_ADC_CLK
3 DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK Parent input clock option to DEV_MCU_ADC1_ADC_CLK
4 DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK Parent input clock option to DEV_MCU_ADC1_ADC_CLK
5 DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_ADC1_ADC_CLK
6 DEV_MCU_ADC1_VBUS_CLK Input clock

Clocks for MCU_CPSW0 Device

Device: J7200_DEV_MCU_CPSW0 (ID = 18)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_CPSW0_MDIO_MDCLK_O Output clock
2 DEV_MCU_CPSW0_CPTS_RFT_CLK Input muxed clock
3 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
4 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
5 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
6 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
7 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
8 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
9 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
10 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
11 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
12 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
17 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
18 DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK
20 DEV_MCU_CPSW0_GMII1_MR_CLK Input clock
21 DEV_MCU_CPSW0_CPPI_CLK_CLK Input clock
22 DEV_MCU_CPSW0_CPTS_GENF0 Output clock
24 DEV_MCU_CPSW0_GMII_RFT_CLK Input clock
27 DEV_MCU_CPSW0_GMII1_MT_CLK Input clock
28 DEV_MCU_CPSW0_RGMII1_TXC_O Output clock
29 DEV_MCU_CPSW0_RMII_MHZ_50_CLK Input clock
30 DEV_MCU_CPSW0_RGMII_MHZ_5_CLK Input clock
31 DEV_MCU_CPSW0_RGMII1_RXC_I Input clock
32 DEV_MCU_CPSW0_RGMII_MHZ_250_CLK Input clock
33 DEV_MCU_CPSW0_RGMII_MHZ_50_CLK Input clock

Clocks for MCU_CPT2_AGGR0 Device

Device: J7200_DEV_MCU_CPT2_AGGR0 (ID = 24)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_CPT2_AGGR0_VCLK_CLK Input clock

Clocks for MCU_DCC0 Device

Device: J7200_DEV_MCU_DCC0 (ID = 44)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_DCC0_DCC_INPUT10_CLK Input clock
1 DEV_MCU_DCC0_DCC_INPUT01_CLK Input clock
2 DEV_MCU_DCC0_DCC_CLKSRC2_CLK Input clock
3 DEV_MCU_DCC0_DCC_CLKSRC7_CLK Input clock
4 DEV_MCU_DCC0_DCC_CLKSRC0_CLK Input clock
5 DEV_MCU_DCC0_VBUS_CLK Input clock
6 DEV_MCU_DCC0_DCC_CLKSRC4_CLK Input clock
7 DEV_MCU_DCC0_DCC_CLKSRC1_CLK Input clock
8 DEV_MCU_DCC0_DCC_CLKSRC3_CLK Input clock
9 DEV_MCU_DCC0_DCC_INPUT00_CLK Input clock
10 DEV_MCU_DCC0_DCC_CLKSRC5_CLK Input clock
11 DEV_MCU_DCC0_DCC_CLKSRC6_CLK Input clock
12 DEV_MCU_DCC0_DCC_INPUT02_CLK Input clock

Clocks for MCU_DCC1 Device

Device: J7200_DEV_MCU_DCC1 (ID = 45)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_DCC1_DCC_INPUT10_CLK Input clock
1 DEV_MCU_DCC1_DCC_INPUT01_CLK Input clock
2 DEV_MCU_DCC1_DCC_CLKSRC2_CLK Input clock
3 DEV_MCU_DCC1_DCC_CLKSRC7_CLK Input clock
4 DEV_MCU_DCC1_DCC_CLKSRC0_CLK Input clock
5 DEV_MCU_DCC1_VBUS_CLK Input clock
6 DEV_MCU_DCC1_DCC_CLKSRC4_CLK Input clock
7 DEV_MCU_DCC1_DCC_CLKSRC1_CLK Input clock
8 DEV_MCU_DCC1_DCC_CLKSRC3_CLK Input clock
9 DEV_MCU_DCC1_DCC_INPUT00_CLK Input clock
10 DEV_MCU_DCC1_DCC_CLKSRC5_CLK Input clock
11 DEV_MCU_DCC1_DCC_CLKSRC6_CLK Input clock
12 DEV_MCU_DCC1_DCC_INPUT02_CLK Input clock

Clocks for MCU_DCC2 Device

Device: J7200_DEV_MCU_DCC2 (ID = 46)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_DCC2_DCC_INPUT10_CLK Input clock
1 DEV_MCU_DCC2_DCC_INPUT01_CLK Input clock
3 DEV_MCU_DCC2_DCC_CLKSRC7_CLK Input clock
4 DEV_MCU_DCC2_DCC_CLKSRC0_CLK Input clock
5 DEV_MCU_DCC2_VBUS_CLK Input clock
7 DEV_MCU_DCC2_DCC_CLKSRC1_CLK Input clock
8 DEV_MCU_DCC2_DCC_CLKSRC3_CLK Input clock
9 DEV_MCU_DCC2_DCC_INPUT00_CLK Input clock
11 DEV_MCU_DCC2_DCC_CLKSRC6_CLK Input clock
12 DEV_MCU_DCC2_DCC_INPUT02_CLK Input clock

Clocks for MCU_ESM0 Device

Device: J7200_DEV_MCU_ESM0 (ID = 98)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_ESM0_CLK Input clock

Clocks for MCU_FSS0 Device

This device has no defined clocks.

Clocks for MCU_FSS0_FSAS_0 Device

Device: J7200_DEV_MCU_FSS0_FSAS_0 (ID = 101)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_FSS0_FSAS_0_GCLK Input clock

Clocks for MCU_FSS0_HYPERBUS1P0_0 Device

Device: J7200_DEV_MCU_FSS0_HYPERBUS1P0_0 (ID = 102)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N Output clock
1 DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK Input clock
2 DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK Input clock
4 DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK Input clock
5 DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK Input clock
7 DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK Input clock
10 DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P Output clock

Clocks for MCU_FSS0_OSPI_0 Device

Device: J7200_DEV_MCU_FSS0_OSPI_0 (ID = 103)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK Input muxed clock
1 DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK
2 DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK
3 DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK Input clock
4 DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK Input clock
5 DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK Input muxed clock
6 DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK
7 DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK
8 DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK Input clock
9 DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK Output clock

Clocks for MCU_FSS0_OSPI_1 Device

Device: J7200_DEV_MCU_FSS0_OSPI_1 (ID = 104)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK Input clock
1 DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK Input clock
7 DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK Input clock

Clocks for MCU_I2C0 Device

Device: J7200_DEV_MCU_I2C0 (ID = 194)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_I2C0_PISCL Input clock
1 DEV_MCU_I2C0_PISYS_CLK Input clock
2 DEV_MCU_I2C0_CLK Input clock

Clocks for MCU_I2C1 Device

Device: J7200_DEV_MCU_I2C1 (ID = 195)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_I2C1_PISCL Input clock
1 DEV_MCU_I2C1_PISYS_CLK Input clock
2 DEV_MCU_I2C1_CLK Input clock
3 DEV_MCU_I2C1_PORSCL Output clock

Clocks for MCU_I3C0 Device

Device: J7200_DEV_MCU_I3C0 (ID = 117)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_I3C0_I3C_SCL_DI Input clock
1 DEV_MCU_I3C0_I3C_SCL_DO Output clock
2 DEV_MCU_I3C0_I3C_PCLK_CLK Input clock
4 DEV_MCU_I3C0_I3C_SCLK_CLK Input clock

Clocks for MCU_I3C1 Device

Device: J7200_DEV_MCU_I3C1 (ID = 118)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_MCU_I3C1_I3C_PCLK_CLK Input clock
4 DEV_MCU_I3C1_I3C_SCLK_CLK Input clock

Clocks for MCU_MCAN0 Device

Device: J7200_DEV_MCU_MCAN0 (ID = 172)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCAN0_MCANSS_HCLK_CLK Input clock
2 DEV_MCU_MCAN0_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
4 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
5 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
6 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK

Clocks for MCU_MCAN1 Device

Device: J7200_DEV_MCU_MCAN1 (ID = 173)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCAN1_MCANSS_HCLK_CLK Input clock
2 DEV_MCU_MCAN1_MCANSS_CCLK_CLK Input muxed clock
3 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
4 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
5 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
6 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK

Clocks for MCU_MCSPI0 Device

Device: J7200_DEV_MCU_MCSPI0 (ID = 274)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCU_MCSPI0_VBUSP_CLK Input clock
4 DEV_MCU_MCSPI0_CLKSPIREF_CLK Input clock
5 DEV_MCU_MCSPI0_IO_CLKSPIO_CLK Output clock

Clocks for MCU_MCSPI1 Device

Device: J7200_DEV_MCU_MCSPI1 (ID = 275)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCSPI1_IO_CLKSPII_CLK Input muxed clock
1 DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK
3 DEV_MCU_MCSPI1_VBUSP_CLK Input clock
4 DEV_MCU_MCSPI1_CLKSPIREF_CLK Input clock
5 DEV_MCU_MCSPI1_IO_CLKSPIO_CLK Output clock

Clocks for MCU_MCSPI2 Device

Device: J7200_DEV_MCU_MCSPI2 (ID = 276)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCSPI2_IO_CLKSPII_CLK Input clock
1 DEV_MCU_MCSPI2_VBUSP_CLK Input clock
2 DEV_MCU_MCSPI2_CLKSPIREF_CLK Input clock
3 DEV_MCU_MCSPI2_IO_CLKSPIO_CLK Output clock

Clocks for MCU_NAVSS0 Device

This device has no defined clocks.

Clocks for MCU_NAVSS0_INTR_0 Device

Device: J7200_DEV_MCU_NAVSS0_INTR_0 (ID = 237)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_INTR_0_INTR_CLK Input clock

Clocks for MCU_NAVSS0_MCRC_0 Device

Device: J7200_DEV_MCU_NAVSS0_MCRC_0 (ID = 238)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_MCRC_0_CLK Input clock

Clocks for MCU_NAVSS0_MODSS Device

Device: J7200_DEV_MCU_NAVSS0_MODSS (ID = 302)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_MODSS_VD2CLK Input clock

Clocks for MCU_NAVSS0_PROXY0 Device

Device: J7200_DEV_MCU_NAVSS0_PROXY0 (ID = 234)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_PROXY0_CLK_CLK Input clock

Clocks for MCU_NAVSS0_RINGACC0 Device

Device: J7200_DEV_MCU_NAVSS0_RINGACC0 (ID = 235)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_RINGACC0_SYS_CLK Input clock

Clocks for MCU_NAVSS0_UDMAP_0 Device

Device: J7200_DEV_MCU_NAVSS0_UDMAP_0 (ID = 236)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK Input clock

Clocks for MCU_NAVSS0_UDMASS Device

Device: J7200_DEV_MCU_NAVSS0_UDMASS (ID = 303)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_UDMASS_VD2CLK Input clock

Clocks for MCU_NAVSS0_UDMASS_INTA_0 Device

Device: J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 (ID = 233)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK Input clock

Clocks for MCU_PBIST0 Device

Device: J7200_DEV_MCU_PBIST0 (ID = 142)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_MCU_PBIST0_CLK7_CLK Input clock
2 DEV_MCU_PBIST0_CLK3_CLK Input clock
3 DEV_MCU_PBIST0_CLK5_CLK Input clock
4 DEV_MCU_PBIST0_CLK1_CLK Input clock
5 DEV_MCU_PBIST0_CLK8_CLK Input clock
6 DEV_MCU_PBIST0_CLK6_CLK Input clock
8 DEV_MCU_PBIST0_CLK4_CLK Input clock
9 DEV_MCU_PBIST0_CLK2_CLK Input clock

Clocks for MCU_PBIST1 Device

Device: J7200_DEV_MCU_PBIST1 (ID = 143)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_MCU_PBIST1_CLK7_CLK Input clock
2 DEV_MCU_PBIST1_CLK3_CLK Input clock
3 DEV_MCU_PBIST1_CLK5_CLK Input clock
4 DEV_MCU_PBIST1_CLK1_CLK Input clock
5 DEV_MCU_PBIST1_CLK8_CLK Input clock
6 DEV_MCU_PBIST1_CLK6_CLK Input clock
8 DEV_MCU_PBIST1_CLK4_CLK Input clock
9 DEV_MCU_PBIST1_CLK2_CLK Input clock

Clocks for MCU_PBIST2 Device

Device: J7200_DEV_MCU_PBIST2 (ID = 144)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_MCU_PBIST2_CLK7_CLK Input clock
2 DEV_MCU_PBIST2_CLK3_CLK Input clock
3 DEV_MCU_PBIST2_CLK5_CLK Input clock
4 DEV_MCU_PBIST2_CLK1_CLK Input clock
5 DEV_MCU_PBIST2_CLK8_CLK Input clock
6 DEV_MCU_PBIST2_CLK6_CLK Input clock
8 DEV_MCU_PBIST2_CLK4_CLK Input clock
9 DEV_MCU_PBIST2_CLK2_CLK Input clock

Clocks for MCU_R5FSS0 Device

This device has no defined clocks.

Clocks for MCU_R5FSS0_CORE0 Device

Device: J7200_DEV_MCU_R5FSS0_CORE0 (ID = 250)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_R5FSS0_CORE0_CPU_CLK Input muxed clock
1 DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK
2 DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK
3 DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK Input clock
4 DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE Input clock

Clocks for MCU_R5FSS0_CORE1 Device

Device: J7200_DEV_MCU_R5FSS0_CORE1 (ID = 251)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_R5FSS0_CORE1_CPU_CLK Input muxed clock
1 DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK
2 DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK
3 DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK Input clock
4 DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE Input clock

Clocks for MCU_RTI0 Device

Device: J7200_DEV_MCU_RTI0 (ID = 262)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_RTI0_VBUSP_CLK Input clock
1 DEV_MCU_RTI0_RTI_CLK Input muxed clock
2 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_RTI0_RTI_CLK
3 DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_RTI0_RTI_CLK
4 DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_RTI0_RTI_CLK
5 DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_RTI0_RTI_CLK

Clocks for MCU_RTI1 Device

Device: J7200_DEV_MCU_RTI1 (ID = 263)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_RTI1_VBUSP_CLK Input clock
1 DEV_MCU_RTI1_RTI_CLK Input muxed clock
2 DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_RTI1_RTI_CLK
3 DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_RTI1_RTI_CLK
4 DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_RTI1_RTI_CLK
5 DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_RTI1_RTI_CLK

Clocks for MCU_SA2_UL0 Device

Device: J7200_DEV_MCU_SA2_UL0 (ID = 265)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_SA2_UL0_X2_CLK Input clock
1 DEV_MCU_SA2_UL0_PKA_IN_CLK Input clock
2 DEV_MCU_SA2_UL0_X1_CLK Input clock

Clocks for MCU_TIMER0 Device

Device: J7200_DEV_MCU_TIMER0 (ID = 35)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER0_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER0_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
3 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
4 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
5 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
6 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
7 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
8 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
9 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
11 DEV_MCU_TIMER0_TIMER_PWM Output clock

Clocks for MCU_TIMER1 Device

Device: J7200_DEV_MCU_TIMER1 (ID = 71)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER1_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER1_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
3 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK

Clocks for MCU_TIMER1_CLKSEL_VD Device

Device: J7200_DEV_MCU_TIMER1_CLKSEL_VD (ID = 308)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER1_CLKSEL_VD_CLK Input muxed clock
1 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
2 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
3 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
4 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
5 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
6 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
7 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK
8 DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK

Clocks for MCU_TIMER2 Device

Device: J7200_DEV_MCU_TIMER2 (ID = 72)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER2_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER2_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
3 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
4 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
5 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
6 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
7 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
8 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
9 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
11 DEV_MCU_TIMER2_TIMER_PWM Output clock

Clocks for MCU_TIMER3 Device

Device: J7200_DEV_MCU_TIMER3 (ID = 73)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER3_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER3_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
3 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK

Clocks for MCU_TIMER3_CLKSEL_VD Device

Device: J7200_DEV_MCU_TIMER3_CLKSEL_VD (ID = 309)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER3_CLKSEL_VD_CLK Input muxed clock
1 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
2 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
3 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
4 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
5 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
6 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
7 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK
8 DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK

Clocks for MCU_TIMER4 Device

Device: J7200_DEV_MCU_TIMER4 (ID = 74)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER4_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER4_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
3 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
4 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
5 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
6 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
7 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
8 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
9 DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK
11 DEV_MCU_TIMER4_TIMER_PWM Output clock

Clocks for MCU_TIMER5 Device

Device: J7200_DEV_MCU_TIMER5 (ID = 75)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER5_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER5_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK
3 DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK

Clocks for MCU_TIMER5_CLKSEL_VD Device

Device: J7200_DEV_MCU_TIMER5_CLKSEL_VD (ID = 310)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER5_CLKSEL_VD_CLK Input muxed clock
1 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
2 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
3 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
4 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
5 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
6 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
7 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK
8 DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK

Clocks for MCU_TIMER6 Device

Device: J7200_DEV_MCU_TIMER6 (ID = 76)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER6_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER6_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
3 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
4 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
5 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
6 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
7 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
8 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
9 DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK
11 DEV_MCU_TIMER6_TIMER_PWM Output clock

Clocks for MCU_TIMER7 Device

Device: J7200_DEV_MCU_TIMER7 (ID = 77)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER7_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER7_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK
3 DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK

Clocks for MCU_TIMER7_CLKSEL_VD Device

Device: J7200_DEV_MCU_TIMER7_CLKSEL_VD (ID = 311)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER7_CLKSEL_VD_CLK Input muxed clock
1 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
2 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
3 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
4 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
5 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
6 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
7 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK
8 DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK

Clocks for MCU_TIMER8 Device

Device: J7200_DEV_MCU_TIMER8 (ID = 78)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER8_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER8_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
3 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
4 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
5 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
6 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
7 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
8 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
9 DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK
11 DEV_MCU_TIMER8_TIMER_PWM Output clock

Clocks for MCU_TIMER9 Device

Device: J7200_DEV_MCU_TIMER9 (ID = 79)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER9_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER9_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK
3 DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK

Clocks for MCU_TIMER9_CLKSEL_VD Device

Device: J7200_DEV_MCU_TIMER9_CLKSEL_VD (ID = 312)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER9_CLKSEL_VD_CLK Input muxed clock
1 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
2 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
3 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
4 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
5 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
6 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
7 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK
8 DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK

Clocks for MCU_UART0 Device

Device: J7200_DEV_MCU_UART0 (ID = 149)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_MCU_UART0_FCLK_CLK Input muxed clock
3 DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_UART0_FCLK_CLK
4 DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK Parent input clock option to DEV_MCU_UART0_FCLK_CLK
5 DEV_MCU_UART0_VBUSP_CLK Input clock

Clocks for MMCSD0 Device

Device: J7200_DEV_MMCSD0 (ID = 91)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD0_EMMCSS_VBUS_CLK Input clock
3 DEV_MMCSD0_EMMCSS_XIN_CLK Input muxed clock
4 DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
5 DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
6 DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
7 DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK

Clocks for MMCSD1 Device

Device: J7200_DEV_MMCSD1 (ID = 92)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD1_EMMCSDSS_IO_CLK_I Input clock
1 DEV_MMCSD1_EMMCSDSS_VBUS_CLK Input clock
2 DEV_MMCSD1_EMMCSDSS_XIN_CLK Input muxed clock
3 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
4 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
5 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
6 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
7 DEV_MMCSD1_EMMCSDSS_IO_CLK_O Output clock

Clocks for NAVSS0 Device

Device: J7200_DEV_NAVSS0 (ID = 199)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_CPTS0_GENF2 Output clock
1 DEV_NAVSS0_CPTS0_GENF3 Output clock
2 DEV_NAVSS0_CPTS0_GENF4 Output clock

Clocks for NAVSS0_CPTS_0 Device

Device: J7200_DEV_NAVSS0_CPTS_0 (ID = 201)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_CPTS_0_VBUSP_GCLK Input clock
1 DEV_NAVSS0_CPTS_0_RCLK Input muxed clock
2 DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
3 DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
4 DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
5 DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
6 DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
7 DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
8 DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
9 DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
10 DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
11 DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
16 DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
17 DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK
20 DEV_NAVSS0_CPTS_0_TS_GENF0 Output clock
21 DEV_NAVSS0_CPTS_0_TS_GENF1 Output clock

Clocks for NAVSS0_DTI_0 Device

Device: J7200_DEV_NAVSS0_DTI_0 (ID = 206)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_DTI_0_CLK_CLK Input clock

Clocks for NAVSS0_INTR_ROUTER_0 Device

Device: J7200_DEV_NAVSS0_INTR_ROUTER_0 (ID = 213)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK Input clock

Clocks for NAVSS0_MAILBOX_0 Device

Device: J7200_DEV_NAVSS0_MAILBOX_0 (ID = 214)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_0_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_1 Device

Device: J7200_DEV_NAVSS0_MAILBOX_1 (ID = 215)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_1_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_10 Device

Device: J7200_DEV_NAVSS0_MAILBOX_10 (ID = 224)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_10_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_11 Device

Device: J7200_DEV_NAVSS0_MAILBOX_11 (ID = 225)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_11_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_2 Device

Device: J7200_DEV_NAVSS0_MAILBOX_2 (ID = 216)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_2_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_3 Device

Device: J7200_DEV_NAVSS0_MAILBOX_3 (ID = 217)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_3_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_4 Device

Device: J7200_DEV_NAVSS0_MAILBOX_4 (ID = 218)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_4_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_5 Device

Device: J7200_DEV_NAVSS0_MAILBOX_5 (ID = 219)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_5_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_6 Device

Device: J7200_DEV_NAVSS0_MAILBOX_6 (ID = 220)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_6_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_7 Device

Device: J7200_DEV_NAVSS0_MAILBOX_7 (ID = 221)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_7_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_8 Device

Device: J7200_DEV_NAVSS0_MAILBOX_8 (ID = 222)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_8_VCLK_CLK Input clock

Clocks for NAVSS0_MAILBOX_9 Device

Device: J7200_DEV_NAVSS0_MAILBOX_9 (ID = 223)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MAILBOX_9_VCLK_CLK Input clock

Clocks for NAVSS0_MCRC_0 Device

Device: J7200_DEV_NAVSS0_MCRC_0 (ID = 227)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MCRC_0_CLK Input clock

Clocks for NAVSS0_MODSS Device

Device: J7200_DEV_NAVSS0_MODSS (ID = 299)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MODSS_VD2CLK Input clock

Clocks for NAVSS0_MODSS_INTA_0 Device

Device: J7200_DEV_NAVSS0_MODSS_INTA_0 (ID = 207)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MODSS_INTA_0_SYS_CLK Input clock

Clocks for NAVSS0_MODSS_INTA_1 Device

Device: J7200_DEV_NAVSS0_MODSS_INTA_1 (ID = 208)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_MODSS_INTA_1_SYS_CLK Input clock

Clocks for NAVSS0_PROXY_0 Device

Device: J7200_DEV_NAVSS0_PROXY_0 (ID = 210)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_PROXY_0_CLK_CLK Input clock

Clocks for NAVSS0_RINGACC_0 Device

Device: J7200_DEV_NAVSS0_RINGACC_0 (ID = 211)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_RINGACC_0_SYS_CLK Input clock

Clocks for NAVSS0_SPINLOCK_0 Device

Device: J7200_DEV_NAVSS0_SPINLOCK_0 (ID = 226)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_SPINLOCK_0_CLK Input clock

Clocks for NAVSS0_TBU_0 Device

Device: J7200_DEV_NAVSS0_TBU_0 (ID = 228)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_TBU_0_CLK_CLK Input clock

Clocks for NAVSS0_TIMERMGR_0 Device

Device: J7200_DEV_NAVSS0_TIMERMGR_0 (ID = 230)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_TIMERMGR_0_VCLK_CLK Input clock
1 DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT Input clock

Clocks for NAVSS0_TIMERMGR_1 Device

Device: J7200_DEV_NAVSS0_TIMERMGR_1 (ID = 231)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_TIMERMGR_1_VCLK_CLK Input clock
1 DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT Input clock

Clocks for NAVSS0_UDMAP_0 Device

Device: J7200_DEV_NAVSS0_UDMAP_0 (ID = 212)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_UDMAP_0_SYS_CLK Input clock

Clocks for NAVSS0_UDMASS Device

Device: J7200_DEV_NAVSS0_UDMASS (ID = 300)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_UDMASS_VD2CLK Input clock

Clocks for NAVSS0_UDMASS_INTA_0 Device

Device: J7200_DEV_NAVSS0_UDMASS_INTA_0 (ID = 209)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK Input clock

Clocks for NAVSS0_VIRTSS Device

Device: J7200_DEV_NAVSS0_VIRTSS (ID = 301)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_NAVSS0_VIRTSS_VD2CLK Input clock

Clocks for PBIST0 Device

Device: J7200_DEV_PBIST0 (ID = 139)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_PBIST0_CLK7_CLK Input clock
2 DEV_PBIST0_CLK3_CLK Input clock
3 DEV_PBIST0_CLK5_CLK Input clock
4 DEV_PBIST0_CLK1_CLK Input clock
5 DEV_PBIST0_CLK8_CLK Input clock
6 DEV_PBIST0_CLK6_CLK Input clock
8 DEV_PBIST0_CLK4_CLK Input clock
9 DEV_PBIST0_CLK2_CLK Input clock

Clocks for PBIST1 Device

Device: J7200_DEV_PBIST1 (ID = 140)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_PBIST1_CLK7_CLK Input clock
2 DEV_PBIST1_CLK3_CLK Input clock
3 DEV_PBIST1_CLK5_CLK Input clock
4 DEV_PBIST1_CLK1_CLK Input clock
5 DEV_PBIST1_CLK8_CLK Input clock
6 DEV_PBIST1_CLK6_CLK Input clock
8 DEV_PBIST1_CLK4_CLK Input clock
9 DEV_PBIST1_CLK2_CLK Input clock

Clocks for PBIST2 Device

Device: J7200_DEV_PBIST2 (ID = 141)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_PBIST2_CLK7_CLK Input clock
2 DEV_PBIST2_CLK3_CLK Input clock
3 DEV_PBIST2_CLK5_CLK Input clock
4 DEV_PBIST2_CLK1_CLK Input clock
5 DEV_PBIST2_CLK8_CLK Input clock
6 DEV_PBIST2_CLK6_CLK Input clock
8 DEV_PBIST2_CLK4_CLK Input clock
9 DEV_PBIST2_CLK2_CLK Input clock

Clocks for PCIE1 Device

Device: J7200_DEV_PCIE1 (ID = 240)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PCIE1_PCIE_LANE0_TXCLK Output clock
1 DEV_PCIE1_PCIE_LANE1_TXMCLK Input clock
2 DEV_PCIE1_PCIE_LANE0_TXMCLK Input clock
3 DEV_PCIE1_PCIE_LANE0_TXFCLK Input clock
4 DEV_PCIE1_PCIE_PM_CLK Input clock
5 DEV_PCIE1_PCIE_LANE3_TXMCLK Input clock
6 DEV_PCIE1_PCIE_CBA_CLK Input clock
7 DEV_PCIE1_PCIE_LANE1_REFCLK Input clock
8 DEV_PCIE1_PCIE_CPTS_RCLK_CLK Input muxed clock
9 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
10 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
11 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
12 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
13 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
14 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
15 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
16 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
17 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
18 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
23 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
24 DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK
25 DEV_PCIE1_PCIE_LANE1_RXFCLK Input clock
27 DEV_PCIE1_PCIE_LANE2_RXCLK Input clock
28 DEV_PCIE1_PCIE_LANE2_TXMCLK Input clock
29 DEV_PCIE1_PCIE_LANE1_TXCLK Output clock
30 DEV_PCIE1_PCIE_LANE3_TXFCLK Input clock
31 DEV_PCIE1_PCIE_LANE2_TXFCLK Input clock
32 DEV_PCIE1_PCIE_LANE1_RXCLK Input clock
33 DEV_PCIE1_PCIE_LANE2_TXCLK Output clock
34 DEV_PCIE1_PCIE_LANE1_TXFCLK Input clock
35 DEV_PCIE1_PCIE_LANE0_REFCLK Input clock
36 DEV_PCIE1_PCIE_LANE3_RXFCLK Input clock
37 DEV_PCIE1_PCIE_LANE2_RXFCLK Input clock
38 DEV_PCIE1_PCIE_LANE3_RXCLK Input clock
39 DEV_PCIE1_PCIE_LANE3_REFCLK Input clock
40 DEV_PCIE1_PCIE_LANE2_REFCLK Input clock
41 DEV_PCIE1_PCIE_LANE0_RXFCLK Input clock
42 DEV_PCIE1_PCIE_LANE3_TXCLK Output clock
43 DEV_PCIE1_PCIE_LANE0_RXCLK Input clock

Clocks for PSC0 Device

Device: J7200_DEV_PSC0 (ID = 133)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PSC0_SLOW_CLK Input clock
1 DEV_PSC0_CLK Input clock

Clocks for R5FSS0 Device

This device has no defined clocks.

Clocks for R5FSS0_CORE0 Device

Device: J7200_DEV_R5FSS0_CORE0 (ID = 245)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS0_CORE0_CPU_CLK Input clock
1 DEV_R5FSS0_CORE0_INTERFACE_CLK Input clock
2 DEV_R5FSS0_CORE0_INTERFACE_PHASE Input clock

Clocks for R5FSS0_CORE1 Device

Device: J7200_DEV_R5FSS0_CORE1 (ID = 246)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS0_CORE1_CPU_CLK Input clock
1 DEV_R5FSS0_CORE1_INTERFACE_CLK Input clock
2 DEV_R5FSS0_CORE1_INTERFACE_PHASE Input clock

Clocks for RTI0 Device

Device: J7200_DEV_RTI0 (ID = 252)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI0_VBUSP_CLK Input clock
1 DEV_RTI0_RTI_CLK Input muxed clock
2 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI0_RTI_CLK
3 DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_RTI0_RTI_CLK
4 DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_RTI0_RTI_CLK
5 DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_RTI0_RTI_CLK
6 DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_RTI0_RTI_CLK
7 DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 Parent input clock option to DEV_RTI0_RTI_CLK
8 DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 Parent input clock option to DEV_RTI0_RTI_CLK
9 DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 Parent input clock option to DEV_RTI0_RTI_CLK

Clocks for RTI1 Device

Device: J7200_DEV_RTI1 (ID = 253)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI1_VBUSP_CLK Input clock
1 DEV_RTI1_RTI_CLK Input muxed clock
2 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI1_RTI_CLK
3 DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_RTI1_RTI_CLK
4 DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_RTI1_RTI_CLK
5 DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_RTI1_RTI_CLK
6 DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_RTI1_RTI_CLK
7 DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 Parent input clock option to DEV_RTI1_RTI_CLK
8 DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 Parent input clock option to DEV_RTI1_RTI_CLK
9 DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 Parent input clock option to DEV_RTI1_RTI_CLK

Clocks for RTI28 Device

Device: J7200_DEV_RTI28 (ID = 258)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI28_VBUSP_CLK Input clock
1 DEV_RTI28_RTI_CLK Input muxed clock
2 DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI28_RTI_CLK
3 DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_RTI28_RTI_CLK
4 DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_RTI28_RTI_CLK
5 DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_RTI28_RTI_CLK
6 DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_RTI28_RTI_CLK
7 DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 Parent input clock option to DEV_RTI28_RTI_CLK
8 DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 Parent input clock option to DEV_RTI28_RTI_CLK
9 DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 Parent input clock option to DEV_RTI28_RTI_CLK

Clocks for RTI29 Device

Device: J7200_DEV_RTI29 (ID = 259)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI29_VBUSP_CLK Input clock
1 DEV_RTI29_RTI_CLK Input muxed clock
2 DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI29_RTI_CLK
3 DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_RTI29_RTI_CLK
4 DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_RTI29_RTI_CLK
5 DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_RTI29_RTI_CLK
6 DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_RTI29_RTI_CLK
7 DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 Parent input clock option to DEV_RTI29_RTI_CLK
8 DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 Parent input clock option to DEV_RTI29_RTI_CLK
9 DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 Parent input clock option to DEV_RTI29_RTI_CLK

Clocks for SERDES_10G1 Device

Device: J7200_DEV_SERDES_10G1 (ID = 292)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_SERDES_10G1_IP3_LN1_TXFCLK Output clock
3 DEV_SERDES_10G1_IP2_LN2_REFCLK Output clock
4 DEV_SERDES_10G1_IP1_LN0_TXMCLK Output clock
6 DEV_SERDES_10G1_IP3_LN3_RXCLK Output clock
9 DEV_SERDES_10G1_IP2_LN2_RXCLK Output clock
10 DEV_SERDES_10G1_IP1_LN0_TXFCLK Output clock
11 DEV_SERDES_10G1_CLK Input clock
13 DEV_SERDES_10G1_IP1_LN3_RXCLK Output clock
14 DEV_SERDES_10G1_IP1_LN1_TXMCLK Output clock
15 DEV_SERDES_10G1_IP2_LN0_TXFCLK Output clock
16 DEV_SERDES_10G1_IP2_LN2_TXMCLK Output clock
19 DEV_SERDES_10G1_IP3_LN1_TXCLK Input clock
21 DEV_SERDES_10G1_IP2_LN3_RXFCLK Output clock
22 DEV_SERDES_10G1_IP1_LN2_TXCLK Input clock
24 DEV_SERDES_10G1_IP2_LN1_RXCLK Output clock
25 DEV_SERDES_10G1_IP2_LN1_TXCLK Input clock
29 DEV_SERDES_10G1_IP1_LN2_TXMCLK Output clock
32 DEV_SERDES_10G1_IP2_LN1_TXMCLK Output clock
33 DEV_SERDES_10G1_IP2_LN1_TXFCLK Output clock
34 DEV_SERDES_10G1_IP1_LN1_TXFCLK Output clock
38 DEV_SERDES_10G1_IP1_LN2_RXCLK Output clock
40 DEV_SERDES_10G1_IP2_LN1_REFCLK Output clock
41 DEV_SERDES_10G1_IP2_LN0_TXMCLK Output clock
42 DEV_SERDES_10G1_IP2_LN3_RXCLK Output clock
43 DEV_SERDES_10G1_IP2_LN2_TXCLK Input clock
44 DEV_SERDES_10G1_IP2_LN2_RXFCLK Output clock
45 DEV_SERDES_10G1_IP1_LN1_RXFCLK Output clock
49 DEV_SERDES_10G1_IP1_LN0_RXCLK Output clock
52 DEV_SERDES_10G1_IP1_LN1_RXCLK Output clock
55 DEV_SERDES_10G1_IP1_LN0_RXFCLK Output clock
56 DEV_SERDES_10G1_IP3_LN3_TXCLK Input clock
59 DEV_SERDES_10G1_IP2_LN3_REFCLK Output clock
61 DEV_SERDES_10G1_IP2_LN0_TXCLK Input clock
62 DEV_SERDES_10G1_IP2_LN3_TXMCLK Output clock
63 DEV_SERDES_10G1_IP1_LN1_REFCLK Output clock
65 DEV_SERDES_10G1_IP1_LN3_TXCLK Input clock
66 DEV_SERDES_10G1_IP3_LN1_TXMCLK Output clock
67 DEV_SERDES_10G1_IP2_LN2_TXFCLK Output clock
73 DEV_SERDES_10G1_IP3_LN1_RXCLK Output clock
74 DEV_SERDES_10G1_IP3_LN1_REFCLK Output clock
75 DEV_SERDES_10G1_IP1_LN3_REFCLK Output clock
77 DEV_SERDES_10G1_IP1_LN0_REFCLK Output clock
80 DEV_SERDES_10G1_IP1_LN2_REFCLK Output clock
81 DEV_SERDES_10G1_IP2_LN0_REFCLK Output clock
82 DEV_SERDES_10G1_IP2_LN0_RXCLK Output clock
85 DEV_SERDES_10G1_CORE_REF_CLK Input muxed clock
86 DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
87 DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
88 DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
89 DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK
92 DEV_SERDES_10G1_IP1_LN3_TXMCLK Output clock
95 DEV_SERDES_10G1_IP2_LN3_TXCLK Input clock
96 DEV_SERDES_10G1_IP3_LN3_RXFCLK Output clock
98 DEV_SERDES_10G1_IP3_LN3_REFCLK Output clock
100 DEV_SERDES_10G1_IP2_LN1_RXFCLK Output clock
102 DEV_SERDES_10G1_IP3_LN1_RXFCLK Output clock
104 DEV_SERDES_10G1_IP1_LN1_TXCLK Input clock
107 DEV_SERDES_10G1_IP3_LN3_TXFCLK Output clock
108 DEV_SERDES_10G1_IP1_LN3_TXFCLK Output clock
109 DEV_SERDES_10G1_IP2_LN3_TXFCLK Output clock
111 DEV_SERDES_10G1_IP1_LN0_TXCLK Input clock
112 DEV_SERDES_10G1_IP2_LN0_RXFCLK Output clock
113 DEV_SERDES_10G1_IP1_LN2_RXFCLK Output clock
118 DEV_SERDES_10G1_IP1_LN2_TXFCLK Output clock
124 DEV_SERDES_10G1_IP1_LN3_RXFCLK Output clock
126 DEV_SERDES_10G1_IP3_LN3_TXMCLK Output clock

Clocks for STM0 Device

Device: J7200_DEV_STM0 (ID = 29)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_STM0_CORE_CLK Input clock
1 DEV_STM0_VBUSP_CLK Input clock
2 DEV_STM0_ATB_CLK Input clock

Clocks for TIMER0 Device

Device: J7200_DEV_TIMER0 (ID = 49)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER0_TIMER_HCLK_CLK Input clock
1 DEV_TIMER0_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
3 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
4 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
5 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
6 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
7 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
8 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
9 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
10 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
11 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
12 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
13 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
14 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
15 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
16 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
17 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
26 DEV_TIMER0_TIMER_PWM Output clock

Clocks for TIMER1 Device

Device: J7200_DEV_TIMER1 (ID = 50)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER1_TIMER_HCLK_CLK Input clock
1 DEV_TIMER1_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
3 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK

Clocks for TIMER10 Device

Device: J7200_DEV_TIMER10 (ID = 60)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER10_TIMER_HCLK_CLK Input clock
1 DEV_TIMER10_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
3 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
4 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
5 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
6 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
7 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
8 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
9 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
10 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
11 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
12 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
13 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
14 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
15 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
16 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
17 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
26 DEV_TIMER10_TIMER_PWM Output clock

Clocks for TIMER11 Device

Device: J7200_DEV_TIMER11 (ID = 62)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER11_TIMER_HCLK_CLK Input clock
1 DEV_TIMER11_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
3 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK

Clocks for TIMER11_CLKSEL_VD Device

Device: J7200_DEV_TIMER11_CLKSEL_VD (ID = 318)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER11_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
2 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
3 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
4 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
5 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
6 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
7 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
8 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
9 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
10 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
11 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
12 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
13 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
14 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
15 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK
16 DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK

Clocks for TIMER12 Device

Device: J7200_DEV_TIMER12 (ID = 63)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER12_TIMER_HCLK_CLK Input clock
1 DEV_TIMER12_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
3 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
4 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
5 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
6 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
7 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
8 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
9 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
10 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
11 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
12 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
13 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
14 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
15 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
16 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
17 DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK
26 DEV_TIMER12_TIMER_PWM Output clock

Clocks for TIMER13 Device

Device: J7200_DEV_TIMER13 (ID = 64)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER13_TIMER_HCLK_CLK Input clock
1 DEV_TIMER13_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK
3 DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK

Clocks for TIMER13_CLKSEL_VD Device

Device: J7200_DEV_TIMER13_CLKSEL_VD (ID = 319)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER13_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
2 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
3 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
4 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
5 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
6 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
7 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
8 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
9 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
10 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
11 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
12 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
13 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
14 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
15 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK
16 DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK

Clocks for TIMER14 Device

Device: J7200_DEV_TIMER14 (ID = 65)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER14_TIMER_HCLK_CLK Input clock
1 DEV_TIMER14_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
3 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
4 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
5 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
6 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
7 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
8 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
9 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
10 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
11 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
12 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
13 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
14 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
15 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
16 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
17 DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK
26 DEV_TIMER14_TIMER_PWM Output clock

Clocks for TIMER15 Device

Device: J7200_DEV_TIMER15 (ID = 66)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER15_TIMER_HCLK_CLK Input clock
1 DEV_TIMER15_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK
3 DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK

Clocks for TIMER15_CLKSEL_VD Device

Device: J7200_DEV_TIMER15_CLKSEL_VD (ID = 320)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER15_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
2 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
3 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
4 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
5 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
6 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
7 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
8 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
9 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
10 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
11 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
12 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
13 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
14 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
15 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK
16 DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK

Clocks for TIMER16 Device

Device: J7200_DEV_TIMER16 (ID = 67)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER16_TIMER_HCLK_CLK Input clock
1 DEV_TIMER16_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
3 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
4 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
5 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
6 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
7 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
8 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
9 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
10 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
11 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
12 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
13 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
14 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
15 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
16 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
17 DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK
26 DEV_TIMER16_TIMER_PWM Output clock

Clocks for TIMER17 Device

Device: J7200_DEV_TIMER17 (ID = 68)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER17_TIMER_HCLK_CLK Input clock
1 DEV_TIMER17_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK
3 DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK

Clocks for TIMER17_CLKSEL_VD Device

Device: J7200_DEV_TIMER17_CLKSEL_VD (ID = 321)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER17_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
2 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
3 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
4 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
5 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
6 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
7 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
8 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
9 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
10 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
11 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
12 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
13 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
14 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
15 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK
16 DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK

Clocks for TIMER18 Device

Device: J7200_DEV_TIMER18 (ID = 69)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER18_TIMER_HCLK_CLK Input clock
1 DEV_TIMER18_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
3 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
4 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
5 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
6 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
7 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
8 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
9 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
10 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
11 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
12 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
13 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
14 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
15 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
16 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
17 DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK
26 DEV_TIMER18_TIMER_PWM Output clock

Clocks for TIMER19 Device

Device: J7200_DEV_TIMER19 (ID = 70)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER19_TIMER_HCLK_CLK Input clock
1 DEV_TIMER19_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK
3 DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK

Clocks for TIMER19_CLKSEL_VD Device

Device: J7200_DEV_TIMER19_CLKSEL_VD (ID = 322)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER19_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
2 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
3 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
4 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
5 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
6 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
7 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
8 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
9 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
10 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
11 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
12 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
13 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
14 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
15 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK
16 DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK

Clocks for TIMER1_CLKSEL_VD Device

Device: J7200_DEV_TIMER1_CLKSEL_VD (ID = 313)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER1_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
2 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
3 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
4 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
5 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
6 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
7 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
8 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
9 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
10 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
11 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
12 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
13 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
14 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
15 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK
16 DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK

Clocks for TIMER2 Device

Device: J7200_DEV_TIMER2 (ID = 51)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER2_TIMER_HCLK_CLK Input clock
1 DEV_TIMER2_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
3 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
4 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
5 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
6 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
7 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
8 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
9 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
10 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
11 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
12 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
13 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
14 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
15 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
16 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
17 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
26 DEV_TIMER2_TIMER_PWM Output clock

Clocks for TIMER3 Device

Device: J7200_DEV_TIMER3 (ID = 52)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER3_TIMER_HCLK_CLK Input clock
1 DEV_TIMER3_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
3 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK

Clocks for TIMER3_CLKSEL_VD Device

Device: J7200_DEV_TIMER3_CLKSEL_VD (ID = 314)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER3_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
2 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
3 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
4 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
5 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
6 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
7 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
8 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
9 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
10 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
11 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
12 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
13 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
14 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
15 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK
16 DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK

Clocks for TIMER4 Device

Device: J7200_DEV_TIMER4 (ID = 53)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER4_TIMER_HCLK_CLK Input clock
1 DEV_TIMER4_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
3 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
4 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
5 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
6 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
7 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
8 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
9 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
10 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
11 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
12 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
13 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
14 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
15 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
16 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
17 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
26 DEV_TIMER4_TIMER_PWM Output clock

Clocks for TIMER5 Device

Device: J7200_DEV_TIMER5 (ID = 54)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER5_TIMER_HCLK_CLK Input clock
1 DEV_TIMER5_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
3 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK

Clocks for TIMER5_CLKSEL_VD Device

Device: J7200_DEV_TIMER5_CLKSEL_VD (ID = 315)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER5_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
2 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
3 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
4 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
5 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
6 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
7 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
8 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
9 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
10 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
11 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
12 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
13 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
14 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
15 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK
16 DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK

Clocks for TIMER6 Device

Device: J7200_DEV_TIMER6 (ID = 55)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER6_TIMER_HCLK_CLK Input clock
1 DEV_TIMER6_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
3 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
4 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
5 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
6 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
7 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
8 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
9 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
10 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
11 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
12 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
13 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
14 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
15 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
16 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
17 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
26 DEV_TIMER6_TIMER_PWM Output clock

Clocks for TIMER7 Device

Device: J7200_DEV_TIMER7 (ID = 57)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER7_TIMER_HCLK_CLK Input clock
1 DEV_TIMER7_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
3 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK

Clocks for TIMER7_CLKSEL_VD Device

Device: J7200_DEV_TIMER7_CLKSEL_VD (ID = 316)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER7_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
2 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
3 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
4 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
5 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
6 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
7 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
8 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
9 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
10 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
11 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
12 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
13 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
14 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
15 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK
16 DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK

Clocks for TIMER8 Device

Device: J7200_DEV_TIMER8 (ID = 58)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER8_TIMER_HCLK_CLK Input clock
1 DEV_TIMER8_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
3 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
4 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
5 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
6 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
7 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
8 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
9 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
10 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
11 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
12 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
13 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
14 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
15 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
16 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
17 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
26 DEV_TIMER8_TIMER_PWM Output clock

Clocks for TIMER9 Device

Device: J7200_DEV_TIMER9 (ID = 59)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER9_TIMER_HCLK_CLK Input clock
1 DEV_TIMER9_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
3 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK

Clocks for TIMER9_CLKSEL_VD Device

Device: J7200_DEV_TIMER9_CLKSEL_VD (ID = 317)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER9_CLKSEL_VD_CLK Input muxed clock
1 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
2 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
3 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
4 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
5 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
6 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
7 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
8 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
9 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
10 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
11 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
12 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
13 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
14 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
15 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK
16 DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK

Clocks for TIMESYNC_INTRTR0 Device

This device has no defined clocks.

Clocks for UART0 Device

Device: J7200_DEV_UART0 (ID = 146)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART0_FCLK_CLK Input clock
3 DEV_UART0_VBUSP_CLK Input clock

Clocks for UART1 Device

Device: J7200_DEV_UART1 (ID = 278)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART1_FCLK_CLK Input clock
3 DEV_UART1_VBUSP_CLK Input clock

Clocks for UART2 Device

Device: J7200_DEV_UART2 (ID = 279)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART2_FCLK_CLK Input clock
3 DEV_UART2_VBUSP_CLK Input clock

Clocks for UART3 Device

Device: J7200_DEV_UART3 (ID = 280)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART3_FCLK_CLK Input clock
3 DEV_UART3_VBUSP_CLK Input clock

Clocks for UART4 Device

Device: J7200_DEV_UART4 (ID = 281)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART4_FCLK_CLK Input clock
3 DEV_UART4_VBUSP_CLK Input clock

Clocks for UART5 Device

Device: J7200_DEV_UART5 (ID = 282)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART5_FCLK_CLK Input clock
3 DEV_UART5_VBUSP_CLK Input clock

Clocks for UART6 Device

Device: J7200_DEV_UART6 (ID = 283)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART6_FCLK_CLK Input clock
3 DEV_UART6_VBUSP_CLK Input clock

Clocks for UART7 Device

Device: J7200_DEV_UART7 (ID = 284)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART7_FCLK_CLK Input clock
3 DEV_UART7_VBUSP_CLK Input clock

Clocks for UART8 Device

Device: J7200_DEV_UART8 (ID = 285)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART8_FCLK_CLK Input clock
3 DEV_UART8_VBUSP_CLK Input clock

Clocks for UART9 Device

Device: J7200_DEV_UART9 (ID = 286)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_UART9_FCLK_CLK Input clock
3 DEV_UART9_VBUSP_CLK Input clock

Clocks for USB0 Device

Device: J7200_DEV_USB0 (ID = 288)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_USB0_PIPE_REFCLK Input muxed clock
1 DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN1_REFCLK Parent input clock option to DEV_USB0_PIPE_REFCLK
2 DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN3_REFCLK Parent input clock option to DEV_USB0_PIPE_REFCLK
3 DEV_USB0_CLK_LPM_CLK Input clock
4 DEV_USB0_BUF_CLK Input clock
5 DEV_USB0_PIPE_TXFCLK Input clock
6 DEV_USB0_USB2_APB_PCLK_CLK Input clock
7 DEV_USB0_PIPE_RXCLK Input clock
8 DEV_USB0_PIPE_TXMCLK Input clock
9 DEV_USB0_PIPE_RXFCLK Input clock
11 DEV_USB0_PIPE_TXCLK Output clock
12 DEV_USB0_USB2_REFCLOCK_CLK Input muxed clock
13 DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
14 DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
15 DEV_USB0_PCLK_CLK Input clock
17 DEV_USB0_ACLK_CLK Input clock

Clocks for WKUPMCU2MAIN_VD Device

This device has no defined clocks.

Clocks for WKUP_DDPA0 Device

Device: J7200_DEV_WKUP_DDPA0 (ID = 145)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_DDPA0_DDPA_CLK Input clock

Clocks for WKUP_DMSC0 Device

This device has no defined clocks.

Clocks for WKUP_ESM0 Device

Device: J7200_DEV_WKUP_ESM0 (ID = 99)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_ESM0_CLK Input clock

Clocks for WKUP_GPIO0 Device

Device: J7200_DEV_WKUP_GPIO0 (ID = 113)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_GPIO0_MMR_CLK Input muxed clock
1 DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK
2 DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0 Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK
3 DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK
4 DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK

Clocks for WKUP_GPIO1 Device

Device: J7200_DEV_WKUP_GPIO1 (ID = 114)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_GPIO1_MMR_CLK Input muxed clock
1 DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK
2 DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0 Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK
3 DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK
4 DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK

Clocks for WKUP_GPIOMUX_INTRTR0 Device

This device has no defined clocks.

Clocks for WKUP_I2C0 Device

Device: J7200_DEV_WKUP_I2C0 (ID = 197)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_I2C0_PISCL Input clock
1 DEV_WKUP_I2C0_PISYS_CLK Input clock
2 DEV_WKUP_I2C0_CLK Input clock
3 DEV_WKUP_I2C0_PORSCL Output clock

Clocks for WKUP_PORZ_SYNC0 Device

Device: J7200_DEV_WKUP_PORZ_SYNC0 (ID = 132)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK Input clock

Clocks for WKUP_PSC0 Device

Device: J7200_DEV_WKUP_PSC0 (ID = 138)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_PSC0_SLOW_CLK Input clock
1 DEV_WKUP_PSC0_CLK Input clock

Clocks for WKUP_UART0 Device

Device: J7200_DEV_WKUP_UART0 (ID = 287)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_WKUP_UART0_FCLK_CLK Input muxed clock
3 DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0 Parent input clock option to DEV_WKUP_UART0_FCLK_CLK
4 DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_WKUP_UART0_FCLK_CLK
5 DEV_WKUP_UART0_VBUSP_CLK Input clock

Clocks for WKUP_VTM0 Device

Device: J7200_DEV_WKUP_VTM0 (ID = 154)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_VTM0_FIX_REF2_CLK Input clock
1 DEV_WKUP_VTM0_VBUSP_CLK Input clock
2 DEV_WKUP_VTM0_FIX_REF_CLK Input clock

Clocks for WKUP_WAKEUP0 Device

Device: J7200_DEV_WKUP_WAKEUP0 (ID = 40)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_WAKEUP0_PLL_CTRL_WKUP_CLK24_CLK Input clock
1 DEV_WKUP_WAKEUP0_WKUP_RCOSC_32K_CLK Output clock
2 DEV_WKUP_WAKEUP0_WKUP_RCOSC_12P5M_CLK Output clock