AM62AX Firewall Descriptions¶
Introduction¶
This chapter provides information on firewalls that system firmware configures by default at boot time. The guide to read the tables in this chapter is provided below. For more details on firewalls, refer to the “Interconnect Firewalls” section of the TRM and Firewall TISCI Description.
Table Legend¶
Firewall ID: The unique identifier for each firewallOwner: The host ID that owns the firewallCBA_PERMISSION_x: Each permission slot takes the form of [user, permission], where “user” is a host ID and “permission” is a combination of r-read, w-write, c-cache, d-debug. Additionally, each firewall region/channel can have up to 3 slots for configuring permissions.
Table Guide¶
- If a firewall is owned by
TIFS/DMSC, it means that only TIFS/DMSC can configure it. - If a firewall is owned by
none, it means any host can configure it. - If a firewall is owned by
rm, it means that the corresponding resource is managed by the resource manager based on the RM boardcfg. - If a firewall is not listed in the table below, it does not mean it doesn’t exist. It simply means it was not one of the firewalls configured at boot time by system firmware.
Note
For additional firewall information, checkout the Firewall FAQ.
List of Region Based Firewalls¶
| Firewall ID | Region | Owner | Dev Group | Start Address | End Address | CBA_PERMISSION_0 | CBA_PERMISSION_1 | CBA_PERMISSION_2 |
|---|---|---|---|---|---|---|---|---|
| 3 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwcd | tifs,rwcd | tifs,rwcd |
| 9 | 0 | tifs | SOC_DEVGRP_MAIN | 0x49800000 | 0x4A67FFFF | tifs,rwcd | everyone,r | |
| 9 | 1 | tifs | SOC_DEVGRP_MAIN | 0x48100000 | 0x4811001F | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 2 | tifs | SOC_DEVGRP_MAIN | 0x48130000 | 0x4823FFFF | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 3 | tifs | SOC_DEVGRP_MAIN | 0x48420000 | 0x48607FFF | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 4 | tifs | SOC_DEVGRP_MAIN | 0x4E000000 | 0x4E01FFFF | tifs,rwcd | everyone,r | |
| 9 | 5 | tifs | SOC_DEVGRP_MAIN | 0x4E0B0000 | 0x4E0C001F | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 6 | tifs | SOC_DEVGRP_MAIN | 0x4E040000 | 0x4E0903FF | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 7 | tifs | SOC_DEVGRP_MAIN | 0x4E200000 | 0x4E2300FF | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 8 | tifs | SOC_DEVGRP_MAIN | 0x4E260000 | 0x4E2601FF | tifs,rwcd | dm, rwcd | everyone,r |
| 9 | 9 | none | SOC_DEVGRP_MAIN | 0x3F005000 | 0x4E2601FF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 9 | 10 | none | SOC_DEVGRP_MAIN | 0x48240000 | 0x482500FF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 33 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x00300000 | 0x003000FF | tifs,rwcd | tifs,rwcd | tifs,rwcd |
| 33 | 1 | none | SOC_DEVGRP_MCU_WAKEUP | 0x00000000 | 0xFFFFFFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 33 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x00A00000 | 0x00A007FF | tifs,rwcd | dm,rwcd | everyone,r |
| 35 | 0 | none | SOC_DEVGRP_MCU_WAKEUP | 0x00000000 | 0xFFFFFFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 35 | 7 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x04210000 | 0x042101FF | tifs,rwcd | dm,rwcd | everyone,r |
| 160 | 0 | none | SOC_DEVGRP_MAIN | 0x4D000000 | 0x4E3FFFFF | everyone,rwcd | ||
| 160 | 1 | tifs | SOC_DEVGRP_MAIN | 0x4E004000 | 0x4E013FFF | sproxy_private,rwcd | ||
| 161 | 1 | hsm | SOC_DEVGRP_MAIN | 0x43600000 | 0x43601FFF | everyone,rwcd | ||
| 161 | 0 | tifs | SOC_DEVGRP_MAIN | 0x43600000 | 0x4360FFFF | tifs,rwcd | ||
| 512 | 0 | tifs | SOC_DEVGRP_MAIN | tifs,rc | tifs,rc | tifs,rc | ||
| 513 | 0 | tifs | SOC_DEVGRP_MAIN | tifs,rwcd | tifs,rwcd | tifs,rwcd | ||
| 514 | 0 | tifs | SOC_DEVGRP_MAIN | tifs,rwcd | tifs,rwcd | tifs,rwcd | ||
| 528 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 536 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 537 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 544 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 545 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 552 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 562 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 576 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 578 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 582 | 0 | tifs | SOC_DEVGRP_MAIN | 0x44234000 | 0x44234FFF | everyone,r | everyone,r | everyone,r |
| 582 | 1 | tifs | SOC_DEVGRP_MAIN | 0x44235000 | 0x44237FFF | tifs,rwcd | tifs,rwcd | tifs,rwcd |
| 592 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 593 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 602 | 0 | tifs | SOC_DEVGRP_MAIN | 0x4423C000 | 0x4423CFFF | tifs,rwcd | ||
| 602 | 1 | hsm | SOC_DEVGRP_MAIN | 0x4423D000 | 0x4423DFFF | hsm,rwcd | ||
| 638 | 0 | tifs | SOC_DEVGRP_MAIN | 0x44800000 | 0x44FFFFFF | tifs,rwd | hsm,rwd | everyone,r |
| 638 | 1 | tifs | SOC_DEVGRP_MAIN | 0x44880000 | 0x44887FFF | everyone,r | tifs,rwd | hsm,rwd |
| 638 | 3 | tifs | SOC_DEVGRP_MAIN | 0x44861000 | 0x44864FFF | everyone,r | tifs,rwd | hsm,rwd |
| 638 | 4 | tifs | SOC_DEVGRP_MAIN | 0x43702000 | 0x43702FFF | tifs,rwd | hsm,rwd | |
| 638 | 6 | tifs | SOC_DEVGRP_MAIN | 0x44914000 | 0x44915FFF | tifs,rwd | ||
| 638 | 7 | tifs | SOC_DEVGRP_MAIN | 0x44801000 | 0x44801FFF | tifs,rwcd | ||
| 638 | 8 | tifs | SOC_DEVGRP_MAIN | 0x44918000 | 0x44918FFF | tifs,rwd | ||
| 638 | 9 | tifs | SOC_DEVGRP_MAIN | 0x44940000 | 0x4494FFFF | tifs,rwd | ||
| 638 | 10 | tifs | SOC_DEVGRP_MAIN | 0x44960000 | 0x4496FFFF | tifs,rwd | ||
| 639 | 0 | tifs | SOC_DEVGRP_MAIN | 0x45000000 | 0x45AFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 639 | 1 | tifs | SOC_DEVGRP_MAIN | 0x45D00000 | 0x45DFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 639 | 2 | tifs | SOC_DEVGRP_MAIN | 0x45E00000 | 0x45FFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 639 | 3 | tifs | SOC_DEVGRP_MAIN | 0x45B00000 | 0x45B09FFF | tifs,rwd | everyone,r | everyone,r |
| 639 | 4 | tifs | SOC_DEVGRP_MAIN | 0x45B0A000 | 0x45CFFFFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 639 | 7 | tifs | SOC_DEVGRP_MAIN | 0x45080000 | 0x45100FFF | tifs,rwd | tifs,rwd | tifs,rwd |
| 641 | 0 | none | SOC_DEVGRP_MAIN | 0x43C00000 | 0x43C2FFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 642 | 0 | none | SOC_DEVGRP_MAIN | 0x43C30000 | 0x43C3FFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 672 | 0 | hsm | SOC_DEVGRP_MAIN | 0x43936000 | 0x43936FFF | hsm,rwd | ||
| 673 | 0 | hsm | SOC_DEVGRP_MAIN | 0x43935000 | 0x439350FF | hsm,rwd | ||
| 680 | 0 | hsm | SOC_DEVGRP_MAIN | 0x43A00000 | 0x43A00FFF | hsm,rwd | ||
| 690 | 0 | hsm | SOC_DEVGRP_MAIN | 0x43701000 | 0x437013FF | hsm,rwd |
Note
For more details on firewalls, refer to the “Interconnect Firewalls” section of the TRM.
List of Channelized Firewalls¶
| Firewall ID | Owner | Dev Group | Start Channel | End Channel | CBA_PERMISSION_0 | CBA_PERMISSION_1 | CBA_PERMISSION_2 |
|---|---|---|---|---|---|---|---|
| 128 | tifs | SOC_DEVGRP_MAIN | 0 | 4 | tifs,rwcd | dm,rc | dm,rc |
List of priv-ids¶
| Master name | priv-id | secure | non-secure | privileged | user | HOST-IDs |
|---|---|---|---|---|---|---|
| a53_non_secure_supervisor | 1 | False | True | True | False | 12,13,14 |
| a53_secure_supervisor | 1 | True | False | True | False | 10,11 |
| sproxy_private | 11 | True | True | True | True | N/A |
| main_0_c7x_0_nonsecure | 32 | False | True | True | True | 20 |
| mcu_0_r5_0 | 96 | False | True | True | True | 30 |
| everyone | 195 | True | True | True | True | N/A |
| block_everyone | 197 | True | True | True | True | N/A |
| tifs | 202 | True | True | True | True | N/A |
| hsm | 204 | False | True | True | True | 253 |
| main_0_r5_0_nonsecure | 212 | False | True | True | True | 36 |
| main_0_r5_0_secure | 212 | True | False | True | True | 35 |
| main_0_r5_1_nonsecure | 212 | False | True | True | True | 38 |
| main_0_r5_1_secure | 212 | True | False | True | True | 37 |
| dm | 212 | True | True | True | True | N/A |