AM62AX Clock Identifiers

Clock for AM62AX Device

This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in AM62AX SoC.

TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.

Device wise clock ID list for AM62AX SoC

This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs

The following table describes functions implemented by clocks

Function Description
Input clock Clock input to the SoC subsystem
Output clock Clock output from the SoC subsystem
Input muxed clock Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source
Parent input clock option to XYZ One of the parent clocks that can be used as a source clock to a input muxed clock

Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:

This device has no defined clocks.

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

Clocks for A53SS0 Device

Device: AM62AX_DEV_A53SS0 (ID = 166)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK Output clock
3 DEV_A53SS0_COREPAC_ARM_CLK_CLK Input clock
5 DEV_A53SS0_PLL_CTRL_CLK Input clock

Clocks for A53SS0_CORE_0 Device

Device: AM62AX_DEV_A53SS0_CORE_0 (ID = 135)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK Input clock

Clocks for A53SS0_CORE_1 Device

Device: AM62AX_DEV_A53SS0_CORE_1 (ID = 136)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK Input clock

Clocks for A53SS0_CORE_2 Device

Device: AM62AX_DEV_A53SS0_CORE_2 (ID = 137)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK Input clock

Clocks for A53SS0_CORE_3 Device

Device: AM62AX_DEV_A53SS0_CORE_3 (ID = 138)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK Input clock

Clocks for A53_RS_BW_LIMITER0 Device

Device: AM62AX_DEV_A53_RS_BW_LIMITER0 (ID = 172)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53_RS_BW_LIMITER0_CLK_CLK Input clock

Clocks for A53_WS_BW_LIMITER1 Device

Device: AM62AX_DEV_A53_WS_BW_LIMITER1 (ID = 173)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53_WS_BW_LIMITER1_CLK_CLK Input clock

Clocks for BOARD0 Device

Device: AM62AX_DEV_BOARD0 (ID = 157)

Note

BOARD0 is a special device that represents the board on which the SoC is mounted.

Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.

Function documented here implies:

Function Description
Input clock Clock is supplied from SoC to the board (It is an output of the SoC)
Output clock Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)

NOTE: Clocks which can be bi-directional are listed as Output clock

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN Input muxed clock
1 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
2 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
3 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
4 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
5 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
6 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
7 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
8 DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
9 DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT Output clock
10 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN Input muxed clock
11 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
12 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
13 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
14 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
15 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
16 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
17 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
18 DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
19 DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT Output clock
20 DEV_BOARD0_CLKOUT0_IN Input muxed clock
21 DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5 Parent input clock option to DEV_BOARD0_CLKOUT0_IN
22 DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 Parent input clock option to DEV_BOARD0_CLKOUT0_IN
23 DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT Output clock
24 DEV_BOARD0_DDR0_CK0_IN Input clock
25 DEV_BOARD0_DDR0_CK0_N_IN Input clock
27 DEV_BOARD0_DDR0_CK0_OUT Output clock
33 DEV_BOARD0_EXT_REFCLK1_OUT Output clock
34 DEV_BOARD0_GPMC0_CLKLB_IN Input clock
35 DEV_BOARD0_GPMC0_CLKLB_OUT Output clock
36 DEV_BOARD0_GPMC0_CLK_IN Input clock
37 DEV_BOARD0_GPMC0_FCLK_MUX_IN Input muxed clock
38 DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN
39 DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN
40 DEV_BOARD0_I2C0_SCL_IN Input clock
41 DEV_BOARD0_I2C0_SCL_OUT Output clock
42 DEV_BOARD0_I2C1_SCL_IN Input clock
43 DEV_BOARD0_I2C1_SCL_OUT Output clock
44 DEV_BOARD0_I2C2_SCL_IN Input clock
45 DEV_BOARD0_I2C2_SCL_OUT Output clock
46 DEV_BOARD0_I2C3_SCL_IN Input clock
47 DEV_BOARD0_I2C3_SCL_OUT Output clock
49 DEV_BOARD0_MCASP0_ACLKR_IN Input clock
50 DEV_BOARD0_MCASP0_ACLKR_OUT Output clock
51 DEV_BOARD0_MCASP0_ACLKX_IN Input clock
52 DEV_BOARD0_MCASP0_ACLKX_OUT Output clock
53 DEV_BOARD0_MCASP0_AFSR_IN Input clock
54 DEV_BOARD0_MCASP0_AFSX_IN Input clock
55 DEV_BOARD0_MCASP1_ACLKR_IN Input clock
56 DEV_BOARD0_MCASP1_ACLKR_OUT Output clock
57 DEV_BOARD0_MCASP1_ACLKX_IN Input clock
58 DEV_BOARD0_MCASP1_ACLKX_OUT Output clock
59 DEV_BOARD0_MCASP1_AFSR_IN Input clock
60 DEV_BOARD0_MCASP1_AFSX_IN Input clock
61 DEV_BOARD0_MCASP2_ACLKR_IN Input clock
62 DEV_BOARD0_MCASP2_ACLKR_OUT Output clock
63 DEV_BOARD0_MCASP2_ACLKX_IN Input clock
64 DEV_BOARD0_MCASP2_ACLKX_OUT Output clock
65 DEV_BOARD0_MCASP2_AFSR_IN Input clock
66 DEV_BOARD0_MCASP2_AFSX_IN Input clock
67 DEV_BOARD0_MCU_EXT_REFCLK0_OUT Output clock
69 DEV_BOARD0_MCU_I2C0_SCL_OUT Output clock
70 DEV_BOARD0_MCU_OBSCLK0_IN Input muxed clock
71 DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
72 DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
73 DEV_BOARD0_MCU_SPI0_CLK_IN Input clock
74 DEV_BOARD0_MCU_SPI0_CLK_OUT Output clock
75 DEV_BOARD0_MCU_SPI1_CLK_IN Input clock
76 DEV_BOARD0_MCU_SPI1_CLK_OUT Output clock
77 DEV_BOARD0_MCU_SYSCLKOUT0_IN Input clock
78 DEV_BOARD0_MCU_TIMER_IO0_IN Input clock
79 DEV_BOARD0_MCU_TIMER_IO1_IN Input clock
80 DEV_BOARD0_MCU_TIMER_IO2_IN Input clock
81 DEV_BOARD0_MCU_TIMER_IO3_IN Input clock
82 DEV_BOARD0_MDIO0_MDC_IN Input clock
83 DEV_BOARD0_MMC0_CLKLB_IN Input clock
84 DEV_BOARD0_MMC0_CLKLB_OUT Output clock
85 DEV_BOARD0_MMC0_CLK_IN Input clock
86 DEV_BOARD0_MMC0_CLK_OUT Output clock
87 DEV_BOARD0_MMC1_CLKLB_IN Input clock
88 DEV_BOARD0_MMC1_CLKLB_OUT Output clock
89 DEV_BOARD0_MMC1_CLK_IN Input clock
90 DEV_BOARD0_MMC1_CLK_OUT Output clock
91 DEV_BOARD0_MMC2_CLKLB_IN Input clock
92 DEV_BOARD0_MMC2_CLKLB_OUT Output clock
93 DEV_BOARD0_MMC2_CLK_IN Input clock
94 DEV_BOARD0_MMC2_CLK_OUT Output clock
95 DEV_BOARD0_OBSCLK0_IN Input muxed clock
96 DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
97 DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_OBSCLK0_IN
128 DEV_BOARD0_OBSCLK1_IN Input clock
129 DEV_BOARD0_OSPI0_DQS_OUT Output clock
130 DEV_BOARD0_OSPI0_LBCLKO_IN Input clock
131 DEV_BOARD0_OSPI0_LBCLKO_OUT Output clock
132 DEV_BOARD0_RGMII1_RXC_OUT Output clock
133 DEV_BOARD0_RGMII1_TXC_IN Input clock
134 DEV_BOARD0_RGMII1_TXC_OUT Output clock
135 DEV_BOARD0_RGMII2_RXC_OUT Output clock
136 DEV_BOARD0_RGMII2_TXC_IN Input clock
137 DEV_BOARD0_RGMII2_TXC_OUT Output clock
138 DEV_BOARD0_RMII1_REF_CLK_OUT Output clock
139 DEV_BOARD0_RMII2_REF_CLK_OUT Output clock
140 DEV_BOARD0_SPI0_CLK_IN Input clock
141 DEV_BOARD0_SPI0_CLK_OUT Output clock
142 DEV_BOARD0_SPI1_CLK_IN Input clock
143 DEV_BOARD0_SPI1_CLK_OUT Output clock
144 DEV_BOARD0_SPI2_CLK_IN Input clock
145 DEV_BOARD0_SPI2_CLK_OUT Output clock
146 DEV_BOARD0_SYSCLKOUT0_IN Input clock
147 DEV_BOARD0_TCK_OUT Output clock
148 DEV_BOARD0_TIMER_IO0_IN Input clock
149 DEV_BOARD0_TIMER_IO1_IN Input clock
150 DEV_BOARD0_TIMER_IO2_IN Input clock
151 DEV_BOARD0_TIMER_IO3_IN Input clock
152 DEV_BOARD0_TIMER_IO4_IN Input clock
153 DEV_BOARD0_TIMER_IO5_IN Input clock
154 DEV_BOARD0_TIMER_IO6_IN Input clock
155 DEV_BOARD0_TIMER_IO7_IN Input clock
156 DEV_BOARD0_TRC_CLK_IN Input clock
157 DEV_BOARD0_VOUT0_EXTPCLKIN_OUT Output clock
158 DEV_BOARD0_VOUT0_PCLK_IN Input clock
159 DEV_BOARD0_WKUP_CLKOUT0_IN Input muxed clock
160 DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0 Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN
161 DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN

Clocks for C7X256V0 Device

This device has no defined clocks.

Clocks for C7X256V0_C7XV_CORE_0 Device

Device: AM62AX_DEV_C7X256V0_C7XV_CORE_0 (ID = 208)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK Input clock

Clocks for C7X256V0_CLEC Device

This device has no defined clocks.

Clocks for C7X256V0_CLK Device

Device: AM62AX_DEV_C7X256V0_CLK (ID = 211)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_C7X256V0_CLK_C7XV_CLK Input clock
1 DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK Output clock
2 DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK Output clock
3 DEV_C7X256V0_CLK_DIVH_CLK4_GCLK Output clock
4 DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK Output clock
5 DEV_C7X256V0_CLK_DIVP_CLK1_GCLK Output clock
6 DEV_C7X256V0_CLK_DIVP_CLK1_SOC_GCLK Output clock
7 DEV_C7X256V0_CLK_PLL_CTRL_CLK Input clock

Clocks for C7X256V0_CORE0 Device

Device: AM62AX_DEV_C7X256V0_CORE0 (ID = 209)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK Input clock
1 DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK Input clock
2 DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK Input clock
3 DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK Input clock
4 DEV_C7X256V0_CORE0_DIVP_CLK1_SOC_GCLK Input clock

Clocks for C7X256V0_DEBUG Device

This device has no defined clocks.

Clocks for C7X256V0_GICSS Device

This device has no defined clocks.

Clocks for C7X256V0_PBIST Device

This device has no defined clocks.

Clocks for C7XV_RSWS_BS_LIMITER6 Device

Device: AM62AX_DEV_C7XV_RSWS_BS_LIMITER6 (ID = 206)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_C7XV_RSWS_BS_LIMITER6_CLK_CLK Input clock

Clocks for CLK_32K_RC_SEL_DEV_VD Device

Device: AM62AX_DEV_CLK_32K_RC_SEL_DEV_VD (ID = 193)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CLK_32K_RC_SEL_DEV_VD_CLK Input muxed clock
1 DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK
2 DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK
3 DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0 Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK
4 DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK

Clocks for CMP_EVENT_INTROUTER0 Device

Device: AM62AX_DEV_CMP_EVENT_INTROUTER0 (ID = 1)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CMP_EVENT_INTROUTER0_INTR_CLK Input clock

Clocks for CODEC0 Device

Device: AM62AX_DEV_CODEC0 (ID = 204)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CODEC0_VPU_ACLK_CLK Input clock
1 DEV_CODEC0_VPU_BCLK_CLK Input clock
2 DEV_CODEC0_VPU_CCLK_CLK Input clock
3 DEV_CODEC0_VPU_PCLK_CLK Input clock

Clocks for CODEC_RS_BW_LIMITER2 Device

Device: AM62AX_DEV_CODEC_RS_BW_LIMITER2 (ID = 221)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CODEC_RS_BW_LIMITER2_CLK_CLK Input clock

Clocks for CODEC_WS_BW_LIMITER3 Device

Device: AM62AX_DEV_CODEC_WS_BW_LIMITER3 (ID = 222)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CODEC_WS_BW_LIMITER3_CLK_CLK Input clock

Clocks for COMPUTE_CLUSTER0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_PBIST_0 Device

This device has no defined clocks.

Clocks for CPSW0 Device

Device: AM62AX_DEV_CPSW0 (ID = 13)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPSW0_CPPI_CLK_CLK Input clock
1 DEV_CPSW0_CPTS_GENF0 Output clock
2 DEV_CPSW0_CPTS_GENF1 Output clock
3 DEV_CPSW0_CPTS_RFT_CLK Input muxed clock
4 DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
5 DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
6 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
8 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
9 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
10 DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
11 DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
13 DEV_CPSW0_GMII1_MR_CLK Input clock
14 DEV_CPSW0_GMII1_MT_CLK Input clock
15 DEV_CPSW0_GMII2_MR_CLK Input clock
16 DEV_CPSW0_GMII2_MT_CLK Input clock
17 DEV_CPSW0_GMII_RFT_CLK Input clock
18 DEV_CPSW0_MDIO_MDCLK_O Output clock
19 DEV_CPSW0_RGMII1_RXC_I Input clock
20 DEV_CPSW0_RGMII1_TXC_I Input clock
21 DEV_CPSW0_RGMII1_TXC_O Output clock
22 DEV_CPSW0_RGMII2_RXC_I Input clock
23 DEV_CPSW0_RGMII2_TXC_I Input clock
24 DEV_CPSW0_RGMII2_TXC_O Output clock
25 DEV_CPSW0_RGMII_MHZ_250_CLK Input clock
26 DEV_CPSW0_RGMII_MHZ_50_CLK Input clock
27 DEV_CPSW0_RGMII_MHZ_5_CLK Input clock
28 DEV_CPSW0_RMII1_MHZ_50_CLK Input clock
29 DEV_CPSW0_RMII2_MHZ_50_CLK Input clock

Clocks for CPT2_AGGR0 Device

Device: AM62AX_DEV_CPT2_AGGR0 (ID = 195)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR0_VCLK_CLK Input clock

Clocks for CPT2_AGGR1 Device

Device: AM62AX_DEV_CPT2_AGGR1 (ID = 194)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR1_VCLK_CLK Input clock

Clocks for CSI_RX_IF0 Device

Device: AM62AX_DEV_CSI_RX_IF0 (ID = 182)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CSI_RX_IF0_MAIN_CLK_CLK Input clock
2 DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK Input clock
3 DEV_CSI_RX_IF0_VBUS_CLK_CLK Input clock
4 DEV_CSI_RX_IF0_VP_CLK_CLK Input clock

Clocks for DBGSUSPENDROUTER0 Device

Device: AM62AX_DEV_DBGSUSPENDROUTER0 (ID = 2)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DBGSUSPENDROUTER0_INTR_CLK Input clock

Clocks for DCC0 Device

Device: AM62AX_DEV_DCC0 (ID = 16)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC0_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC0_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC0_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC0_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC0_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC0_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC0_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC0_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC0_DCC_INPUT00_CLK Input clock
9 DEV_DCC0_DCC_INPUT01_CLK Input clock
10 DEV_DCC0_DCC_INPUT02_CLK Input clock
11 DEV_DCC0_DCC_INPUT10_CLK Input clock
12 DEV_DCC0_VBUS_CLK Input clock

Clocks for DCC1 Device

Device: AM62AX_DEV_DCC1 (ID = 17)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC1_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC1_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC1_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC1_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC1_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC1_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC1_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC1_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC1_DCC_INPUT00_CLK Input clock
9 DEV_DCC1_DCC_INPUT01_CLK Input clock
10 DEV_DCC1_DCC_INPUT02_CLK Input clock
11 DEV_DCC1_DCC_INPUT10_CLK Input clock
12 DEV_DCC1_VBUS_CLK Input clock

Clocks for DCC2 Device

Device: AM62AX_DEV_DCC2 (ID = 18)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC2_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC2_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC2_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC2_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC2_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC2_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC2_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC2_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC2_DCC_INPUT00_CLK Input clock
9 DEV_DCC2_DCC_INPUT01_CLK Input clock
10 DEV_DCC2_DCC_INPUT02_CLK Input clock
11 DEV_DCC2_DCC_INPUT10_CLK Input clock
12 DEV_DCC2_VBUS_CLK Input clock

Clocks for DCC3 Device

Device: AM62AX_DEV_DCC3 (ID = 19)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC3_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC3_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC3_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC3_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC3_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC3_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC3_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC3_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC3_DCC_INPUT00_CLK Input clock
9 DEV_DCC3_DCC_INPUT01_CLK Input clock
10 DEV_DCC3_DCC_INPUT02_CLK Input clock
11 DEV_DCC3_DCC_INPUT10_CLK Input clock
12 DEV_DCC3_VBUS_CLK Input clock

Clocks for DCC4 Device

Device: AM62AX_DEV_DCC4 (ID = 20)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC4_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC4_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC4_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC4_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC4_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC4_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC4_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC4_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC4_DCC_INPUT00_CLK Input clock
9 DEV_DCC4_DCC_INPUT01_CLK Input clock
10 DEV_DCC4_DCC_INPUT02_CLK Input clock
11 DEV_DCC4_DCC_INPUT10_CLK Input clock
12 DEV_DCC4_VBUS_CLK Input clock

Clocks for DCC5 Device

Device: AM62AX_DEV_DCC5 (ID = 21)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC5_DCC_CLKSRC0_CLK Input clock
2 DEV_DCC5_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC5_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC5_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC5_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC5_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC5_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC5_DCC_INPUT00_CLK Input clock
9 DEV_DCC5_DCC_INPUT01_CLK Input clock
10 DEV_DCC5_DCC_INPUT02_CLK Input clock
11 DEV_DCC5_DCC_INPUT10_CLK Input clock
12 DEV_DCC5_VBUS_CLK Input clock

Clocks for DCC6 Device

Device: AM62AX_DEV_DCC6 (ID = 183)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC6_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC6_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC6_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC6_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC6_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC6_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC6_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC6_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC6_DCC_INPUT00_CLK Input clock
9 DEV_DCC6_DCC_INPUT01_CLK Input clock
10 DEV_DCC6_DCC_INPUT02_CLK Input clock
11 DEV_DCC6_DCC_INPUT10_CLK Input clock
12 DEV_DCC6_VBUS_CLK Input clock

Clocks for DDPA0 Device

Device: AM62AX_DEV_DDPA0 (ID = 85)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DDPA0_DDPA_CLK Input clock

Clocks for DDR32SS0 Device

Device: AM62AX_DEV_DDR32SS0 (ID = 170)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DDR32SS0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK Output clock
1 DEV_DDR32SS0_DDRSS_DDR_PLL_CLK Input clock
2 DEV_DDR32SS0_DDRSS_TCK Input clock
3 DEV_DDR32SS0_PLL_CTRL_CLK Input clock

Clocks for DEBUGSS0 Device

Device: AM62AX_DEV_DEBUGSS0 (ID = 171)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DEBUGSS0_CFG_CLK Input clock
1 DEV_DEBUGSS0_DBG_CLK Input clock
2 DEV_DEBUGSS0_SYS_CLK Input clock

Clocks for DEBUGSS_WRAP0 Device

Device: AM62AX_DEV_DEBUGSS_WRAP0 (ID = 24)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DEBUGSS_WRAP0_ATB_CLK Input clock
1 DEV_DEBUGSS_WRAP0_CORE_CLK Input clock
2 DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK Output clock
20 DEV_DEBUGSS_WRAP0_JTAG_TCK Input clock
21 DEV_DEBUGSS_WRAP0_P1500_WRCK Input clock
22 DEV_DEBUGSS_WRAP0_TREXPT_CLK Input clock

Clocks for DMASS0 Device

This device has no defined clocks.

Clocks for DMASS0_BCDMA_0 Device

Device: AM62AX_DEV_DMASS0_BCDMA_0 (ID = 26)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_BCDMA_0_CLK Input clock

Clocks for DMASS0_CBASS_0 Device

Device: AM62AX_DEV_DMASS0_CBASS_0 (ID = 27)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_CBASS_0_CLK Input clock

Clocks for DMASS0_INTAGGR_0 Device

Device: AM62AX_DEV_DMASS0_INTAGGR_0 (ID = 28)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_INTAGGR_0_CLK Input clock

Clocks for DMASS0_IPCSS_0 Device

Device: AM62AX_DEV_DMASS0_IPCSS_0 (ID = 29)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_IPCSS_0_CLK Input clock

Clocks for DMASS0_PKTDMA_0 Device

Device: AM62AX_DEV_DMASS0_PKTDMA_0 (ID = 30)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_PKTDMA_0_CLK Input clock

Clocks for DMASS0_RINGACC_0 Device

Device: AM62AX_DEV_DMASS0_RINGACC_0 (ID = 33)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_RINGACC_0_CLK Input clock

Clocks for DMASS1 Device

This device has no defined clocks.

Clocks for DMASS1_BCDMA_0 Device

Device: AM62AX_DEV_DMASS1_BCDMA_0 (ID = 199)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS1_BCDMA_0_CLK Input clock

Clocks for DMASS1_INTAGGR_0 Device

Device: AM62AX_DEV_DMASS1_INTAGGR_0 (ID = 200)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS1_INTAGGR_0_CLK Input clock

Clocks for DPHY_RX0 Device

Device: AM62AX_DEV_DPHY_RX0 (ID = 185)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
2 DEV_DPHY_RX0_IO_RX_CL_L_M Input clock
2 DEV_DPHY_RX0_IO_RX_CL_L_M Output clock
3 DEV_DPHY_RX0_IO_RX_CL_L_P Input clock
3 DEV_DPHY_RX0_IO_RX_CL_L_P Output clock
4 DEV_DPHY_RX0_JTAG_TCK Input clock
5 DEV_DPHY_RX0_MAIN_CLK_CLK Input clock
6 DEV_DPHY_RX0_PPI_RX_BYTE_CLK Output clock

Clocks for DSS0 Device

Device: AM62AX_DEV_DSS0 (ID = 186)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DSS0_DPI_0_IN_CLK Input clock
2 DEV_DSS0_DPI_1_IN_CLK Input muxed clock
3 DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK Parent input clock option to DEV_DSS0_DPI_1_IN_CLK
4 DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT Parent input clock option to DEV_DSS0_DPI_1_IN_CLK
5 DEV_DSS0_DPI_1_OUT_CLK Output clock
6 DEV_DSS0_DSS_FUNC_CLK Input clock

Clocks for ECAP0 Device

Device: AM62AX_DEV_ECAP0 (ID = 51)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP0_VBUS_CLK Input clock

Clocks for ECAP1 Device

Device: AM62AX_DEV_ECAP1 (ID = 52)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP1_VBUS_CLK Input clock

Clocks for ECAP2 Device

Device: AM62AX_DEV_ECAP2 (ID = 53)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP2_VBUS_CLK Input clock

Clocks for ELM0 Device

Device: AM62AX_DEV_ELM0 (ID = 54)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ELM0_VBUSP_CLK Input clock

Clocks for EMIF_CFG_ISO_VD Device

This device has no defined clocks.

Clocks for EMIF_DATA_ISO_VD Device

This device has no defined clocks.

Clocks for EPWM0 Device

Device: AM62AX_DEV_EPWM0 (ID = 86)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM0_VBUSP_CLK Input clock

Clocks for EPWM1 Device

Device: AM62AX_DEV_EPWM1 (ID = 87)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM1_VBUSP_CLK Input clock

Clocks for EPWM2 Device

Device: AM62AX_DEV_EPWM2 (ID = 88)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM2_VBUSP_CLK Input clock

Clocks for EQEP0 Device

Device: AM62AX_DEV_EQEP0 (ID = 59)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP0_VBUS_CLK Input clock

Clocks for EQEP1 Device

Device: AM62AX_DEV_EQEP1 (ID = 60)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP1_VBUS_CLK Input clock

Clocks for EQEP2 Device

Device: AM62AX_DEV_EQEP2 (ID = 62)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP2_VBUS_CLK Input clock

Clocks for ESM0 Device

Device: AM62AX_DEV_ESM0 (ID = 63)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ESM0_CLK Input clock

Clocks for FSS0 Device

This device has no defined clocks.

Clocks for FSS0_FSAS_0 Device

Device: AM62AX_DEV_FSS0_FSAS_0 (ID = 74)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSS0_FSAS_0_GCLK Input clock

Clocks for FSS0_OSPI_0 Device

Device: AM62AX_DEV_FSS0_OSPI_0 (ID = 75)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSS0_OSPI_0_OSPI_DQS_CLK Input clock
1 DEV_FSS0_OSPI_0_OSPI_HCLK_CLK Input clock
2 DEV_FSS0_OSPI_0_OSPI_ICLK_CLK Input muxed clock
3 DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK
4 DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK
5 DEV_FSS0_OSPI_0_OSPI_OCLK_CLK Output clock
6 DEV_FSS0_OSPI_0_OSPI_PCLK_CLK Input clock
7 DEV_FSS0_OSPI_0_OSPI_RCLK_CLK Input muxed clock
8 DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK
9 DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK

Clocks for GICSS0 Device

Device: AM62AX_DEV_GICSS0 (ID = 76)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GICSS0_VCLK_CLK Input clock

Clocks for GPIO0 Device

Device: AM62AX_DEV_GPIO0 (ID = 77)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO0_MMR_CLK Input clock

Clocks for GPIO1 Device

Device: AM62AX_DEV_GPIO1 (ID = 78)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO1_MMR_CLK Input clock

Clocks for GPMC0 Device

Device: AM62AX_DEV_GPMC0 (ID = 80)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPMC0_FUNC_CLK Input muxed clock
1 DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK Parent input clock option to DEV_GPMC0_FUNC_CLK
2 DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK Parent input clock option to DEV_GPMC0_FUNC_CLK
3 DEV_GPMC0_PI_GPMC_RET_CLK Input clock
4 DEV_GPMC0_PO_GPMC_DEV_CLK Output clock
5 DEV_GPMC0_VBUSM_CLK Input clock

Clocks for HSM0 Device

Device: AM62AX_DEV_HSM0 (ID = 225)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_HSM0_DAP_CLK Input clock

Clocks for I2C0 Device

Device: AM62AX_DEV_I2C0 (ID = 102)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C0_CLK Input clock
1 DEV_I2C0_PISCL Input clock
2 DEV_I2C0_PISYS_CLK Input clock
3 DEV_I2C0_PORSCL Output clock

Clocks for I2C1 Device

Device: AM62AX_DEV_I2C1 (ID = 103)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C1_CLK Input clock
1 DEV_I2C1_PISCL Input clock
2 DEV_I2C1_PISYS_CLK Input clock
3 DEV_I2C1_PORSCL Output clock

Clocks for I2C2 Device

Device: AM62AX_DEV_I2C2 (ID = 104)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C2_CLK Input clock
1 DEV_I2C2_PISCL Input clock
2 DEV_I2C2_PISYS_CLK Input clock
3 DEV_I2C2_PORSCL Output clock

Clocks for I2C3 Device

Device: AM62AX_DEV_I2C3 (ID = 105)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C3_CLK Input clock
1 DEV_I2C3_PISCL Input clock
2 DEV_I2C3_PISYS_CLK Input clock
3 DEV_I2C3_PORSCL Output clock

Clocks for JPGENC0 Device

Device: AM62AX_DEV_JPGENC0 (ID = 201)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_JPGENC0_CORE_CLK Input clock

Clocks for JPGENC_RS_BW_LIMITER4 Device

Device: AM62AX_DEV_JPGENC_RS_BW_LIMITER4 (ID = 215)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_JPGENC_RS_BW_LIMITER4_CLK_CLK Input clock

Clocks for JPGENC_WS_BW_LIMITER5 Device

Device: AM62AX_DEV_JPGENC_WS_BW_LIMITER5 (ID = 216)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_JPGENC_WS_BW_LIMITER5_CLK_CLK Input clock

Clocks for LED0 Device

Device: AM62AX_DEV_LED0 (ID = 83)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_LED0_VBUS_CLK Input clock

Clocks for MAILBOX0 Device

This device has no defined clocks.

Clocks for MAIN2MCU_VD Device

This device has no defined clocks.

Clocks for MAIN_GPIOMUX_INTROUTER0 Device

Device: AM62AX_DEV_MAIN_GPIOMUX_INTROUTER0 (ID = 3)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK Input clock

Clocks for MAIN_USB0_ISO_VD Device

This device has no defined clocks.

Clocks for MAIN_USB1_ISO_VD Device

This device has no defined clocks.

Clocks for MCAN0 Device

Device: AM62AX_DEV_MCAN0 (ID = 98)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_MCAN0_MCANSS_CCLK_CLK Input muxed clock
2 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
3 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
4 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
5 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
6 DEV_MCAN0_MCANSS_HCLK_CLK Input clock

Clocks for MCASP0 Device

Device: AM62AX_DEV_MCASP0 (ID = 190)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCASP0_AUX_CLK Input muxed clock
1 DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK Parent input clock option to DEV_MCASP0_AUX_CLK
2 DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK Parent input clock option to DEV_MCASP0_AUX_CLK
3 DEV_MCASP0_MCASP_ACLKR_PIN Input clock
4 DEV_MCASP0_MCASP_ACLKR_POUT Output clock
5 DEV_MCASP0_MCASP_ACLKX_PIN Input clock
6 DEV_MCASP0_MCASP_ACLKX_POUT Output clock
7 DEV_MCASP0_MCASP_AFSR_POUT Output clock
8 DEV_MCASP0_MCASP_AFSX_POUT Output clock
9 DEV_MCASP0_MCASP_AHCLKR_PIN Input muxed clock
10 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
11 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
12 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
13 DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN
14 DEV_MCASP0_MCASP_AHCLKR_POUT Output clock
15 DEV_MCASP0_MCASP_AHCLKX_PIN Input muxed clock
16 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
17 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
18 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
19 DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN
20 DEV_MCASP0_MCASP_AHCLKX_POUT Output clock
21 DEV_MCASP0_VBUSP_CLK Input clock

Clocks for MCASP1 Device

Device: AM62AX_DEV_MCASP1 (ID = 191)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCASP1_AUX_CLK Input muxed clock
1 DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK Parent input clock option to DEV_MCASP1_AUX_CLK
2 DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK Parent input clock option to DEV_MCASP1_AUX_CLK
3 DEV_MCASP1_MCASP_ACLKR_PIN Input clock
4 DEV_MCASP1_MCASP_ACLKR_POUT Output clock
5 DEV_MCASP1_MCASP_ACLKX_PIN Input clock
6 DEV_MCASP1_MCASP_ACLKX_POUT Output clock
7 DEV_MCASP1_MCASP_AFSR_POUT Output clock
8 DEV_MCASP1_MCASP_AFSX_POUT Output clock
9 DEV_MCASP1_MCASP_AHCLKR_PIN Input muxed clock
10 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
11 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
12 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
13 DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN
14 DEV_MCASP1_MCASP_AHCLKR_POUT Output clock
15 DEV_MCASP1_MCASP_AHCLKX_PIN Input muxed clock
16 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
17 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
18 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
19 DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN
20 DEV_MCASP1_MCASP_AHCLKX_POUT Output clock
21 DEV_MCASP1_VBUSP_CLK Input clock

Clocks for MCASP2 Device

Device: AM62AX_DEV_MCASP2 (ID = 192)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCASP2_AUX_CLK Input muxed clock
1 DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK Parent input clock option to DEV_MCASP2_AUX_CLK
2 DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK Parent input clock option to DEV_MCASP2_AUX_CLK
3 DEV_MCASP2_MCASP_ACLKR_PIN Input clock
4 DEV_MCASP2_MCASP_ACLKR_POUT Output clock
5 DEV_MCASP2_MCASP_ACLKX_PIN Input clock
6 DEV_MCASP2_MCASP_ACLKX_POUT Output clock
7 DEV_MCASP2_MCASP_AFSR_POUT Output clock
8 DEV_MCASP2_MCASP_AFSX_POUT Output clock
9 DEV_MCASP2_MCASP_AHCLKR_PIN Input muxed clock
10 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
11 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
12 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
13 DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN
14 DEV_MCASP2_MCASP_AHCLKR_POUT Output clock
15 DEV_MCASP2_MCASP_AHCLKX_PIN Input muxed clock
16 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
17 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
18 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
19 DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN
20 DEV_MCASP2_MCASP_AHCLKX_POUT Output clock
21 DEV_MCASP2_VBUSP_CLK Input clock

Clocks for MCRC64_0 Device

Device: AM62AX_DEV_MCRC64_0 (ID = 116)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCRC64_0_CLK Input clock

Clocks for MCSPI0 Device

Device: AM62AX_DEV_MCSPI0 (ID = 141)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI0_CLKSPIREF_CLK Input clock
2 DEV_MCSPI0_IO_CLKSPIO_CLK Output clock
3 DEV_MCSPI0_VBUSP_CLK Input clock
4 DEV_MCSPI0_IO_CLKSPII_CLK Input muxed clock
5 DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK
6 DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK

Clocks for MCSPI1 Device

Device: AM62AX_DEV_MCSPI1 (ID = 142)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI1_CLKSPIREF_CLK Input clock
2 DEV_MCSPI1_IO_CLKSPIO_CLK Output clock
3 DEV_MCSPI1_VBUSP_CLK Input clock
4 DEV_MCSPI1_IO_CLKSPII_CLK Input muxed clock
5 DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK
6 DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK

Clocks for MCSPI2 Device

Device: AM62AX_DEV_MCSPI2 (ID = 143)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI2_CLKSPIREF_CLK Input clock
2 DEV_MCSPI2_IO_CLKSPIO_CLK Output clock
3 DEV_MCSPI2_VBUSP_CLK Input clock
4 DEV_MCSPI2_IO_CLKSPII_CLK Input muxed clock
5 DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK
6 DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK

Clocks for MCU_CPT2_AGGR0 Device

Device: AM62AX_DEV_MCU_CPT2_AGGR0 (ID = 196)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_CPT2_AGGR0_VCLK_CLK Input clock

Clocks for MCU_DCC0 Device

Device: AM62AX_DEV_MCU_DCC0 (ID = 23)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_DCC0_DCC_CLKSRC0_CLK Input clock
1 DEV_MCU_DCC0_DCC_CLKSRC1_CLK Input clock
2 DEV_MCU_DCC0_DCC_CLKSRC2_CLK Input clock
3 DEV_MCU_DCC0_DCC_CLKSRC3_CLK Input clock
4 DEV_MCU_DCC0_DCC_CLKSRC4_CLK Input clock
5 DEV_MCU_DCC0_DCC_CLKSRC5_CLK Input clock
6 DEV_MCU_DCC0_DCC_CLKSRC6_CLK Input clock
7 DEV_MCU_DCC0_DCC_CLKSRC7_CLK Input clock
8 DEV_MCU_DCC0_DCC_INPUT00_CLK Input clock
9 DEV_MCU_DCC0_DCC_INPUT01_CLK Input clock
10 DEV_MCU_DCC0_DCC_INPUT02_CLK Input clock
11 DEV_MCU_DCC0_DCC_INPUT10_CLK Input clock
12 DEV_MCU_DCC0_VBUS_CLK Input clock

Clocks for MCU_DCC1 Device

Device: AM62AX_DEV_MCU_DCC1 (ID = 197)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_DCC1_DCC_CLKSRC0_CLK Input clock
1 DEV_MCU_DCC1_DCC_CLKSRC1_CLK Input clock
5 DEV_MCU_DCC1_DCC_CLKSRC5_CLK Input clock
6 DEV_MCU_DCC1_DCC_CLKSRC6_CLK Input clock
7 DEV_MCU_DCC1_DCC_CLKSRC7_CLK Input clock
8 DEV_MCU_DCC1_DCC_INPUT00_CLK Input clock
9 DEV_MCU_DCC1_DCC_INPUT01_CLK Input clock
10 DEV_MCU_DCC1_DCC_INPUT02_CLK Input clock
11 DEV_MCU_DCC1_DCC_INPUT10_CLK Input clock
12 DEV_MCU_DCC1_VBUS_CLK Input clock

Clocks for MCU_GPIO0 Device

Device: AM62AX_DEV_MCU_GPIO0 (ID = 79)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_GPIO0_MMR_CLK Input muxed clock
1 DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_GPIO0_MMR_CLK
2 DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT Parent input clock option to DEV_MCU_GPIO0_MMR_CLK
3 DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_GPIO0_MMR_CLK
4 DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_GPIO0_MMR_CLK

Clocks for MCU_I2C0 Device

Device: AM62AX_DEV_MCU_I2C0 (ID = 106)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_I2C0_CLK Input clock
1 DEV_MCU_I2C0_PISCL Input clock
2 DEV_MCU_I2C0_PISYS_CLK Input clock
3 DEV_MCU_I2C0_PORSCL Output clock

Clocks for MCU_MCAN0 Device

Device: AM62AX_DEV_MCU_MCAN0 (ID = 188)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_MCU_MCAN0_MCANSS_CCLK_CLK Input muxed clock
2 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
3 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
4 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
5 DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK
6 DEV_MCU_MCAN0_MCANSS_HCLK_CLK Input clock

Clocks for MCU_MCAN1 Device

Device: AM62AX_DEV_MCU_MCAN1 (ID = 189)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_MCU_MCAN1_MCANSS_CCLK_CLK Input muxed clock
2 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
3 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
4 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
5 DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK
6 DEV_MCU_MCAN1_MCANSS_HCLK_CLK Input clock

Clocks for MCU_MCRC64_0 Device

Device: AM62AX_DEV_MCU_MCRC64_0 (ID = 100)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCRC64_0_CLK Input clock

Clocks for MCU_MCSPI0 Device

Device: AM62AX_DEV_MCU_MCSPI0 (ID = 147)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCSPI0_CLKSPIREF_CLK Input clock
2 DEV_MCU_MCSPI0_IO_CLKSPIO_CLK Output clock
3 DEV_MCU_MCSPI0_VBUSP_CLK Input clock
4 DEV_MCU_MCSPI0_IO_CLKSPII_CLK Input muxed clock
5 DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK
6 DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK

Clocks for MCU_MCSPI1 Device

Device: AM62AX_DEV_MCU_MCSPI1 (ID = 148)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCSPI1_CLKSPIREF_CLK Input clock
2 DEV_MCU_MCSPI1_IO_CLKSPIO_CLK Output clock
3 DEV_MCU_MCSPI1_VBUSP_CLK Input clock
4 DEV_MCU_MCSPI1_IO_CLKSPII_CLK Input muxed clock
5 DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK
6 DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK

Clocks for MCU_MCU_16FF0 Device

Device: AM62AX_DEV_MCU_MCU_16FF0 (ID = 180)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
3 DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK Input clock

Clocks for MCU_OBSCLK_MUX_SEL_DEV_VD Device

Device: AM62AX_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD (ID = 227)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK Input muxed clock
1 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
2 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
3 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
4 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0 Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
5 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
6 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
7 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
8 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
9 DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK

Clocks for MCU_PBIST0 Device

Device: AM62AX_DEV_MCU_PBIST0 (ID = 203)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
7 DEV_MCU_PBIST0_CLK8_CLK Input clock

Clocks for MCU_R5FSS0 Device

This device has no defined clocks.

Clocks for MCU_R5FSS0_CORE0 Device

Device: AM62AX_DEV_MCU_R5FSS0_CORE0 (ID = 9)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_R5FSS0_CORE0_CPU0_CLK Input clock
1 DEV_MCU_R5FSS0_CORE0_INTERFACE0_CLK Input clock

Clocks for MCU_RTI0 Device

Device: AM62AX_DEV_MCU_RTI0 (ID = 131)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_RTI0_RTI_CLK Input muxed clock
1 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_RTI0_RTI_CLK
2 DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_MCU_RTI0_RTI_CLK
3 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_RTI0_RTI_CLK
4 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_RTI0_RTI_CLK
5 DEV_MCU_RTI0_VBUSP_CLK Input clock

Clocks for MCU_TIMER0 Device

Device: AM62AX_DEV_MCU_TIMER0 (ID = 35)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER0_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER0_TIMER_PWM Output clock
2 DEV_MCU_TIMER0_TIMER_TCLK_CLK Input muxed clock
3 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
4 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
5 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
6 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
7 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
8 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
9 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
10 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK

Clocks for MCU_TIMER1 Device

Device: AM62AX_DEV_MCU_TIMER1 (ID = 48)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER1_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER1_TIMER_PWM Output clock
2 DEV_MCU_TIMER1_TIMER_TCLK_CLK Input muxed clock
3 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1 Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
4 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK

Clocks for MCU_TIMER2 Device

Device: AM62AX_DEV_MCU_TIMER2 (ID = 49)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER2_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER2_TIMER_PWM Output clock
2 DEV_MCU_TIMER2_TIMER_TCLK_CLK Input muxed clock
3 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
4 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
5 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
6 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
7 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
8 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
9 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
10 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK

Clocks for MCU_TIMER3 Device

Device: AM62AX_DEV_MCU_TIMER3 (ID = 50)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER3_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER3_TIMER_PWM Output clock
2 DEV_MCU_TIMER3_TIMER_TCLK_CLK Input muxed clock
3 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3 Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
4 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK

Clocks for MCU_UART0 Device

Device: AM62AX_DEV_MCU_UART0 (ID = 149)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_UART0_FCLK_CLK Input clock
3 DEV_MCU_UART0_VBUSP_CLK Input clock

Clocks for MMCSD0 Device

Device: AM62AX_DEV_MMCSD0 (ID = 57)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD0_EMMCSDSS_IO_CLK_I Input muxed clock
1 DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I
2 DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I
3 DEV_MMCSD0_EMMCSDSS_IO_CLK_O Output clock
5 DEV_MMCSD0_EMMCSDSS_VBUS_CLK Input clock
6 DEV_MMCSD0_EMMCSDSS_XIN_CLK Input muxed clock
7 DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK
8 DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK

Clocks for MMCSD1 Device

Device: AM62AX_DEV_MMCSD1 (ID = 58)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD1_EMMCSDSS_IO_CLK_I Input muxed clock
1 DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I
2 DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I
3 DEV_MMCSD1_EMMCSDSS_IO_CLK_O Output clock
5 DEV_MMCSD1_EMMCSDSS_VBUS_CLK Input clock
6 DEV_MMCSD1_EMMCSDSS_XIN_CLK Input muxed clock
7 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
8 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK

Clocks for MMCSD2 Device

Device: AM62AX_DEV_MMCSD2 (ID = 184)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD2_EMMCSDSS_IO_CLK_I Input muxed clock
1 DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I
2 DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT Parent input clock option to DEV_MMCSD2_EMMCSDSS_IO_CLK_I
3 DEV_MMCSD2_EMMCSDSS_IO_CLK_O Output clock
5 DEV_MMCSD2_EMMCSDSS_VBUS_CLK Input clock
6 DEV_MMCSD2_EMMCSDSS_XIN_CLK Input muxed clock
7 DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK
8 DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK

Clocks for OBSCLK0_MUX_SEL_DEV_VD Device

Device: AM62AX_DEV_OBSCLK0_MUX_SEL_DEV_VD (ID = 228)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK Input muxed clock
1 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
2 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
3 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
4 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
5 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
6 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
7 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
8 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
9 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
10 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
11 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_C7XV_WRAP_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
12 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
13 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
14 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_DDR_WRAP_MAIN_0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
15 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
16 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
17 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
18 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
19 DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK

Clocks for PBIST0 Device

Device: AM62AX_DEV_PBIST0 (ID = 163)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
7 DEV_PBIST0_CLK8_CLK Input clock
9 DEV_PBIST0_TCLK_CLK Input clock

Clocks for PBIST3 Device

Device: AM62AX_DEV_PBIST3 (ID = 220)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_PBIST3_CLK8_CLK Input clock

Clocks for PSC0 Device

Device: AM62AX_DEV_PSC0 (ID = 169)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PSC0_CLK Input clock
1 DEV_PSC0_SLOW_CLK Input clock

Clocks for PSC0_FW_0 Device

Device: AM62AX_DEV_PSC0_FW_0 (ID = 168)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PSC0_FW_0_CLK Input clock

Clocks for PSCSS0 Device

This device has no defined clocks.

Clocks for R5FSS0 Device

This device has no defined clocks.

Clocks for R5FSS0_CORE0 Device

Device: AM62AX_DEV_R5FSS0_CORE0 (ID = 121)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS0_CORE0_CPU_CLK Input muxed clock
1 DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT2_CLK Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK
2 DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK
5 DEV_R5FSS0_CORE0_INTERFACE_CLK Input clock

Clocks for R5FSS0_SS0 Device

This device has no defined clocks.

Clocks for RTI0 Device

Device: AM62AX_DEV_RTI0 (ID = 125)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI0_RTI_CLK Input muxed clock
1 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI0_RTI_CLK
2 DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_RTI0_RTI_CLK
3 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI0_RTI_CLK
4 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI0_RTI_CLK
5 DEV_RTI0_VBUSP_CLK Input clock

Clocks for RTI1 Device

Device: AM62AX_DEV_RTI1 (ID = 126)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI1_RTI_CLK Input muxed clock
1 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI1_RTI_CLK
2 DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_RTI1_RTI_CLK
3 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI1_RTI_CLK
4 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI1_RTI_CLK
5 DEV_RTI1_VBUSP_CLK Input clock

Clocks for RTI2 Device

Device: AM62AX_DEV_RTI2 (ID = 127)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI2_RTI_CLK Input muxed clock
1 DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI2_RTI_CLK
2 DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_RTI2_RTI_CLK
3 DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI2_RTI_CLK
4 DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI2_RTI_CLK
5 DEV_RTI2_VBUSP_CLK Input clock

Clocks for RTI3 Device

Device: AM62AX_DEV_RTI3 (ID = 128)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI3_RTI_CLK Input muxed clock
1 DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI3_RTI_CLK
2 DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_RTI3_RTI_CLK
3 DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI3_RTI_CLK
4 DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI3_RTI_CLK
5 DEV_RTI3_VBUSP_CLK Input clock

Clocks for RTI4 Device

Device: AM62AX_DEV_RTI4 (ID = 205)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI4_RTI_CLK Input muxed clock
1 DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI4_RTI_CLK
2 DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_RTI4_RTI_CLK
3 DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI4_RTI_CLK
4 DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI4_RTI_CLK
5 DEV_RTI4_VBUSP_CLK Input clock

Clocks for SMS0 Device

This device has no defined clocks.

Clocks for SPINLOCK0 Device

Device: AM62AX_DEV_SPINLOCK0 (ID = 150)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_SPINLOCK0_VCLK_CLK Input clock

Clocks for STM0 Device

Device: AM62AX_DEV_STM0 (ID = 15)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_STM0_ATB_CLK Input clock
1 DEV_STM0_CORE_CLK Input clock
2 DEV_STM0_VBUSP_CLK Input clock

Clocks for TIMER0 Device

Device: AM62AX_DEV_TIMER0 (ID = 36)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER0_TIMER_HCLK_CLK Input clock
1 DEV_TIMER0_TIMER_PWM Output clock
2 DEV_TIMER0_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
4 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
5 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
6 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
7 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
8 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
10 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
11 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
12 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
13 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
14 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
15 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK

Clocks for TIMER1 Device

Device: AM62AX_DEV_TIMER1 (ID = 37)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER1_TIMER_HCLK_CLK Input clock
1 DEV_TIMER1_TIMER_PWM Output clock
2 DEV_TIMER1_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
4 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK

Clocks for TIMER2 Device

Device: AM62AX_DEV_TIMER2 (ID = 38)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER2_TIMER_HCLK_CLK Input clock
1 DEV_TIMER2_TIMER_PWM Output clock
2 DEV_TIMER2_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
4 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
5 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
6 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
7 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
8 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
10 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
11 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
12 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
13 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
14 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
15 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK

Clocks for TIMER3 Device

Device: AM62AX_DEV_TIMER3 (ID = 39)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER3_TIMER_HCLK_CLK Input clock
1 DEV_TIMER3_TIMER_PWM Output clock
2 DEV_TIMER3_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
4 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK

Clocks for TIMER4 Device

Device: AM62AX_DEV_TIMER4 (ID = 40)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER4_TIMER_HCLK_CLK Input clock
1 DEV_TIMER4_TIMER_PWM Output clock
2 DEV_TIMER4_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
4 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
5 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
6 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
7 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
8 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
10 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
11 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
12 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
13 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
14 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
15 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK

Clocks for TIMER5 Device

Device: AM62AX_DEV_TIMER5 (ID = 41)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER5_TIMER_HCLK_CLK Input clock
1 DEV_TIMER5_TIMER_PWM Output clock
2 DEV_TIMER5_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
4 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK

Clocks for TIMER6 Device

Device: AM62AX_DEV_TIMER6 (ID = 42)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER6_TIMER_HCLK_CLK Input clock
1 DEV_TIMER6_TIMER_PWM Output clock
2 DEV_TIMER6_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
4 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
5 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
6 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
7 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
8 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
10 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
11 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
12 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
13 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
14 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
15 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK

Clocks for TIMER7 Device

Device: AM62AX_DEV_TIMER7 (ID = 43)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER7_TIMER_HCLK_CLK Input clock
1 DEV_TIMER7_TIMER_PWM Output clock
2 DEV_TIMER7_TIMER_TCLK_CLK Input muxed clock
3 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
4 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK

Clocks for TIMESYNC_EVENT_ROUTER0 Device

Device: AM62AX_DEV_TIMESYNC_EVENT_ROUTER0 (ID = 6)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMESYNC_EVENT_ROUTER0_INTR_CLK Input clock

Clocks for UART0 Device

Device: AM62AX_DEV_UART0 (ID = 146)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART0_FCLK_CLK Input muxed clock
1 DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0 Parent input clock option to DEV_UART0_FCLK_CLK
2 DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART0_FCLK_CLK
5 DEV_UART0_VBUSP_CLK Input clock

Clocks for UART1 Device

Device: AM62AX_DEV_UART1 (ID = 152)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART1_FCLK_CLK Input muxed clock
1 DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1 Parent input clock option to DEV_UART1_FCLK_CLK
2 DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART1_FCLK_CLK
5 DEV_UART1_VBUSP_CLK Input clock

Clocks for UART2 Device

Device: AM62AX_DEV_UART2 (ID = 153)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART2_FCLK_CLK Input muxed clock
1 DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2 Parent input clock option to DEV_UART2_FCLK_CLK
2 DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART2_FCLK_CLK
5 DEV_UART2_VBUSP_CLK Input clock

Clocks for UART3 Device

Device: AM62AX_DEV_UART3 (ID = 154)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART3_FCLK_CLK Input muxed clock
1 DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3 Parent input clock option to DEV_UART3_FCLK_CLK
2 DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART3_FCLK_CLK
5 DEV_UART3_VBUSP_CLK Input clock

Clocks for UART4 Device

Device: AM62AX_DEV_UART4 (ID = 155)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART4_FCLK_CLK Input muxed clock
1 DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4 Parent input clock option to DEV_UART4_FCLK_CLK
2 DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART4_FCLK_CLK
5 DEV_UART4_VBUSP_CLK Input clock

Clocks for UART5 Device

Device: AM62AX_DEV_UART5 (ID = 156)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART5_FCLK_CLK Input muxed clock
1 DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5 Parent input clock option to DEV_UART5_FCLK_CLK
2 DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART5_FCLK_CLK
5 DEV_UART5_VBUSP_CLK Input clock

Clocks for UART6 Device

Device: AM62AX_DEV_UART6 (ID = 158)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART6_FCLK_CLK Input muxed clock
1 DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6 Parent input clock option to DEV_UART6_FCLK_CLK
2 DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART6_FCLK_CLK
5 DEV_UART6_VBUSP_CLK Input clock

Clocks for USB0 Device

Device: AM62AX_DEV_USB0 (ID = 161)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_USB0_BUS_CLK Input clock
1 DEV_USB0_CFG_CLK Input clock
2 DEV_USB0_USB2_APB_PCLK_CLK Input clock
3 DEV_USB0_USB2_REFCLOCK_CLK Input muxed clock
4 DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
5 DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
10 DEV_USB0_USB2_TAP_TCK Input clock

Clocks for USB1 Device

Device: AM62AX_DEV_USB1 (ID = 162)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_USB1_BUS_CLK Input clock
1 DEV_USB1_CFG_CLK Input clock
2 DEV_USB1_USB2_APB_PCLK_CLK Input clock
3 DEV_USB1_USB2_REFCLOCK_CLK Input muxed clock
4 DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK
5 DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK
10 DEV_USB1_USB2_TAP_TCK Input clock

Clocks for VPAC0 Device

Device: AM62AX_DEV_VPAC0 (ID = 219)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
1 DEV_VPAC0_PLL_CTRL_CLK Input clock
3 DEV_VPAC0_VPAC_PLL_CFG_CLK Input clock
4 DEV_VPAC0_VPAC_PLL_CLK Input clock

Clocks for VPAC_RSWS_BW_LIMITER7 Device

Device: AM62AX_DEV_VPAC_RSWS_BW_LIMITER7 (ID = 218)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_VPAC_RSWS_BW_LIMITER7_CLK_CLK Input clock

Clocks for VPAC_RSWS_BW_LIMITER8 Device

Device: AM62AX_DEV_VPAC_RSWS_BW_LIMITER8 (ID = 217)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_VPAC_RSWS_BW_LIMITER8_CLK_CLK Input clock

Clocks for WKUP_CLKOUT_SEL_DEV_VD Device

Device: AM62AX_DEV_WKUP_CLKOUT_SEL_DEV_VD (ID = 226)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK Input muxed clock
1 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
2 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
3 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
4 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
5 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
6 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
7 DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK

Clocks for WKUP_DEEPSLEEP_SOURCES0 Device

Device: AM62AX_DEV_WKUP_DEEPSLEEP_SOURCES0 (ID = 176)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK Input clock

Clocks for WKUP_ESM0 Device

Device: AM62AX_DEV_WKUP_ESM0 (ID = 64)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_ESM0_CLK Input clock

Clocks for WKUP_GTC0 Device

Device: AM62AX_DEV_WKUP_GTC0 (ID = 61)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_GTC0_GTC_CLK Input muxed clock
1 DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
2 DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
3 DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
5 DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
6 DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
7 DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2 Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
8 DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_WKUP_GTC0_GTC_CLK
9 DEV_WKUP_GTC0_VBUSP_CLK Input muxed clock
10 DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK
11 DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK

Clocks for WKUP_I2C0 Device

Device: AM62AX_DEV_WKUP_I2C0 (ID = 107)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_I2C0_CLK Input muxed clock
1 DEV_WKUP_I2C0_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_I2C0_CLK
2 DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_I2C0_CLK
4 DEV_WKUP_I2C0_PISYS_CLK Input clock
5 DEV_WKUP_I2C0_PORSCL Output clock

Clocks for WKUP_MCU_GPIOMUX_INTROUTER0 Device

Device: AM62AX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 (ID = 5)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK Input clock

Clocks for WKUP_PBIST0 Device

Device: AM62AX_DEV_WKUP_PBIST0 (ID = 165)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
7 DEV_WKUP_PBIST0_CLK8_CLK Input clock

Clocks for WKUP_PBIST1 Device

This device has no defined clocks.

Clocks for WKUP_PSC0 Device

Device: AM62AX_DEV_WKUP_PSC0 (ID = 140)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_PSC0_CLK Input clock
1 DEV_WKUP_PSC0_SLOW_CLK Input clock

Clocks for WKUP_RTCSS0 Device

Device: AM62AX_DEV_WKUP_RTCSS0 (ID = 117)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_RTCSS0_ANA_OSC32K_CLK Input muxed clock
1 DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK
2 DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK
4 DEV_WKUP_RTCSS0_JTAG_WRCK Input clock
6 DEV_WKUP_RTCSS0_VCLK_CLK Input muxed clock
7 DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK
8 DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK

Clocks for WKUP_RTI0 Device

Device: AM62AX_DEV_WKUP_RTI0 (ID = 132)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_RTI0_RTI_CLK Input muxed clock
1 DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_WKUP_RTI0_RTI_CLK
2 DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_WKUP_RTI0_RTI_CLK
3 DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_WKUP_RTI0_RTI_CLK
4 DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_WKUP_RTI0_RTI_CLK
5 DEV_WKUP_RTI0_VBUSP_CLK Input muxed clock
6 DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK
7 DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK

Clocks for WKUP_TIMER0 Device

Device: AM62AX_DEV_WKUP_TIMER0 (ID = 110)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_TIMER0_TIMER_HCLK_CLK Input muxed clock
1 DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK
2 DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK
3 DEV_WKUP_TIMER0_TIMER_PWM Output clock
4 DEV_WKUP_TIMER0_TIMER_TCLK_CLK Input muxed clock
5 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
6 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04 Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
7 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
8 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
9 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
10 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
11 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK
12 DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK

Clocks for WKUP_TIMER1 Device

Device: AM62AX_DEV_WKUP_TIMER1 (ID = 111)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_TIMER1_TIMER_HCLK_CLK Input muxed clock
1 DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK
2 DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK
4 DEV_WKUP_TIMER1_TIMER_TCLK_CLK Input muxed clock
5 DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1 Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK
6 DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM Parent input clock option to DEV_WKUP_TIMER1_TIMER_TCLK_CLK

Clocks for WKUP_UART0 Device

Device: AM62AX_DEV_WKUP_UART0 (ID = 114)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_UART0_FCLK_CLK Input clock
3 DEV_WKUP_UART0_VBUSP_CLK Input muxed clock
4 DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK
5 DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK

Clocks for WKUP_VTM0 Device

Device: AM62AX_DEV_WKUP_VTM0 (ID = 95)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_WKUP_VTM0_FIX_REF2_CLK Input clock
1 DEV_WKUP_VTM0_FIX_REF_CLK Input clock
2 DEV_WKUP_VTM0_VBUSP_CLK Input muxed clock
3 DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK
4 DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK