AM275X Clock Identifiers¶
Clock for AM275X Device¶
This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in AM275X SoC.
TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.
Device wise clock ID list for AM275X SoC¶
This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs
The following table describes functions implemented by clocks
| Function | Description |
|---|---|
| Input clock | Clock input to the SoC subsystem |
| Output clock | Clock output from the SoC subsystem |
| Input muxed clock | Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source |
| Parent input clock option to XYZ | One of the parent clocks that can be used as a source clock to a input muxed clock |
Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:
This device has no defined clocks.
The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.
Clocks for AASRC0 Device¶
Device: AM275X_DEV_AASRC0 (ID = 299)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 8 | DEV_AASRC0_RX0_SYNC_CLK | Input muxed clock |
| 9 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 10 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 11 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 12 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 13 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 17 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 18 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 19 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 20 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 21 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 25 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 26 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 27 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 29 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 30 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 31 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 33 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 34 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 35 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 36 | DEV_AASRC0_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_RX0_SYNC_CLK |
| 41 | DEV_AASRC0_RX1_SYNC_CLK | Input muxed clock |
| 42 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 43 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 44 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 45 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 46 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 50 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 51 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 52 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 53 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 54 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 58 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 59 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 60 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 62 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 63 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 64 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 66 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 67 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 68 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 69 | DEV_AASRC0_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_RX1_SYNC_CLK |
| 74 | DEV_AASRC0_RX2_SYNC_CLK | Input muxed clock |
| 75 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 76 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 77 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 78 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 79 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 83 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 84 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 85 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 86 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 87 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 91 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 92 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 93 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 95 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 96 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 97 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 99 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 100 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 101 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 102 | DEV_AASRC0_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_RX2_SYNC_CLK |
| 107 | DEV_AASRC0_RX3_SYNC_CLK | Input muxed clock |
| 108 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 109 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 110 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 111 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 112 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 116 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 117 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 118 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 119 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 120 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 124 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 125 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 126 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 128 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 129 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 130 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 132 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 133 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 134 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 135 | DEV_AASRC0_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_RX3_SYNC_CLK |
| 144 | DEV_AASRC0_SYS_CLK | Input clock |
| 145 | DEV_AASRC0_TX0_SYNC_CLK | Input muxed clock |
| 146 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 147 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 148 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 149 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 150 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 154 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 155 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 156 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 157 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 158 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 162 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 163 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 164 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 166 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 167 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 168 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 170 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 171 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 172 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 173 | DEV_AASRC0_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_TX0_SYNC_CLK |
| 178 | DEV_AASRC0_TX1_SYNC_CLK | Input muxed clock |
| 179 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 180 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 181 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 182 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 183 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 187 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 188 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 189 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 190 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 191 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 195 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 196 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 197 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 199 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 200 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 201 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 203 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 204 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 205 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 206 | DEV_AASRC0_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_TX1_SYNC_CLK |
| 211 | DEV_AASRC0_TX2_SYNC_CLK | Input muxed clock |
| 212 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 213 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 214 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 215 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 216 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 220 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 221 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 222 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 223 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 224 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 228 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 229 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 230 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 232 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 233 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 234 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 236 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 237 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 238 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 239 | DEV_AASRC0_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_TX2_SYNC_CLK |
| 244 | DEV_AASRC0_TX3_SYNC_CLK | Input muxed clock |
| 245 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 246 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 247 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 248 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 249 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 253 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 254 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 255 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 256 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 257 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 261 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 262 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 263 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 265 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 266 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 267 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 269 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 270 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 271 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 272 | DEV_AASRC0_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC0_TX3_SYNC_CLK |
| 281 | DEV_AASRC0_VBUSP_CLK | Input clock |
Clocks for AASRC1 Device¶
Device: AM275X_DEV_AASRC1 (ID = 300)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 8 | DEV_AASRC1_RX0_SYNC_CLK | Input muxed clock |
| 9 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 10 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 11 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 12 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 13 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 17 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 18 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 19 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 20 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 21 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 25 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 26 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 27 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 29 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 30 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 31 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 33 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 34 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 35 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 36 | DEV_AASRC1_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_RX0_SYNC_CLK |
| 41 | DEV_AASRC1_RX1_SYNC_CLK | Input muxed clock |
| 42 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 43 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 44 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 45 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 46 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 50 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 51 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 52 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 53 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 54 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 58 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 59 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 60 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 62 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 63 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 64 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 66 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 67 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 68 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 69 | DEV_AASRC1_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_RX1_SYNC_CLK |
| 74 | DEV_AASRC1_RX2_SYNC_CLK | Input muxed clock |
| 75 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 76 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 77 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 78 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 79 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 83 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 84 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 85 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 86 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 87 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 91 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 92 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 93 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 95 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 96 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 97 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 99 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 100 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 101 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 102 | DEV_AASRC1_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_RX2_SYNC_CLK |
| 107 | DEV_AASRC1_RX3_SYNC_CLK | Input muxed clock |
| 108 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 109 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 110 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 111 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 112 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 116 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 117 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 118 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 119 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 120 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 124 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 125 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 126 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 128 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 129 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 130 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 132 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 133 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 134 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 135 | DEV_AASRC1_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_RX3_SYNC_CLK |
| 144 | DEV_AASRC1_SYS_CLK | Input clock |
| 145 | DEV_AASRC1_TX0_SYNC_CLK | Input muxed clock |
| 146 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 147 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 148 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 149 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 150 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 154 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 155 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 156 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 157 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 158 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 162 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 163 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 164 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 166 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 167 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 168 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 170 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 171 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 172 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 173 | DEV_AASRC1_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_TX0_SYNC_CLK |
| 178 | DEV_AASRC1_TX1_SYNC_CLK | Input muxed clock |
| 179 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 180 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 181 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 182 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 183 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 187 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 188 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 189 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 190 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 191 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 195 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 196 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 197 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 199 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 200 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 201 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 203 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 204 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 205 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 206 | DEV_AASRC1_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_TX1_SYNC_CLK |
| 211 | DEV_AASRC1_TX2_SYNC_CLK | Input muxed clock |
| 212 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 213 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 214 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 215 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 216 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 220 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 221 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 222 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 223 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 224 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 228 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 229 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 230 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 232 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 233 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 234 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 236 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 237 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 238 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 239 | DEV_AASRC1_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_TX2_SYNC_CLK |
| 244 | DEV_AASRC1_TX3_SYNC_CLK | Input muxed clock |
| 245 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 246 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 247 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 248 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 249 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 253 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 254 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 255 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 256 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 257 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 261 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 262 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 263 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 265 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 266 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 267 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 269 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 270 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 271 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 272 | DEV_AASRC1_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_AASRC1_TX3_SYNC_CLK |
| 281 | DEV_AASRC1_VBUSP_CLK | Input clock |
Clocks for ADC0 Device¶
Device: AM275X_DEV_ADC0 (ID = 0)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ADC0_ADC_CLK | Input muxed clock |
| 1 | DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_ADC0_ADC_CLK |
| 2 | DEV_ADC0_ADC_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_ADC0_ADC_CLK |
| 3 | DEV_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT4_CLK | Parent input clock option to DEV_ADC0_ADC_CLK |
| 4 | DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_ADC0_ADC_CLK |
| 5 | DEV_ADC0_SYS_CLK | Input clock |
| 6 | DEV_ADC0_VBUS_CLK | Input clock |
Clocks for ATL0 Device¶
Device: AM275X_DEV_ATL0 (ID = 246)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ATL0_ATL_CLK | Input muxed clock |
| 1 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 2 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 4 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 5 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 6 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_CLK |
| 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_CLK |
| 9 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | Output clock |
| 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | Output clock |
| 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | Output clock |
| 12 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | Output clock |
| 13 | DEV_ATL0_ATL_IO_PORT_AWS | Input muxed clock |
| 14 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 15 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 16 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 17 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 18 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 19 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 20 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 21 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 22 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 23 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 24 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 25 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 26 | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS |
| 30 | DEV_ATL0_ATL_IO_PORT_AWS_1 | Input muxed clock |
| 31 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 32 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 33 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 34 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 35 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 36 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 37 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 38 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 39 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 40 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 41 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 42 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 43 | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1 |
| 53 | DEV_ATL0_ATL_IO_PORT_AWS_2 | Input muxed clock |
| 54 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 55 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 56 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 57 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 58 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 59 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 60 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 61 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 62 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 63 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 64 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 65 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 66 | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2 |
| 70 | DEV_ATL0_ATL_IO_PORT_AWS_3 | Input muxed clock |
| 71 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 72 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 73 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 74 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 75 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 76 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 77 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 78 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 79 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 80 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 81 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 82 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 83 | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3 |
| 93 | DEV_ATL0_ATL_IO_PORT_BWS | Input muxed clock |
| 94 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 95 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 96 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 97 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 98 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 99 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 100 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 101 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 102 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 103 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 104 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 105 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 106 | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS |
| 110 | DEV_ATL0_ATL_IO_PORT_BWS_1 | Input muxed clock |
| 111 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 112 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 113 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 114 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 115 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 116 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 117 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 118 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 119 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 120 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 121 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 122 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 123 | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1 |
| 133 | DEV_ATL0_ATL_IO_PORT_BWS_2 | Input muxed clock |
| 134 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 135 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 136 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 137 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 138 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 139 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 140 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 141 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 142 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 143 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 144 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 145 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 146 | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2 |
| 150 | DEV_ATL0_ATL_IO_PORT_BWS_3 | Input muxed clock |
| 151 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 152 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 153 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 154 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 155 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 156 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 157 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 158 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 159 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 160 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 161 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 162 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 163 | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3 |
| 173 | DEV_ATL0_VBUS_CLK | Input clock |
Clocks for BOARD0 Device¶
Device: AM275X_DEV_BOARD0 (ID = 157)
Note
BOARD0 is a special device that represents the board on which the SoC is mounted.
Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.
Function documented here implies:
| Function | Description |
|---|---|
| Input clock | Clock is supplied from SoC to the board (It is an output of the SoC) |
| Output clock | Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC) |
NOTE: Clocks which can be bi-directional are listed as Output clock
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | Input muxed clock |
| 1 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 2 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 3 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 4 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 5 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 6 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 7 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 8 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 9 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 10 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 11 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 12 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 13 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 14 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 15 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 16 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 17 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | Output clock |
| 18 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | Input muxed clock |
| 19 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 20 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 21 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 22 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 23 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 24 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 25 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 26 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 27 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 28 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 29 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 30 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 31 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 32 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 33 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 34 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 35 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | Output clock |
| 36 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN | Input muxed clock |
| 37 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 38 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 39 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 40 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 41 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 42 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 43 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 44 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 45 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 46 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 47 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 48 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 49 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 50 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 51 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 52 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 53 | DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT | Output clock |
| 54 | DEV_BOARD0_CLKOUT0_IN | Input muxed clock |
| 55 | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5 | Parent input clock option to DEV_BOARD0_CLKOUT0_IN |
| 56 | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 | Parent input clock option to DEV_BOARD0_CLKOUT0_IN |
| 57 | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Output clock |
| 58 | DEV_BOARD0_EXT_REFCLK1_OUT | Output clock |
| 59 | DEV_BOARD0_HYPERBUS0_CK_IN | Input clock |
| 60 | DEV_BOARD0_HYPERBUS0_CKN_IN | Input clock |
| 61 | DEV_BOARD0_I2C0_SCL_IN | Input clock |
| 62 | DEV_BOARD0_I2C0_SCL_OUT | Output clock |
| 63 | DEV_BOARD0_I2C1_SCL_IN | Input clock |
| 64 | DEV_BOARD0_I2C1_SCL_OUT | Output clock |
| 65 | DEV_BOARD0_I2C2_SCL_IN | Input clock |
| 66 | DEV_BOARD0_I2C2_SCL_OUT | Output clock |
| 67 | DEV_BOARD0_I2C3_SCL_IN | Input clock |
| 68 | DEV_BOARD0_I2C3_SCL_OUT | Output clock |
| 69 | DEV_BOARD0_I2C4_SCL_IN | Input clock |
| 70 | DEV_BOARD0_I2C4_SCL_OUT | Output clock |
| 71 | DEV_BOARD0_I2C5_SCL_IN | Input clock |
| 72 | DEV_BOARD0_I2C5_SCL_OUT | Output clock |
| 73 | DEV_BOARD0_I2C6_SCL_IN | Input clock |
| 74 | DEV_BOARD0_I2C6_SCL_OUT | Output clock |
| 76 | DEV_BOARD0_MCASP0_ACLKR_IN | Input clock |
| 77 | DEV_BOARD0_MCASP0_ACLKR_OUT | Output clock |
| 78 | DEV_BOARD0_MCASP0_ACLKX_IN | Input clock |
| 79 | DEV_BOARD0_MCASP0_ACLKX_OUT | Output clock |
| 80 | DEV_BOARD0_MCASP0_AFSR_IN | Input clock |
| 81 | DEV_BOARD0_MCASP0_AFSR_OUT | Output clock |
| 82 | DEV_BOARD0_MCASP0_AFSX_IN | Input clock |
| 83 | DEV_BOARD0_MCASP0_AFSX_OUT | Output clock |
| 84 | DEV_BOARD0_MCASP1_ACLKR_IN | Input clock |
| 85 | DEV_BOARD0_MCASP1_ACLKR_OUT | Output clock |
| 86 | DEV_BOARD0_MCASP1_ACLKX_IN | Input clock |
| 87 | DEV_BOARD0_MCASP1_ACLKX_OUT | Output clock |
| 88 | DEV_BOARD0_MCASP1_AFSR_IN | Input clock |
| 89 | DEV_BOARD0_MCASP1_AFSR_OUT | Output clock |
| 90 | DEV_BOARD0_MCASP1_AFSX_IN | Input clock |
| 91 | DEV_BOARD0_MCASP1_AFSX_OUT | Output clock |
| 92 | DEV_BOARD0_MCASP2_ACLKR_IN | Input clock |
| 93 | DEV_BOARD0_MCASP2_ACLKR_OUT | Output clock |
| 94 | DEV_BOARD0_MCASP2_ACLKX_IN | Input clock |
| 95 | DEV_BOARD0_MCASP2_ACLKX_OUT | Output clock |
| 96 | DEV_BOARD0_MCASP2_AFSR_IN | Input clock |
| 97 | DEV_BOARD0_MCASP2_AFSR_OUT | Output clock |
| 98 | DEV_BOARD0_MCASP2_AFSX_IN | Input clock |
| 99 | DEV_BOARD0_MCASP2_AFSX_OUT | Output clock |
| 100 | DEV_BOARD0_MCASP3_ACLKR_IN | Input clock |
| 101 | DEV_BOARD0_MCASP3_ACLKR_OUT | Output clock |
| 102 | DEV_BOARD0_MCASP3_ACLKX_IN | Input clock |
| 103 | DEV_BOARD0_MCASP3_ACLKX_OUT | Output clock |
| 104 | DEV_BOARD0_MCASP3_AFSR_IN | Input clock |
| 105 | DEV_BOARD0_MCASP3_AFSR_OUT | Output clock |
| 106 | DEV_BOARD0_MCASP3_AFSX_IN | Input clock |
| 107 | DEV_BOARD0_MCASP3_AFSX_OUT | Output clock |
| 108 | DEV_BOARD0_MCASP4_ACLKR_IN | Input clock |
| 109 | DEV_BOARD0_MCASP4_ACLKR_OUT | Output clock |
| 110 | DEV_BOARD0_MCASP4_ACLKX_IN | Input clock |
| 111 | DEV_BOARD0_MCASP4_ACLKX_OUT | Output clock |
| 112 | DEV_BOARD0_MCASP4_AFSR_IN | Input clock |
| 113 | DEV_BOARD0_MCASP4_AFSR_OUT | Output clock |
| 114 | DEV_BOARD0_MCASP4_AFSX_IN | Input clock |
| 115 | DEV_BOARD0_MCASP4_AFSX_OUT | Output clock |
| 116 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | Output clock |
| 117 | DEV_BOARD0_MCU_OBSCLK0_IN | Input muxed clock |
| 118 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN |
| 119 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN |
| 120 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | Input clock |
| 121 | DEV_BOARD0_MDIO0_MDC_IN | Input clock |
| 122 | DEV_BOARD0_MLB0_MLBCLK_OUT | Output clock |
| 123 | DEV_BOARD0_MMC0_CLKLB_IN | Input clock |
| 124 | DEV_BOARD0_MMC0_CLKLB_OUT | Output clock |
| 125 | DEV_BOARD0_MMC0_CLK_IN | Input clock |
| 126 | DEV_BOARD0_MMC0_CLK_OUT | Output clock |
| 127 | DEV_BOARD0_OBSCLK0_IN | Input muxed clock |
| 128 | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 129 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 130 | DEV_BOARD0_OBSCLK1_IN | Input muxed clock |
| 131 | DEV_BOARD0_OBSCLK1_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 | Parent input clock option to DEV_BOARD0_OBSCLK1_IN |
| 132 | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK1_IN |
| 133 | DEV_BOARD0_OSPI0_CLK_IN | Input clock |
| 134 | DEV_BOARD0_OSPI0_DQS_OUT | Output clock |
| 135 | DEV_BOARD0_OSPI0_LBCLKO_IN | Input clock |
| 136 | DEV_BOARD0_OSPI0_LBCLKO_OUT | Output clock |
| 137 | DEV_BOARD0_OSPI1_CLK_IN | Input clock |
| 138 | DEV_BOARD0_OSPI1_DQS_OUT | Output clock |
| 139 | DEV_BOARD0_OSPI1_LBCLKO_IN | Input clock |
| 140 | DEV_BOARD0_OSPI1_LBCLKO_OUT | Output clock |
| 141 | DEV_BOARD0_RGMII1_RXC_OUT | Output clock |
| 143 | DEV_BOARD0_RGMII2_RXC_OUT | Output clock |
| 145 | DEV_BOARD0_RMII1_REF_CLK_OUT | Output clock |
| 146 | DEV_BOARD0_RMII2_REF_CLK_OUT | Output clock |
| 147 | DEV_BOARD0_SPI0_CLK_IN | Input clock |
| 148 | DEV_BOARD0_SPI0_CLK_OUT | Output clock |
| 149 | DEV_BOARD0_SPI1_CLK_IN | Input clock |
| 150 | DEV_BOARD0_SPI1_CLK_OUT | Output clock |
| 151 | DEV_BOARD0_SPI2_CLK_IN | Input clock |
| 152 | DEV_BOARD0_SPI2_CLK_OUT | Output clock |
| 153 | DEV_BOARD0_SPI3_CLK_IN | Input clock |
| 154 | DEV_BOARD0_SPI3_CLK_OUT | Output clock |
| 155 | DEV_BOARD0_SPI4_CLK_IN | Input clock |
| 156 | DEV_BOARD0_SPI4_CLK_OUT | Output clock |
| 157 | DEV_BOARD0_SYSCLKOUT0_IN | Input clock |
| 158 | DEV_BOARD0_TCK_OUT | Output clock |
| 159 | DEV_BOARD0_TIMER_IO0_IN | Input clock |
| 160 | DEV_BOARD0_TIMER_IO1_IN | Input clock |
| 161 | DEV_BOARD0_TIMER_IO2_IN | Input clock |
| 162 | DEV_BOARD0_TIMER_IO3_IN | Input clock |
| 163 | DEV_BOARD0_TIMER_IO4_IN | Input clock |
| 164 | DEV_BOARD0_TIMER_IO5_IN | Input clock |
| 165 | DEV_BOARD0_TIMER_IO6_IN | Input clock |
| 166 | DEV_BOARD0_TIMER_IO7_IN | Input clock |
| 167 | DEV_BOARD0_TRC_CLK_IN | Input clock |
| 168 | DEV_BOARD0_WKUP_CLKOUT0_IN | Input muxed clock |
| 169 | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0 | Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN |
| 170 | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_BOARD0_WKUP_CLKOUT0_IN |
| 171 | DEV_BOARD0_WKUP_I2C0_SCL_IN | Input clock |
| 172 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | Output clock |
| 173 | DEV_BOARD0_HFOSC1_CLK_OUT | Output clock |
Clocks for C7X256V0 Device¶
This device has no defined clocks.
Clocks for C7X256V0_C7XV_CORE_0 Device¶
Device: AM275X_DEV_C7X256V0_C7XV_CORE_0 (ID = 208)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK | Input clock |
Clocks for C7X256V0_CLEC Device¶
This device has no defined clocks.
Clocks for C7X256V0_CLK Device¶
Device: AM275X_DEV_C7X256V0_CLK (ID = 211)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C7X256V0_CLK_C7XV_CLK | Input clock |
| 1 | DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK | Output clock |
| 2 | DEV_C7X256V0_CLK_DIVH_CLK2_PULSAR_GCLK | Output clock |
| 3 | DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK | Output clock |
| 4 | DEV_C7X256V0_CLK_DIVH_CLK4_GCLK | Output clock |
| 5 | DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK | Output clock |
| 6 | DEV_C7X256V0_CLK_DIVP_CLK1_GCLK | Output clock |
| 7 | DEV_C7X256V0_CLK_PLL_CTRL_CLK | Input clock |
| 8 | DEV_C7X256V0_CLK_PULSAR_PLL_CLK_CLK | Input clock |
Clocks for C7X256V0_CORE0 Device¶
Device: AM275X_DEV_C7X256V0_CORE0 (ID = 209)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C7X256V0_CORE0_DIVH_CLK2_PULSAR_GCLK | Input clock |
| 1 | DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK | Input clock |
| 2 | DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK | Input clock |
| 3 | DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK | Input clock |
| 4 | DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK | Input clock |
| 6 | DEV_C7X256V0_CORE0_PULSAR_PLL_CLK_CLK | Input clock |
Clocks for C7X256V0_DEBUG Device¶
This device has no defined clocks.
Clocks for C7X256V0_GICSS Device¶
This device has no defined clocks.
Clocks for C7X256V0_PBIST Device¶
This device has no defined clocks.
Clocks for C7X256V1 Device¶
This device has no defined clocks.
Clocks for C7X256V1_C7XV_CORE_0 Device¶
Device: AM275X_DEV_C7X256V1_C7XV_CORE_0 (ID = 268)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C7X256V1_C7XV_CORE_0_C7XV_CLK | Input clock |
Clocks for C7X256V1_CLEC Device¶
This device has no defined clocks.
Clocks for C7X256V1_CLK Device¶
Device: AM275X_DEV_C7X256V1_CLK (ID = 271)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C7X256V1_CLK_C7XV_CLK | Input clock |
| 1 | DEV_C7X256V1_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK | Output clock |
| 2 | DEV_C7X256V1_CLK_DIVH_CLK2_PULSAR_GCLK | Output clock |
| 3 | DEV_C7X256V1_CLK_DIVH_CLK2_SOC_GCLK | Output clock |
| 4 | DEV_C7X256V1_CLK_DIVH_CLK4_GCLK | Output clock |
| 5 | DEV_C7X256V1_CLK_DIVH_CLK4_SOC_GCLK | Output clock |
| 6 | DEV_C7X256V1_CLK_DIVP_CLK1_GCLK | Output clock |
| 7 | DEV_C7X256V1_CLK_PLL_CTRL_CLK | Input clock |
| 8 | DEV_C7X256V1_CLK_PULSAR_PLL_CLK_CLK | Input clock |
Clocks for C7X256V1_CORE0 Device¶
Device: AM275X_DEV_C7X256V1_CORE0 (ID = 269)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C7X256V1_CORE0_DIVH_CLK2_PULSAR_GCLK | Input clock |
| 1 | DEV_C7X256V1_CORE0_DIVH_CLK2_SOC_GCLK | Input clock |
| 2 | DEV_C7X256V1_CORE0_DIVH_CLK4_GCLK | Input clock |
| 3 | DEV_C7X256V1_CORE0_DIVH_CLK4_SOC_GCLK | Input clock |
| 4 | DEV_C7X256V1_CORE0_DIVP_CLK1_GCLK | Input clock |
| 6 | DEV_C7X256V1_CORE0_PULSAR_PLL_CLK_CLK | Input clock |
Clocks for C7X256V1_DEBUG Device¶
This device has no defined clocks.
Clocks for C7X256V1_GICSS Device¶
This device has no defined clocks.
Clocks for C7X256V1_PBIST Device¶
This device has no defined clocks.
Clocks for CLK_32K_RC_SEL_DEV_VD Device¶
Device: AM275X_DEV_CLK_32K_RC_SEL_DEV_VD (ID = 193)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CLK_32K_RC_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK |
| 2 | DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK8 | Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK |
| 3 | DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0 | Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK |
| 4 | DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT | Parent input clock option to DEV_CLK_32K_RC_SEL_DEV_VD_CLK |
Clocks for CPSW0 Device¶
Device: AM275X_DEV_CPSW0 (ID = 13)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPSW0_CPPI_CLK_CLK | Input clock |
| 1 | DEV_CPSW0_CPTS_GENF0 | Output clock |
| 2 | DEV_CPSW0_CPTS_GENF1 | Output clock |
| 3 | DEV_CPSW0_CPTS_RFT_CLK | Input muxed clock |
| 4 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 5 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 6 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 8 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 9 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 10 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 11 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 12 | DEV_CPSW0_GMII1_MR_CLK | Input clock |
| 13 | DEV_CPSW0_GMII1_MT_CLK | Input clock |
| 14 | DEV_CPSW0_GMII2_MR_CLK | Input clock |
| 15 | DEV_CPSW0_GMII2_MT_CLK | Input clock |
| 16 | DEV_CPSW0_GMII_RFT_CLK | Input clock |
| 17 | DEV_CPSW0_MDIO_MDCLK_O | Output clock |
| 18 | DEV_CPSW0_RGMII_MHZ_250_CLK | Input clock |
| 19 | DEV_CPSW0_RGMII_MHZ_50_CLK | Input clock |
| 20 | DEV_CPSW0_RGMII_MHZ_5_CLK | Input clock |
| 21 | DEV_CPSW0_RMII1_MHZ_50_CLK | Input clock |
| 22 | DEV_CPSW0_RMII2_MHZ_50_CLK | Input clock |
Clocks for CPT2_AGGR0 Device¶
Device: AM275X_DEV_CPT2_AGGR0 (ID = 195)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPT2_AGGR0_VCLK_CLK | Input clock |
Clocks for CPT2_AGGR1 Device¶
Device: AM275X_DEV_CPT2_AGGR1 (ID = 194)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPT2_AGGR1_VCLK_CLK | Input clock |
Clocks for CPT2_AGGR2 Device¶
Device: AM275X_DEV_CPT2_AGGR2 (ID = 196)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPT2_AGGR2_VCLK_CLK | Input clock |
Clocks for DBG_INTROUTER0 Device¶
Device: AM275X_DEV_DBG_INTROUTER0 (ID = 2)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DBG_INTROUTER0_INTR_CLK | Input clock |
Clocks for DCC0 Device¶
Device: AM275X_DEV_DCC0 (ID = 16)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC0_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC0_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC0_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC0_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC0_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC0_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC0_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC0_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC0_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC0_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC0_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC0_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC0_VBUS_CLK | Input clock |
Clocks for DCC1 Device¶
Device: AM275X_DEV_DCC1 (ID = 17)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC1_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC1_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC1_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC1_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC1_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC1_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC1_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC1_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC1_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC1_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC1_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC1_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC1_VBUS_CLK | Input clock |
Clocks for DCC2 Device¶
Device: AM275X_DEV_DCC2 (ID = 18)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC2_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC2_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC2_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC2_DCC_CLKSRC3_CLK | Input clock |
| 5 | DEV_DCC2_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC2_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC2_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC2_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC2_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC2_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC2_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC2_VBUS_CLK | Input clock |
Clocks for DCC3 Device¶
Device: AM275X_DEV_DCC3 (ID = 19)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC3_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC3_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC3_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC3_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC3_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC3_DCC_CLKSRC5_CLK | Input clock |
| 8 | DEV_DCC3_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC3_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC3_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC3_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC3_VBUS_CLK | Input clock |
Clocks for DCC4 Device¶
Device: AM275X_DEV_DCC4 (ID = 20)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_DCC4_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC4_DCC_CLKSRC2_CLK | Input clock |
| 4 | DEV_DCC4_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC4_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC4_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC4_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC4_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC4_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC4_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC4_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC4_VBUS_CLK | Input clock |
Clocks for DCC5 Device¶
Device: AM275X_DEV_DCC5 (ID = 21)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC5_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC5_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC5_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC5_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC5_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC5_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC5_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC5_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC5_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC5_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC5_VBUS_CLK | Input clock |
Clocks for DCC6 Device¶
Device: AM275X_DEV_DCC6 (ID = 183)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_DCC6_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC6_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC6_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC6_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC6_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC6_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC6_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC6_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC6_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC6_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC6_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC6_VBUS_CLK | Input clock |
Clocks for DCC7 Device¶
Device: AM275X_DEV_DCC7 (ID = 229)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC7_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC7_DCC_CLKSRC1_CLK | Input clock |
| 3 | DEV_DCC7_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC7_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC7_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC7_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC7_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC7_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC7_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC7_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC7_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC7_VBUS_CLK | Input clock |
Clocks for DCC8 Device¶
Device: AM275X_DEV_DCC8 (ID = 230)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC8_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_DCC8_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_DCC8_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC8_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_DCC8_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_DCC8_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_DCC8_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_DCC8_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_DCC8_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_DCC8_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_DCC8_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_DCC8_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_DCC8_VBUS_CLK | Input clock |
Clocks for DDPA0 Device¶
Device: AM275X_DEV_DDPA0 (ID = 85)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DDPA0_DDPA_CLK | Input clock |
Clocks for DEBUGSS0 Device¶
Device: AM275X_DEV_DEBUGSS0 (ID = 171)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DEBUGSS0_CFG_CLK | Input clock |
| 1 | DEV_DEBUGSS0_DBG_CLK | Input clock |
| 2 | DEV_DEBUGSS0_SYS_CLK | Input clock |
Clocks for DEBUGSS_WRAP0 Device¶
Device: AM275X_DEV_DEBUGSS_WRAP0 (ID = 24)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DEBUGSS_WRAP0_ATB_CLK | Input clock |
| 1 | DEV_DEBUGSS_WRAP0_CORE_CLK | Input clock |
| 2 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | Output clock |
| 20 | DEV_DEBUGSS_WRAP0_JTAG_TCK | Input clock |
| 21 | DEV_DEBUGSS_WRAP0_P1500_WRCK | Input clock |
| 22 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | Input clock |
Clocks for DMASS0 Device¶
This device has no defined clocks.
Clocks for DMASS0_BCDMA_0 Device¶
Device: AM275X_DEV_DMASS0_BCDMA_0 (ID = 26)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMASS0_BCDMA_0_CLK | Input clock |
Clocks for DMASS0_CBASS_0 Device¶
Device: AM275X_DEV_DMASS0_CBASS_0 (ID = 27)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMASS0_CBASS_0_CLK | Input clock |
Clocks for DMASS0_INTAGGR_0 Device¶
Device: AM275X_DEV_DMASS0_INTAGGR_0 (ID = 28)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMASS0_INTAGGR_0_CLK | Input clock |
Clocks for DMASS0_IPCSS_0 Device¶
Device: AM275X_DEV_DMASS0_IPCSS_0 (ID = 29)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMASS0_IPCSS_0_CLK | Input clock |
Clocks for DMASS0_PKTDMA_0 Device¶
Device: AM275X_DEV_DMASS0_PKTDMA_0 (ID = 30)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMASS0_PKTDMA_0_CLK | Input clock |
Clocks for DMASS0_RINGACC_0 Device¶
Device: AM275X_DEV_DMASS0_RINGACC_0 (ID = 33)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMASS0_RINGACC_0_CLK | Input clock |
Clocks for ECAP0 Device¶
Device: AM275X_DEV_ECAP0 (ID = 51)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP0_VBUS_CLK | Input clock |
Clocks for ECAP1 Device¶
Device: AM275X_DEV_ECAP1 (ID = 52)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP1_VBUS_CLK | Input clock |
Clocks for ECAP2 Device¶
Device: AM275X_DEV_ECAP2 (ID = 53)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP2_VBUS_CLK | Input clock |
Clocks for ECAP3 Device¶
Device: AM275X_DEV_ECAP3 (ID = 292)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP3_VBUS_CLK | Input clock |
Clocks for ECAP4 Device¶
Device: AM275X_DEV_ECAP4 (ID = 293)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP4_VBUS_CLK | Input clock |
Clocks for ECAP5 Device¶
Device: AM275X_DEV_ECAP5 (ID = 294)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP5_VBUS_CLK | Input clock |
Clocks for EPWM0 Device¶
Device: AM275X_DEV_EPWM0 (ID = 86)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EPWM0_VBUSP_CLK | Input clock |
Clocks for EPWM1 Device¶
Device: AM275X_DEV_EPWM1 (ID = 87)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EPWM1_VBUSP_CLK | Input clock |
Clocks for EPWM2 Device¶
Device: AM275X_DEV_EPWM2 (ID = 88)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EPWM2_VBUSP_CLK | Input clock |
Clocks for ESM0 Device¶
Device: AM275X_DEV_ESM0 (ID = 63)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ESM0_CLK | Input clock |
Clocks for FSS0 Device¶
Device: AM275X_DEV_FSS0 (ID = 298)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_FSS0_M8051EW_JTAG_TCK | Input clock |
| 1 | DEV_FSS0_OSPI0_DQS_CLK | Input clock |
| 2 | DEV_FSS0_OSPI0_ICLK_CLK | Input muxed clock |
| 3 | DEV_FSS0_OSPI0_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT | Parent input clock option to DEV_FSS0_OSPI0_ICLK_CLK |
| 4 | DEV_FSS0_OSPI0_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT | Parent input clock option to DEV_FSS0_OSPI0_ICLK_CLK |
| 5 | DEV_FSS0_OSPI0_OCLK_CLK | Output clock |
| 6 | DEV_FSS0_OSPI0_RCLK_CLK | Input muxed clock |
| 7 | DEV_FSS0_OSPI0_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_FSS0_OSPI0_RCLK_CLK |
| 8 | DEV_FSS0_OSPI0_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK | Parent input clock option to DEV_FSS0_OSPI0_RCLK_CLK |
| 9 | DEV_FSS0_VBUS_CLK | Input clock |
Clocks for FSS1 Device¶
This device has no defined clocks.
Clocks for FSS1_FSAS_0 Device¶
Device: AM275X_DEV_FSS1_FSAS_0 (ID = 74)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_FSS1_FSAS_0_GCLK | Input clock |
Clocks for FSS1_HYPERBUS1P0_0 Device¶
Device: AM275X_DEV_FSS1_HYPERBUS1P0_0 (ID = 295)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_FSS1_HYPERBUS1P0_0_CBA_CLK | Input clock |
| 2 | DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX1_CLK | Input clock |
| 4 | DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | Input clock |
| 6 | DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX2_CLK | Input clock |
| 8 | DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | Input clock |
| 10 | DEV_FSS1_HYPERBUS1P0_0_HPB_OUT_CLK_N | Output clock |
| 11 | DEV_FSS1_HYPERBUS1P0_0_HPB_OUT_CLK_P | Output clock |
Clocks for FSS1_MISC_0 Device¶
This device has no defined clocks.
Clocks for FSS1_OSPI_0 Device¶
Device: AM275X_DEV_FSS1_OSPI_0 (ID = 75)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_FSS1_OSPI_0_OSPI_DQS_CLK | Input clock |
| 1 | DEV_FSS1_OSPI_0_OSPI_HCLK_CLK | Input clock |
| 2 | DEV_FSS1_OSPI_0_OSPI_ICLK_CLK | Input muxed clock |
| 3 | DEV_FSS1_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI1_DQS_OUT | Parent input clock option to DEV_FSS1_OSPI_0_OSPI_ICLK_CLK |
| 4 | DEV_FSS1_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI1_LBCLKO_OUT | Parent input clock option to DEV_FSS1_OSPI_0_OSPI_ICLK_CLK |
| 5 | DEV_FSS1_OSPI_0_OSPI_OCLK_CLK | Output clock |
| 6 | DEV_FSS1_OSPI_0_OSPI_PCLK_CLK | Input clock |
| 7 | DEV_FSS1_OSPI_0_OSPI_RCLK_CLK | Input muxed clock |
| 8 | DEV_FSS1_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_FSS1_OSPI_0_OSPI_RCLK_CLK |
| 9 | DEV_FSS1_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK | Parent input clock option to DEV_FSS1_OSPI_0_OSPI_RCLK_CLK |
Clocks for FSS1_OSPI_1 Device¶
Device: AM275X_DEV_FSS1_OSPI_1 (ID = 297)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_FSS1_OSPI_1_OSPI_HCLK_CLK | Input clock |
| 6 | DEV_FSS1_OSPI_1_OSPI_PCLK_CLK | Input clock |
Clocks for GPIO0 Device¶
Device: AM275X_DEV_GPIO0 (ID = 77)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO0_MMR_CLK | Input clock |
Clocks for GPIO1 Device¶
Device: AM275X_DEV_GPIO1 (ID = 78)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO1_MMR_CLK | Input clock |
Clocks for I2C0 Device¶
Device: AM275X_DEV_I2C0 (ID = 102)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C0_CLK | Input clock |
| 1 | DEV_I2C0_PISCL | Input clock |
| 2 | DEV_I2C0_PISYS_CLK | Input clock |
| 3 | DEV_I2C0_PORSCL | Output clock |
Clocks for I2C1 Device¶
Device: AM275X_DEV_I2C1 (ID = 103)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C1_CLK | Input clock |
| 1 | DEV_I2C1_PISCL | Input clock |
| 2 | DEV_I2C1_PISYS_CLK | Input clock |
| 3 | DEV_I2C1_PORSCL | Output clock |
Clocks for I2C2 Device¶
Device: AM275X_DEV_I2C2 (ID = 104)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C2_CLK | Input clock |
| 1 | DEV_I2C2_PISCL | Input clock |
| 2 | DEV_I2C2_PISYS_CLK | Input clock |
| 3 | DEV_I2C2_PORSCL | Output clock |
Clocks for I2C3 Device¶
Device: AM275X_DEV_I2C3 (ID = 105)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C3_CLK | Input clock |
| 1 | DEV_I2C3_PISCL | Input clock |
| 2 | DEV_I2C3_PISYS_CLK | Input clock |
| 3 | DEV_I2C3_PORSCL | Output clock |
Clocks for I2C4 Device¶
Device: AM275X_DEV_I2C4 (ID = 257)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C4_CLK | Input clock |
| 1 | DEV_I2C4_PISCL | Input clock |
| 2 | DEV_I2C4_PISYS_CLK | Input clock |
| 3 | DEV_I2C4_PORSCL | Output clock |
Clocks for I2C5 Device¶
Device: AM275X_DEV_I2C5 (ID = 314)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C5_CLK | Input clock |
| 1 | DEV_I2C5_PISCL | Input clock |
| 2 | DEV_I2C5_PISYS_CLK | Input clock |
| 3 | DEV_I2C5_PORSCL | Output clock |
Clocks for I2C6 Device¶
Device: AM275X_DEV_I2C6 (ID = 315)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C6_CLK | Input clock |
| 1 | DEV_I2C6_PISCL | Input clock |
| 2 | DEV_I2C6_PISYS_CLK | Input clock |
| 3 | DEV_I2C6_PORSCL | Output clock |
Clocks for LED0 Device¶
Device: AM275X_DEV_LED0 (ID = 83)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_LED0_VBUS_CLK | Input clock |
Clocks for MAILBOX0 Device¶
This device has no defined clocks.
Clocks for MAIN_GPIOMUX_INTROUTER0 Device¶
Device: AM275X_DEV_MAIN_GPIOMUX_INTROUTER0 (ID = 3)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK | Input clock |
Clocks for MAIN_USB0_ISO_VD Device¶
This device has no defined clocks.
Clocks for MCAN0 Device¶
Device: AM275X_DEV_MCAN0 (ID = 98)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_MCAN0_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 6 | DEV_MCAN0_MCANSS_HCLK_CLK | Input clock |
Clocks for MCAN1 Device¶
Device: AM275X_DEV_MCAN1 (ID = 99)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_MCAN1_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 6 | DEV_MCAN1_MCANSS_HCLK_CLK | Input clock |
Clocks for MCAN2 Device¶
Device: AM275X_DEV_MCAN2 (ID = 310)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_MCAN2_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 6 | DEV_MCAN2_MCANSS_HCLK_CLK | Input clock |
Clocks for MCAN3 Device¶
Device: AM275X_DEV_MCAN3 (ID = 311)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_MCAN3_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 6 | DEV_MCAN3_MCANSS_HCLK_CLK | Input clock |
Clocks for MCAN4 Device¶
Device: AM275X_DEV_MCAN4 (ID = 312)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_MCAN4_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 6 | DEV_MCAN4_MCANSS_HCLK_CLK | Input clock |
Clocks for MCASP0 Device¶
Device: AM275X_DEV_MCASP0 (ID = 190)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP0_AUX_CLK | Input muxed clock |
| 1 | DEV_MCASP0_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT0 | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 2 | DEV_MCASP0_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT0 | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 3 | DEV_MCASP0_MCASP_ACLKR_PIN | Input clock |
| 4 | DEV_MCASP0_MCASP_ACLKR_POUT | Output clock |
| 5 | DEV_MCASP0_MCASP_ACLKX_PIN | Input clock |
| 6 | DEV_MCASP0_MCASP_ACLKX_POUT | Output clock |
| 7 | DEV_MCASP0_MCASP_AFSR_PIN | Input clock |
| 8 | DEV_MCASP0_MCASP_AFSR_POUT | Output clock |
| 9 | DEV_MCASP0_MCASP_AFSX_PIN | Input clock |
| 10 | DEV_MCASP0_MCASP_AFSX_POUT | Output clock |
| 11 | DEV_MCASP0_MCASP_AHCLKR_PIN | Input muxed clock |
| 12 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 13 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 14 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 15 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 16 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 18 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 20 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 21 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 22 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 23 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 24 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 25 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 28 | DEV_MCASP0_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP0_MCASP_AHCLKX_PIN | Input muxed clock |
| 30 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 31 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 32 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 33 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 34 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 36 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 38 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 39 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 40 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 41 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 42 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 43 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 46 | DEV_MCASP0_MCASP_AHCLKX_POUT | Output clock |
| 47 | DEV_MCASP0_VBUSP_CLK | Input clock |
Clocks for MCASP0_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP0_AUXCLK_SEL_DEV_VD (ID = 330)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
| 4 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
| 5 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
| 6 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
| 7 | DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP0_LOCAL_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD (ID = 335)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 | Parent input clock option to DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 | Parent input clock option to DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP1 Device¶
Device: AM275X_DEV_MCASP1 (ID = 191)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP1_AUX_CLK | Input muxed clock |
| 1 | DEV_MCASP1_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT1 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 2 | DEV_MCASP1_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT1 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 3 | DEV_MCASP1_MCASP_ACLKR_PIN | Input clock |
| 4 | DEV_MCASP1_MCASP_ACLKR_POUT | Output clock |
| 5 | DEV_MCASP1_MCASP_ACLKX_PIN | Input clock |
| 6 | DEV_MCASP1_MCASP_ACLKX_POUT | Output clock |
| 7 | DEV_MCASP1_MCASP_AFSR_PIN | Input clock |
| 8 | DEV_MCASP1_MCASP_AFSR_POUT | Output clock |
| 9 | DEV_MCASP1_MCASP_AFSX_PIN | Input clock |
| 10 | DEV_MCASP1_MCASP_AFSX_POUT | Output clock |
| 11 | DEV_MCASP1_MCASP_AHCLKR_PIN | Input muxed clock |
| 12 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 13 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 14 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 15 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 16 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 18 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 20 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 21 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 22 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 23 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 24 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 25 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 28 | DEV_MCASP1_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP1_MCASP_AHCLKX_PIN | Input muxed clock |
| 30 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 31 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 32 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 33 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 34 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 36 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 38 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 39 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 40 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 41 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 42 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 43 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 46 | DEV_MCASP1_MCASP_AHCLKX_POUT | Output clock |
| 47 | DEV_MCASP1_VBUSP_CLK | Input clock |
Clocks for MCASP1_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP1_AUXCLK_SEL_DEV_VD (ID = 331)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
| 4 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
| 5 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
| 6 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
| 7 | DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP1_LOCAL_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD (ID = 336)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 | Parent input clock option to DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 | Parent input clock option to DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP2 Device¶
Device: AM275X_DEV_MCASP2 (ID = 192)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP2_AUX_CLK | Input muxed clock |
| 1 | DEV_MCASP2_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT2 | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 2 | DEV_MCASP2_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT2 | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 3 | DEV_MCASP2_MCASP_ACLKR_PIN | Input clock |
| 4 | DEV_MCASP2_MCASP_ACLKR_POUT | Output clock |
| 5 | DEV_MCASP2_MCASP_ACLKX_PIN | Input clock |
| 6 | DEV_MCASP2_MCASP_ACLKX_POUT | Output clock |
| 7 | DEV_MCASP2_MCASP_AFSR_PIN | Input clock |
| 8 | DEV_MCASP2_MCASP_AFSR_POUT | Output clock |
| 9 | DEV_MCASP2_MCASP_AFSX_PIN | Input clock |
| 10 | DEV_MCASP2_MCASP_AFSX_POUT | Output clock |
| 11 | DEV_MCASP2_MCASP_AHCLKR_PIN | Input muxed clock |
| 12 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 13 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 14 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 15 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 16 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 18 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 20 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 21 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 22 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 23 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 24 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 25 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 28 | DEV_MCASP2_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP2_MCASP_AHCLKX_PIN | Input muxed clock |
| 30 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 31 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 32 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 33 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 34 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 36 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 38 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 39 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 40 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 41 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 42 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 43 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 46 | DEV_MCASP2_MCASP_AHCLKX_POUT | Output clock |
| 47 | DEV_MCASP2_VBUSP_CLK | Input clock |
Clocks for MCASP2_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP2_AUXCLK_SEL_DEV_VD (ID = 332)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
| 4 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
| 5 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
| 6 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
| 7 | DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP2_LOCAL_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD (ID = 337)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 | Parent input clock option to DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 | Parent input clock option to DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP3 Device¶
Device: AM275X_DEV_MCASP3 (ID = 255)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP3_AUX_CLK | Input muxed clock |
| 1 | DEV_MCASP3_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT3 | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 2 | DEV_MCASP3_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT3 | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 3 | DEV_MCASP3_MCASP_ACLKR_PIN | Input clock |
| 4 | DEV_MCASP3_MCASP_ACLKR_POUT | Output clock |
| 5 | DEV_MCASP3_MCASP_ACLKX_PIN | Input clock |
| 6 | DEV_MCASP3_MCASP_ACLKX_POUT | Output clock |
| 7 | DEV_MCASP3_MCASP_AFSR_PIN | Input clock |
| 8 | DEV_MCASP3_MCASP_AFSR_POUT | Output clock |
| 9 | DEV_MCASP3_MCASP_AFSX_PIN | Input clock |
| 10 | DEV_MCASP3_MCASP_AFSX_POUT | Output clock |
| 11 | DEV_MCASP3_MCASP_AHCLKR_PIN | Input muxed clock |
| 12 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 13 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 14 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 15 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 16 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 18 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 20 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 21 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 22 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 23 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 24 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 25 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 28 | DEV_MCASP3_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP3_MCASP_AHCLKX_PIN | Input muxed clock |
| 30 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 31 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 32 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 33 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 34 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 36 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 38 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 39 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 40 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 41 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 42 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 43 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 46 | DEV_MCASP3_MCASP_AHCLKX_POUT | Output clock |
| 47 | DEV_MCASP3_VBUSP_CLK | Input clock |
Clocks for MCASP3_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP3_AUXCLK_SEL_DEV_VD (ID = 333)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
| 4 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
| 5 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
| 6 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
| 7 | DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP3_LOCAL_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD (ID = 338)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 | Parent input clock option to DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 | Parent input clock option to DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP4 Device¶
Device: AM275X_DEV_MCASP4 (ID = 256)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP4_AUX_CLK | Input muxed clock |
| 1 | DEV_MCASP4_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT4 | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 2 | DEV_MCASP4_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT4 | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 3 | DEV_MCASP4_MCASP_ACLKR_PIN | Input clock |
| 4 | DEV_MCASP4_MCASP_ACLKR_POUT | Output clock |
| 5 | DEV_MCASP4_MCASP_ACLKX_PIN | Input clock |
| 6 | DEV_MCASP4_MCASP_ACLKX_POUT | Output clock |
| 7 | DEV_MCASP4_MCASP_AFSR_PIN | Input clock |
| 8 | DEV_MCASP4_MCASP_AFSR_POUT | Output clock |
| 9 | DEV_MCASP4_MCASP_AFSX_PIN | Input clock |
| 10 | DEV_MCASP4_MCASP_AFSX_POUT | Output clock |
| 11 | DEV_MCASP4_MCASP_AHCLKR_PIN | Input muxed clock |
| 12 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 13 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 14 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 15 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 16 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 18 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 20 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 21 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 22 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 23 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 24 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 25 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 28 | DEV_MCASP4_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP4_MCASP_AHCLKX_PIN | Input muxed clock |
| 30 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 31 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 32 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 33 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 34 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 36 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 38 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 39 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 40 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 41 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 42 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 43 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 46 | DEV_MCASP4_MCASP_AHCLKX_POUT | Output clock |
| 47 | DEV_MCASP4_VBUSP_CLK | Input clock |
Clocks for MCASP4_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP4_AUXCLK_SEL_DEV_VD (ID = 334)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
| 4 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
| 5 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
| 6 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
| 7 | DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCASP4_LOCAL_AUXCLK_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD (ID = 339)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 | Parent input clock option to DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 2 | DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 | Parent input clock option to DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
| 3 | DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK |
Clocks for MCRC64_0 Device¶
Device: AM275X_DEV_MCRC64_0 (ID = 116)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCRC64_0_CLK | Input clock |
Clocks for MCSPI0 Device¶
Device: AM275X_DEV_MCSPI0 (ID = 141)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI0_CLKSPIREF_CLK | Input clock |
| 1 | DEV_MCSPI0_IO_CLKSPII_CLK | Input muxed clock |
| 2 | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT | Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK |
| 3 | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK |
| 4 | DEV_MCSPI0_IO_CLKSPIO_CLK | Output clock |
| 5 | DEV_MCSPI0_VBUSP_CLK | Input clock |
Clocks for MCSPI1 Device¶
Device: AM275X_DEV_MCSPI1 (ID = 142)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI1_CLKSPIREF_CLK | Input clock |
| 1 | DEV_MCSPI1_IO_CLKSPII_CLK | Input muxed clock |
| 2 | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT | Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK |
| 3 | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK |
| 4 | DEV_MCSPI1_IO_CLKSPIO_CLK | Output clock |
| 5 | DEV_MCSPI1_VBUSP_CLK | Input clock |
Clocks for MCSPI2 Device¶
Device: AM275X_DEV_MCSPI2 (ID = 143)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI2_CLKSPIREF_CLK | Input clock |
| 1 | DEV_MCSPI2_IO_CLKSPII_CLK | Input muxed clock |
| 2 | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT | Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK |
| 3 | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK |
| 4 | DEV_MCSPI2_IO_CLKSPIO_CLK | Output clock |
| 5 | DEV_MCSPI2_VBUSP_CLK | Input clock |
Clocks for MCSPI3 Device¶
Device: AM275X_DEV_MCSPI3 (ID = 144)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI3_CLKSPIREF_CLK | Input clock |
| 1 | DEV_MCSPI3_IO_CLKSPII_CLK | Input muxed clock |
| 2 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT | Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK |
| 3 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK |
| 4 | DEV_MCSPI3_IO_CLKSPIO_CLK | Output clock |
| 5 | DEV_MCSPI3_VBUSP_CLK | Input clock |
Clocks for MCSPI4 Device¶
Device: AM275X_DEV_MCSPI4 (ID = 145)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI4_CLKSPIREF_CLK | Input clock |
| 1 | DEV_MCSPI4_IO_CLKSPII_CLK | Input muxed clock |
| 2 | DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT | Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK |
| 3 | DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK |
| 4 | DEV_MCSPI4_IO_CLKSPIO_CLK | Output clock |
| 5 | DEV_MCSPI4_VBUSP_CLK | Input clock |
Clocks for MCU_DCC0 Device¶
Device: AM275X_DEV_MCU_DCC0 (ID = 23)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | Input clock |
| 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | Input clock |
| 4 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | Input clock |
| 5 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_MCU_DCC0_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_MCU_DCC0_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_MCU_DCC0_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_MCU_DCC0_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_MCU_DCC0_VBUS_CLK | Input clock |
Clocks for MCU_DCC1 Device¶
Device: AM275X_DEV_MCU_DCC1 (ID = 197)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | Input clock |
| 1 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | Input clock |
| 5 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | Input clock |
| 6 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | Input clock |
| 7 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | Input clock |
| 8 | DEV_MCU_DCC1_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_MCU_DCC1_DCC_INPUT01_CLK | Input clock |
| 10 | DEV_MCU_DCC1_DCC_INPUT02_CLK | Input clock |
| 11 | DEV_MCU_DCC1_DCC_INPUT10_CLK | Input clock |
| 12 | DEV_MCU_DCC1_VBUS_CLK | Input clock |
Clocks for MCU_GPIO0 Device¶
Device: AM275X_DEV_MCU_GPIO0 (ID = 79)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_GPIO0_MMR_CLK | Input muxed clock |
| 1 | DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 | Parent input clock option to DEV_MCU_GPIO0_MMR_CLK |
| 3 | DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_MCU_GPIO0_MMR_CLK |
| 4 | DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_MCU_GPIO0_MMR_CLK |
Clocks for MCU_MCU_16FF0 Device¶
Device: AM275X_DEV_MCU_MCU_16FF0 (ID = 180)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 3 | DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK | Input clock |
Clocks for MCU_MCU_GPIOMUX_INTROUTER0 Device¶
Device: AM275X_DEV_MCU_MCU_GPIOMUX_INTROUTER0 (ID = 5)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK | Input clock |
Clocks for MCU_OBSCLK_MUX_SEL_DEV_VD Device¶
Device: AM275X_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD (ID = 227)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 2 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 3 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 4 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0 | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 5 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 6 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 7 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK8 | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 8 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
| 9 | DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK |
Clocks for MLB0 Device¶
Device: AM275X_DEV_MLB0 (ID = 313)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 1 | DEV_MLB0_MLBSS_HCLK_CLK | Input clock |
| 2 | DEV_MLB0_MLBSS_MLB_CLK | Input clock |
| 3 | DEV_MLB0_MLBSS_PCLK_CLK | Input clock |
| 4 | DEV_MLB0_MLBSS_SCLK_CLK | Input clock |
Clocks for MMCSD0 Device¶
Device: AM275X_DEV_MMCSD0 (ID = 58)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MMCSD0_EMMCSDSS_IO_CLK_I | Input muxed clock |
| 1 | DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT | Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I |
| 2 | DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT | Parent input clock option to DEV_MMCSD0_EMMCSDSS_IO_CLK_I |
| 3 | DEV_MMCSD0_EMMCSDSS_IO_CLK_O | Output clock |
| 5 | DEV_MMCSD0_EMMCSDSS_VBUS_CLK | Input clock |
| 6 | DEV_MMCSD0_EMMCSDSS_XIN_CLK | Input muxed clock |
| 7 | DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK | Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK |
| 8 | DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSDSS_XIN_CLK |
Clocks for OBSCLK0_MUX_SEL_DEV_VD Device¶
Device: AM275X_DEV_OBSCLK0_MUX_SEL_DEV_VD (ID = 228)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 2 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 3 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 4 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 5 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 6 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 7 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 8 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 9 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_AM275_C7XV_WRAP_0_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 10 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 11 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 12 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 13 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 14 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK8 | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 15 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 16 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
| 17 | DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK |
Clocks for PBIST0 Device¶
Device: AM275X_DEV_PBIST0 (ID = 301)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST0_CLK8_CLK | Input clock |
| 9 | DEV_PBIST0_TCLK_CLK | Input clock |
Clocks for PBIST1 Device¶
Device: AM275X_DEV_PBIST1 (ID = 254)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST1_CLK8_CLK | Input clock |
| 9 | DEV_PBIST1_TCLK_CLK | Input clock |
Clocks for PBIST2 Device¶
Device: AM275X_DEV_PBIST2 (ID = 302)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST2_CLK8_CLK | Input clock |
| 9 | DEV_PBIST2_TCLK_CLK | Input clock |
Clocks for PBIST3 Device¶
Device: AM275X_DEV_PBIST3 (ID = 303)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST3_CLK8_CLK | Input clock |
| 9 | DEV_PBIST3_TCLK_CLK | Input clock |
Clocks for PBIST4 Device¶
Device: AM275X_DEV_PBIST4 (ID = 304)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST4_CLK8_CLK | Input clock |
| 9 | DEV_PBIST4_TCLK_CLK | Input clock |
Clocks for PBIST5 Device¶
Device: AM275X_DEV_PBIST5 (ID = 305)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST5_CLK8_CLK | Input clock |
| 9 | DEV_PBIST5_TCLK_CLK | Input clock |
Clocks for PBIST6 Device¶
Device: AM275X_DEV_PBIST6 (ID = 306)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST6_CLK8_CLK | Input clock |
| 9 | DEV_PBIST6_TCLK_CLK | Input clock |
Clocks for PBIST7 Device¶
Device: AM275X_DEV_PBIST7 (ID = 307)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST7_CLK8_CLK | Input clock |
| 9 | DEV_PBIST7_TCLK_CLK | Input clock |
Clocks for PBIST8 Device¶
Device: AM275X_DEV_PBIST8 (ID = 308)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_PBIST8_CLK8_CLK | Input clock |
| 9 | DEV_PBIST8_TCLK_CLK | Input clock |
Clocks for PSCSS0 Device¶
Device: AM275X_DEV_PSCSS0 (ID = 139)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PSCSS0_CLK | Input clock |
| 1 | DEV_PSCSS0_SLOW_CLK | Input clock |
Clocks for R5FSS0 Device¶
This device has no defined clocks.
Clocks for R5FSS0_CORE0 Device¶
Device: AM275X_DEV_R5FSS0_CORE0 (ID = 318)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS0_CORE0_CPU_CLK | Input muxed clock |
| 1 | DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK |
| 2 | DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 | Parent input clock option to DEV_R5FSS0_CORE0_CPU_CLK |
| 3 | DEV_R5FSS0_CORE0_INTERFACE_CLK | Input clock |
Clocks for R5FSS0_CORE1 Device¶
Device: AM275X_DEV_R5FSS0_CORE1 (ID = 319)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS0_CORE1_CPU_CLK | Input muxed clock |
| 1 | DEV_R5FSS0_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | Parent input clock option to DEV_R5FSS0_CORE1_CPU_CLK |
| 2 | DEV_R5FSS0_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 | Parent input clock option to DEV_R5FSS0_CORE1_CPU_CLK |
| 3 | DEV_R5FSS0_CORE1_INTERFACE_CLK | Input clock |
Clocks for R5FSS1 Device¶
This device has no defined clocks.
Clocks for R5FSS1_CORE0 Device¶
Device: AM275X_DEV_R5FSS1_CORE0 (ID = 320)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS1_CORE0_CPU_CLK | Input muxed clock |
| 1 | DEV_R5FSS1_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | Parent input clock option to DEV_R5FSS1_CORE0_CPU_CLK |
| 2 | DEV_R5FSS1_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 | Parent input clock option to DEV_R5FSS1_CORE0_CPU_CLK |
| 3 | DEV_R5FSS1_CORE0_INTERFACE_CLK | Input clock |
Clocks for R5FSS1_CORE1 Device¶
Device: AM275X_DEV_R5FSS1_CORE1 (ID = 321)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS1_CORE1_CPU_CLK | Input muxed clock |
| 1 | DEV_R5FSS1_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | Parent input clock option to DEV_R5FSS1_CORE1_CPU_CLK |
| 2 | DEV_R5FSS1_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 | Parent input clock option to DEV_R5FSS1_CORE1_CPU_CLK |
| 3 | DEV_R5FSS1_CORE1_INTERFACE_CLK | Input clock |
Clocks for RL2_CORE0_CFG0 Device¶
Device: AM275X_DEV_RL2_CORE0_CFG0 (ID = 326)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_CORE0_CFG0_CLK | Input clock |
Clocks for RL2_CORE0_CFG1 Device¶
Device: AM275X_DEV_RL2_CORE0_CFG1 (ID = 327)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_CORE0_CFG1_CLK | Input clock |
Clocks for RL2_CORE1_CFG0 Device¶
Device: AM275X_DEV_RL2_CORE1_CFG0 (ID = 328)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_CORE1_CFG0_CLK | Input clock |
Clocks for RL2_CORE1_CFG1 Device¶
Device: AM275X_DEV_RL2_CORE1_CFG1 (ID = 329)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_CORE1_CFG1_CLK | Input clock |
Clocks for RL2_OF_CBA4_0 Device¶
Device: AM275X_DEV_RL2_OF_CBA4_0 (ID = 322)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_OF_CBA4_0_CLK | Input clock |
| 1 | DEV_RL2_OF_CBA4_0_TAGMEM_CLK | Output clock |
Clocks for RL2_OF_CBA4_1 Device¶
Device: AM275X_DEV_RL2_OF_CBA4_1 (ID = 323)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_OF_CBA4_1_CLK | Input clock |
| 1 | DEV_RL2_OF_CBA4_1_TAGMEM_CLK | Output clock |
Clocks for RL2_OF_CBA4_2 Device¶
Device: AM275X_DEV_RL2_OF_CBA4_2 (ID = 324)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_OF_CBA4_2_CLK | Input clock |
| 1 | DEV_RL2_OF_CBA4_2_TAGMEM_CLK | Output clock |
Clocks for RL2_OF_CBA4_3 Device¶
Device: AM275X_DEV_RL2_OF_CBA4_3 (ID = 325)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RL2_OF_CBA4_3_CLK | Input clock |
| 1 | DEV_RL2_OF_CBA4_3_TAGMEM_CLK | Output clock |
Clocks for RTI0 Device¶
Device: AM275X_DEV_RTI0 (ID = 127)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI0_RTI_CLK | Input muxed clock |
| 1 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_RTI0_RTI_CLK |
| 2 | DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_RTI0_RTI_CLK |
| 3 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_RTI0_RTI_CLK |
| 4 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_RTI0_RTI_CLK |
| 5 | DEV_RTI0_VBUSP_CLK | Input clock |
Clocks for RTI1 Device¶
Device: AM275X_DEV_RTI1 (ID = 128)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI1_RTI_CLK | Input muxed clock |
| 1 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_RTI1_RTI_CLK |
| 2 | DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_RTI1_RTI_CLK |
| 3 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_RTI1_RTI_CLK |
| 4 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_RTI1_RTI_CLK |
| 5 | DEV_RTI1_VBUSP_CLK | Input clock |
Clocks for RTI2 Device¶
Device: AM275X_DEV_RTI2 (ID = 130)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI2_RTI_CLK | Input muxed clock |
| 1 | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_RTI2_RTI_CLK |
| 2 | DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_RTI2_RTI_CLK |
| 3 | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_RTI2_RTI_CLK |
| 4 | DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_RTI2_RTI_CLK |
| 5 | DEV_RTI2_VBUSP_CLK | Input clock |
Clocks for RTI3 Device¶
Device: AM275X_DEV_RTI3 (ID = 131)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI3_RTI_CLK | Input muxed clock |
| 1 | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_RTI3_RTI_CLK |
| 2 | DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_RTI3_RTI_CLK |
| 3 | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_RTI3_RTI_CLK |
| 4 | DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_RTI3_RTI_CLK |
| 5 | DEV_RTI3_VBUSP_CLK | Input clock |
Clocks for RTI4 Device¶
Device: AM275X_DEV_RTI4 (ID = 205)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI4_RTI_CLK | Input muxed clock |
| 1 | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_RTI4_RTI_CLK |
| 2 | DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_RTI4_RTI_CLK |
| 3 | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_RTI4_RTI_CLK |
| 4 | DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_RTI4_RTI_CLK |
| 5 | DEV_RTI4_VBUSP_CLK | Input clock |
Clocks for RTI5 Device¶
Device: AM275X_DEV_RTI5 (ID = 263)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI5_RTI_CLK | Input muxed clock |
| 1 | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_RTI5_RTI_CLK |
| 2 | DEV_RTI5_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_RTI5_RTI_CLK |
| 3 | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_RTI5_RTI_CLK |
| 4 | DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_RTI5_RTI_CLK |
| 5 | DEV_RTI5_VBUSP_CLK | Input clock |
Clocks for SMS0 Device¶
This device has no defined clocks.
Clocks for SPINLOCK0 Device¶
Device: AM275X_DEV_SPINLOCK0 (ID = 150)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SPINLOCK0_VCLK_CLK | Input clock |
Clocks for STM0 Device¶
Device: AM275X_DEV_STM0 (ID = 15)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_STM0_ATB_CLK | Input clock |
| 1 | DEV_STM0_CORE_CLK | Input clock |
| 2 | DEV_STM0_VBUSP_CLK | Input clock |
Clocks for TIMER0 Device¶
Device: AM275X_DEV_TIMER0 (ID = 36)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER0_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER0_TIMER_PWM | Output clock |
| 2 | DEV_TIMER0_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
Clocks for TIMER1 Device¶
Device: AM275X_DEV_TIMER1 (ID = 37)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER1_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER1_TIMER_PWM | Output clock |
| 2 | DEV_TIMER1_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1 | Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK |
| 4 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK |
Clocks for TIMER10 Device¶
Device: AM275X_DEV_TIMER10 (ID = 46)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER10_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER10_TIMER_PWM | Output clock |
| 2 | DEV_TIMER10_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
Clocks for TIMER11 Device¶
Device: AM275X_DEV_TIMER11 (ID = 47)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER11_TIMER_HCLK_CLK | Input clock |
| 2 | DEV_TIMER11_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT11 | Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK |
| 4 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK |
Clocks for TIMER12 Device¶
Device: AM275X_DEV_TIMER12 (ID = 288)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER12_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER12_TIMER_PWM | Output clock |
| 2 | DEV_TIMER12_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
Clocks for TIMER13 Device¶
Device: AM275X_DEV_TIMER13 (ID = 289)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER13_TIMER_HCLK_CLK | Input clock |
| 2 | DEV_TIMER13_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT13 | Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK |
| 4 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK |
Clocks for TIMER14 Device¶
Device: AM275X_DEV_TIMER14 (ID = 290)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER14_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER14_TIMER_PWM | Output clock |
| 2 | DEV_TIMER14_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
Clocks for TIMER15 Device¶
Device: AM275X_DEV_TIMER15 (ID = 291)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER15_TIMER_HCLK_CLK | Input clock |
| 2 | DEV_TIMER15_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT15 | Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK |
| 4 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK |
Clocks for TIMER2 Device¶
Device: AM275X_DEV_TIMER2 (ID = 38)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER2_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER2_TIMER_PWM | Output clock |
| 2 | DEV_TIMER2_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
Clocks for TIMER3 Device¶
Device: AM275X_DEV_TIMER3 (ID = 39)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER3_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER3_TIMER_PWM | Output clock |
| 2 | DEV_TIMER3_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3 | Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK |
| 4 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK |
Clocks for TIMER4 Device¶
Device: AM275X_DEV_TIMER4 (ID = 40)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER4_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER4_TIMER_PWM | Output clock |
| 2 | DEV_TIMER4_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
Clocks for TIMER5 Device¶
Device: AM275X_DEV_TIMER5 (ID = 41)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER5_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER5_TIMER_PWM | Output clock |
| 2 | DEV_TIMER5_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5 | Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK |
| 4 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK |
Clocks for TIMER6 Device¶
Device: AM275X_DEV_TIMER6 (ID = 42)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER6_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER6_TIMER_PWM | Output clock |
| 2 | DEV_TIMER6_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
Clocks for TIMER7 Device¶
Device: AM275X_DEV_TIMER7 (ID = 43)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER7_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER7_TIMER_PWM | Output clock |
| 2 | DEV_TIMER7_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7 | Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK |
| 4 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK |
Clocks for TIMER8 Device¶
Device: AM275X_DEV_TIMER8 (ID = 44)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER8_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER8_TIMER_PWM | Output clock |
| 2 | DEV_TIMER8_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
Clocks for TIMER9 Device¶
Device: AM275X_DEV_TIMER9 (ID = 45)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER9_TIMER_HCLK_CLK | Input clock |
| 2 | DEV_TIMER9_TIMER_TCLK_CLK | Input muxed clock |
| 3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT9 | Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK |
| 4 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM | Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK |
Clocks for TIMESYNC_EVENT_INTROUTER0 Device¶
Device: AM275X_DEV_TIMESYNC_EVENT_INTROUTER0 (ID = 6)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK | Input clock |
Clocks for UART0 Device¶
Device: AM275X_DEV_UART0 (ID = 146)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART0_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART0_FCLK_CLK_PARENT_USART_CLK_DIV_OUT0 | Parent input clock option to DEV_UART0_FCLK_CLK |
| 2 | DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART0_FCLK_CLK |
| 5 | DEV_UART0_VBUSP_CLK | Input clock |
Clocks for UART1 Device¶
Device: AM275X_DEV_UART1 (ID = 152)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART1_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART1_FCLK_CLK_PARENT_USART_CLK_DIV_OUT1 | Parent input clock option to DEV_UART1_FCLK_CLK |
| 2 | DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART1_FCLK_CLK |
| 5 | DEV_UART1_VBUSP_CLK | Input clock |
Clocks for UART2 Device¶
Device: AM275X_DEV_UART2 (ID = 153)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART2_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART2_FCLK_CLK_PARENT_USART_CLK_DIV_OUT2 | Parent input clock option to DEV_UART2_FCLK_CLK |
| 2 | DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART2_FCLK_CLK |
| 5 | DEV_UART2_VBUSP_CLK | Input clock |
Clocks for UART3 Device¶
Device: AM275X_DEV_UART3 (ID = 154)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART3_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART3_FCLK_CLK_PARENT_USART_CLK_DIV_OUT3 | Parent input clock option to DEV_UART3_FCLK_CLK |
| 2 | DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART3_FCLK_CLK |
| 5 | DEV_UART3_VBUSP_CLK | Input clock |
Clocks for UART4 Device¶
Device: AM275X_DEV_UART4 (ID = 155)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART4_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART4_FCLK_CLK_PARENT_USART_CLK_DIV_OUT4 | Parent input clock option to DEV_UART4_FCLK_CLK |
| 2 | DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART4_FCLK_CLK |
| 5 | DEV_UART4_VBUSP_CLK | Input clock |
Clocks for UART5 Device¶
Device: AM275X_DEV_UART5 (ID = 156)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART5_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART5_FCLK_CLK_PARENT_USART_CLK_DIV_OUT5 | Parent input clock option to DEV_UART5_FCLK_CLK |
| 2 | DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART5_FCLK_CLK |
| 5 | DEV_UART5_VBUSP_CLK | Input clock |
Clocks for UART6 Device¶
Device: AM275X_DEV_UART6 (ID = 158)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART6_FCLK_CLK | Input muxed clock |
| 1 | DEV_UART6_FCLK_CLK_PARENT_USART_CLK_DIV_OUT6 | Parent input clock option to DEV_UART6_FCLK_CLK |
| 2 | DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK | Parent input clock option to DEV_UART6_FCLK_CLK |
| 5 | DEV_UART6_VBUSP_CLK | Input clock |
Clocks for USB0 Device¶
Device: AM275X_DEV_USB0 (ID = 161)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_USB0_BUS_CLK | Input clock |
| 1 | DEV_USB0_CFG_CLK | Input clock |
| 2 | DEV_USB0_USB2_APB_PCLK_CLK | Input clock |
| 3 | DEV_USB0_USB2_REFCLOCK_CLK | Input muxed clock |
| 4 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK |
| 5 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK | Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK |
| 10 | DEV_USB0_USB2_TAP_TCK | Input clock |
Clocks for WKUP_CLKOUT_SEL_DEV_VD Device¶
Device: AM275X_DEV_WKUP_CLKOUT_SEL_DEV_VD (ID = 226)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK | Input muxed clock |
| 1 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
| 2 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
| 3 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
| 4 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
| 5 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
| 6 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
| 7 | DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK |
Clocks for WKUP_DEEPSLEEP_SOURCES0 Device¶
Device: AM275X_DEV_WKUP_DEEPSLEEP_SOURCES0 (ID = 176)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK | Input clock |
Clocks for WKUP_ESM0 Device¶
Device: AM275X_DEV_WKUP_ESM0 (ID = 64)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_ESM0_CLK | Input clock |
Clocks for WKUP_GTC0 Device¶
Device: AM275X_DEV_WKUP_GTC0 (ID = 61)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_GTC0_GTC_CLK | Input muxed clock |
| 1 | DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 2 | DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 3 | DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 5 | DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 6 | DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 7 | DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 8 | DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_WKUP_GTC0_GTC_CLK |
| 9 | DEV_WKUP_GTC0_VBUSP_CLK | Input muxed clock |
| 10 | DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK |
| 11 | DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_GTC0_VBUSP_CLK |
Clocks for WKUP_I2C0 Device¶
Device: AM275X_DEV_WKUP_I2C0 (ID = 107)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_I2C0_CLK | Input muxed clock |
| 1 | DEV_WKUP_I2C0_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_I2C0_CLK |
| 2 | DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_I2C0_CLK |
| 3 | DEV_WKUP_I2C0_PISCL | Input clock |
| 4 | DEV_WKUP_I2C0_PISYS_CLK | Input clock |
| 5 | DEV_WKUP_I2C0_PORSCL | Output clock |
Clocks for WKUP_PBIST0 Device¶
Device: AM275X_DEV_WKUP_PBIST0 (ID = 165)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_WKUP_PBIST0_CLK8_CLK | Input clock |
Clocks for WKUP_PBIST1 Device¶
Device: AM275X_DEV_WKUP_PBIST1 (ID = 309)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 7 | DEV_WKUP_PBIST1_CLK8_CLK | Input clock |
| 9 | DEV_WKUP_PBIST1_TCLK_CLK | Input clock |
Clocks for WKUP_PSC0 Device¶
Device: AM275X_DEV_WKUP_PSC0 (ID = 140)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_PSC0_CLK | Input clock |
| 1 | DEV_WKUP_PSC0_SLOW_CLK | Input clock |
Clocks for WKUP_R5FSS0 Device¶
This device has no defined clocks.
Clocks for WKUP_R5FSS0_CORE0 Device¶
Device: AM275X_DEV_WKUP_R5FSS0_CORE0 (ID = 121)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_R5FSS0_CORE0_CPU_CLK | Input muxed clock |
| 1 | DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_WKUP_R5FSS0_CORE0_CPU_CLK |
| 2 | DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_R5FSS0_CORE0_CPU_CLK |
| 5 | DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK | Input clock |
Clocks for WKUP_R5FSS0_SS0 Device¶
This device has no defined clocks.
Clocks for WKUP_RTCSS0 Device¶
Device: AM275X_DEV_WKUP_RTCSS0 (ID = 117)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_RTCSS0_ANA_OSC32K_CLK | Input muxed clock |
| 1 | DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK |
| 2 | DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_WKUP_RTCSS0_ANA_OSC32K_CLK |
| 4 | DEV_WKUP_RTCSS0_JTAG_WRCK | Input clock |
| 6 | DEV_WKUP_RTCSS0_VCLK_CLK | Input muxed clock |
| 7 | DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK |
| 8 | DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_RTCSS0_VCLK_CLK |
Clocks for WKUP_RTI0 Device¶
Device: AM275X_DEV_WKUP_RTI0 (ID = 132)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_RTI0_RTI_CLK | Input muxed clock |
| 1 | DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_WKUP_RTI0_RTI_CLK |
| 2 | DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_WKUP_RTI0_RTI_CLK |
| 3 | DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_WKUP_RTI0_RTI_CLK |
| 4 | DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_WKUP_RTI0_RTI_CLK |
| 5 | DEV_WKUP_RTI0_VBUSP_CLK | Input muxed clock |
| 6 | DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK |
| 7 | DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_RTI0_VBUSP_CLK |
Clocks for WKUP_TIMER0 Device¶
Device: AM275X_DEV_WKUP_TIMER0 (ID = 110)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_TIMER0_TIMER_HCLK_CLK | Input muxed clock |
| 1 | DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK |
| 2 | DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_TIMER0_TIMER_HCLK_CLK |
| 3 | DEV_WKUP_TIMER0_TIMER_PWM | Output clock |
| 4 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK | Input muxed clock |
| 5 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 6 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT02 | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 7 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 8 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 9 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 10 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 11 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
| 12 | DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 | Parent input clock option to DEV_WKUP_TIMER0_TIMER_TCLK_CLK |
Clocks for WKUP_TIMER1 Device¶
Device: AM275X_DEV_WKUP_TIMER1 (ID = 111)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_TIMER1_TIMER_HCLK_CLK | Input muxed clock |
| 1 | DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK |
| 2 | DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_TIMER1_TIMER_HCLK_CLK |
| 4 | DEV_WKUP_TIMER1_TIMER_TCLK_CLK | Input clock |
Clocks for WKUP_UART0 Device¶
Device: AM275X_DEV_WKUP_UART0 (ID = 114)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_UART0_FCLK_CLK | Input clock |
| 3 | DEV_WKUP_UART0_VBUSP_CLK | Input muxed clock |
| 4 | DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK |
| 5 | DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_UART0_VBUSP_CLK |
Clocks for WKUP_VTM0 Device¶
Device: AM275X_DEV_WKUP_VTM0 (ID = 95)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_VTM0_FIX_REF2_CLK | Input clock |
| 1 | DEV_WKUP_VTM0_FIX_REF_CLK | Input clock |
| 2 | DEV_WKUP_VTM0_VBUSP_CLK | Input muxed clock |
| 3 | DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK |
| 4 | DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | Parent input clock option to DEV_WKUP_VTM0_VBUSP_CLK |