132 #ifndef ti_drivers_spi_SPIMSP432E4DMA__include 133 #define ti_drivers_spi_SPIMSP432E4DMA__include 142 #include <ti/devices/msp432e4/inc/msp432.h> 144 #include <ti/devices/msp432e4/driverlib/pin_map.h> 147 #include <ti/drivers/dpl/HwiP.h> 148 #include <ti/drivers/dpl/SemaphoreP.h> 155 #define SPIMSP432E4_PA2_SSI0CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 2, GPIO_PA2_SSI0CLK) 160 #define SPIMSP432E4_PA3_SSI0FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 3, GPIO_PA3_SSI0FSS) 165 #define SPIMSP432E4_PA4_SSI0XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 4, GPIO_PA4_SSI0XDAT0) 170 #define SPIMSP432E4_PA5_SSI0XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTA, 5, GPIO_PA5_SSI0XDAT1) 175 #define SPIMSP432E4_PB5_SSI1CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 5, GPIO_PB5_SSI1CLK) 180 #define SPIMSP432E4_PB4_SSI1FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTB, 4, GPIO_PB4_SSI1FSS) 185 #define SPIMSP432E4_PE4_SSI1XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 4, GPIO_PE4_SSI1XDAT0) 190 #define SPIMSP432E4_PE5_SSI1XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTE, 5, GPIO_PE5_SSI1XDAT1) 195 #define SPIMSP432E4_PD3_SSI2CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 3, GPIO_PD3_SSI2CLK) 200 #define SPIMSP432E4_PG7_SSI2CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 7, GPIO_PG7_SSI2CLK) 205 #define SPIMSP432E4_PD2_SSI2FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 2, GPIO_PD2_SSI2FSS) 210 #define SPIMSP432E4_PG6_SSI2FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 6, GPIO_PG6_SSI2FSS) 215 #define SPIMSP432E4_PD1_SSI2XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 1, GPIO_PD1_SSI2XDAT0) 220 #define SPIMSP432E4_PG5_SSI2XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 5, GPIO_PG5_SSI2XDAT0) 225 #define SPIMSP432E4_PD0_SSI2XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTD, 0, GPIO_PD0_SSI2XDAT1) 230 #define SPIMSP432E4_PG4_SSI2XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTG, 4, GPIO_PG4_SSI2XDAT1) 235 #define SPIMSP432E4_PQ0_SSI3CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 0, GPIO_PQ0_SSI3CLK) 240 #define SPIMSP432E4_PF3_SSI3CLK GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 3, GPIO_PF3_SSI3CLK) 245 #define SPIMSP432E4_PQ1_SSI3FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 1, GPIO_PQ1_SSI3FSS) 250 #define SPIMSP432E4_PF2_SSI3FSS GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 2, GPIO_PF2_SSI3FSS) 255 #define SPIMSP432E4_PQ2_SSI3XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 2, GPIO_PQ2_SSI3XDAT0) 260 #define SPIMSP432E4_PF1_SSI3XDAT0 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 1, GPIO_PF1_SSI3XDAT0) 265 #define SPIMSP432E4_PQ3_SSI3XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTQ, 3, GPIO_PQ3_SSI3XDAT1) 270 #define SPIMSP432E4_PF0_SSI3XDAT1 GPIOMSP432E4_pinConfigMask(GPIOMSP432E4_PORTF, 0, GPIO_PF0_SSI3XDAT1) 299 #define SPIMSP432E4_PIN_NO_CONFIG (0xFFFFFFFF) uint32_t activeChannel
Definition: SPIMSP432E4DMA.h:426
SPIMSP432E4DMA Object.
Definition: SPIMSP432E4DMA.h:409
uint32_t intNum
Definition: SPIMSP432E4DMA.h:376
uint32_t txDmaChannel
Definition: SPIMSP432E4DMA.h:389
uint32_t transferTimeout
Definition: SPIMSP432E4DMA.h:425
UDMAMSP432E4 Global configuration.
Definition: UDMAMSP432E4.h:143
void(* SPI_CallbackFxn)(SPI_Handle handle, SPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in SPI_MODE_CALLBACK.
Definition: SPI.h:569
enum SPI_Mode_ SPI_Mode
Definitions for various SPI modes of operation.
uint32_t xdat1PinMask
Definition: SPIMSP432E4DMA.h:401
A SPI_Transaction data structure is used with SPI_transfer(). It indicates how many SPI_FrameFormat f...
Definition: SPI.h:548
uDMA driver implementation for MSP432E4.
size_t framesTransferred
Definition: SPIMSP432E4DMA.h:419
uint16_t minDmaTransferSize
Definition: SPIMSP432E4DMA.h:392
SPIMSP432E4DMA Hardware attributes.
Definition: SPIMSP432E4DMA.h:372
uint32_t baseAddr
Definition: SPIMSP432E4DMA.h:374
UDMAMSP432E4_Handle dmaHandle
Definition: SPIMSP432E4DMA.h:413
uint32_t dataSize
Definition: SPIMSP432E4DMA.h:424
uint16_t defaultTxBufValue
Definition: SPIMSP432E4DMA.h:384
SPI_Mode spiMode
Definition: SPIMSP432E4DMA.h:431
size_t framesQueued
Definition: SPIMSP432E4DMA.h:418
size_t altTransferSize
Definition: SPIMSP432E4DMA.h:421
uint32_t intPriority
Definition: SPIMSP432E4DMA.h:378
uint32_t xdat0PinMask
Definition: SPIMSP432E4DMA.h:399
uint32_t bitRate
Definition: SPIMSP432E4DMA.h:423
uint16_t rxScratchBuf
Definition: SPIMSP432E4DMA.h:429
uint32_t busyBit
Definition: SPIMSP432E4DMA.h:427
enum SPI_TransferMode_ SPI_TransferMode
SPI transfer mode determines the whether the SPI controller operates synchronously or asynchronously...
The definition of a SPI function table that contains the required set of functions to control a speci...
Definition: SPI.h:683
SPI_Transaction * headPtr
Definition: SPIMSP432E4DMA.h:415
struct SPIMSP432E4DMA_Object SPIMSP432E4DMA_Object
SPIMSP432E4DMA Object.
SemaphoreP_Handle transferComplete
Definition: SPIMSP432E4DMA.h:411
uint32_t rxDmaChannel
Definition: SPIMSP432E4DMA.h:387
HwiP_Handle hwiHandle
Definition: SPIMSP432E4DMA.h:410
uint16_t * scratchBufPtr
Definition: SPIMSP432E4DMA.h:381
uint32_t fssPinMask
Definition: SPIMSP432E4DMA.h:397
uint32_t clkPinMask
Definition: SPIMSP432E4DMA.h:395
SPI_CallbackFxn transferCallbackFxn
Definition: SPIMSP432E4DMA.h:412
SPI_Transaction * tailPtr
Definition: SPIMSP432E4DMA.h:416
const SPI_FxnTable SPIMSP432E4DMA_fxnTable
SPI_TransferMode transferMode
Definition: SPIMSP432E4DMA.h:432
bool isOpen
Definition: SPIMSP432E4DMA.h:435
struct SPIMSP432E4DMA_HWAttrs SPIMSP432E4DMA_HWAttrs
SPIMSP432E4DMA Hardware attributes.
size_t priTransferSize
Definition: SPIMSP432E4DMA.h:420
uint8_t format
Definition: SPIMSP432E4DMA.h:434