LRFDRFE

Instance: LRFDRFE
Component: LRFDRFE
Base address: 0x40083000


TOP:LRFDRFE Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

ENABLE

RW

32

0x0000 0000

0x0000 0000

0x4008 3000

FWSRC

RW

32

0x0000 0000

0x0000 0004

0x4008 3004

INIT

WO

32

0x0000 0000

0x0000 0008

0x4008 3008

PDREQ

RW

32

0x0000 0000

0x0000 000C

0x4008 300C

EVT0

RO

32

0x0000 0000

0x0000 0010

0x4008 3010

EVT1

RO

32

0x0000 0000

0x0000 0014

0x4008 3014

EVTMSK0

RW

32

0x0000 0000

0x0000 0018

0x4008 3018

EVTMSK1

RW

32

0x0000 0000

0x0000 001C

0x4008 301C

EVTCLR0

WO

32

0x0000 0000

0x0000 0020

0x4008 3020

EVTCLR1

WO

32

0x0000 0000

0x0000 0024

0x4008 3024

HFXTSTAT

RO

32

0x0000 0000

0x0000 0028

0x4008 3028

RFSTATE

RW

32

0x0000 0000

0x0000 0030

0x4008 3030

API

RO

32

0x0000 0000

0x0000 0048

0x4008 3048

CMDPAR0

RO

32

0x0000 0000

0x0000 004C

0x4008 304C

CMDPAR1

RO

32

0x0000 0000

0x0000 0050

0x4008 3050

MSGBOX

RW

32

0x0000 0000

0x0000 0054

0x4008 3054

MCEDATOUT0

RW

32

0x0000 0000

0x0000 0058

0x4008 3058

MCEDATIN0

RO

32

0x0000 0000

0x0000 005C

0x4008 305C

MCECMDOUT

RW

32

0x0000 0000

0x0000 0060

0x4008 3060

MCECMDIN

RO

32

0x0000 0000

0x0000 0064

0x4008 3064

PBEDATOUT0

RW

32

0x0000 0000

0x0000 0068

0x4008 3068

PBEDATIN0

RO

32

0x0000 0000

0x0000 006C

0x4008 306C

PBECMDOUT

RW

32

0x0000 0000

0x0000 0070

0x4008 3070

PBECMDIN

RO

32

0x0000 0000

0x0000 0074

0x4008 3074

STRB

WO

32

0x0000 0000

0x0000 0078

0x4008 3078

MAGNTHRCFG

RW

32

0x0000 0000

0x0000 0080

0x4008 3080

MAGNTHR

RW

32

0x0000 0000

0x0000 0084

0x4008 3084

RSSIOFFSET

RW

32

0x0000 0000

0x0000 0088

0x4008 3088

GAINCTL

RW

32

0x0000 0000

0x0000 008C

0x4008 308C

MAGNCTL0

RW

32

0x0000 0000

0x0000 0090

0x4008 3090

MAGNCTL1

RW

32

0x0000 0000

0x0000 0094

0x4008 3094

SPARE0

RW

32

0x0000 0000

0x0000 0098

0x4008 3098

SPARE1

RW

32

0x0000 0000

0x0000 009C

0x4008 309C

SPARE2

RW

32

0x0000 0000

0x0000 00A0

0x4008 30A0

SPARE3

RW

32

0x0000 0000

0x0000 00A4

0x4008 30A4

SPARE4

RW

32

0x0000 0000

0x0000 00A8

0x4008 30A8

SPARE5

RW

32

0x0000 0000

0x0000 00AC

0x4008 30AC

LNA

RW

32

0x0000 0000

0x0000 00B0

0x4008 30B0

IFAMPRFLDO

RW

32

0x0000 0000

0x0000 00B4

0x4008 30B4

PA0

RW

32

0x0000 0000

0x0000 00B8

0x4008 30B8

PA1

RW

32

0x0000 0000

0x0000 00BC

0x4008 30BC

ULNA

RW

32

0x0000 0000

0x0000 00C0

0x4008 30C0

IFADC0

RW

32

0x0000 0000

0x0000 00C4

0x4008 30C4

IFADC1

RW

32

0x0000 0000

0x0000 00C8

0x4008 30C8

IFADCLF

RW

32

0x0000 0000

0x0000 00CC

0x4008 30CC

IFADCQUANT

RW

32

0x0000 0000

0x0000 00D0

0x4008 30D0

IFADCALDO

RW

32

0x0000 0000

0x0000 00D4

0x4008 30D4

IFADCDLDO

RW

32

0x0000 0000

0x0000 00D8

0x4008 30D8

IFADCTST

RW

32

0x0000 0000

0x0000 00DC

0x4008 30DC

ATSTREFL

RW

32

0x0000 0000

0x0000 00E0

0x4008 30E0

ATSTREFH

RW

32

0x0000 0000

0x0000 00E4

0x4008 30E4

DCO

RW

32

0x0000 0000

0x0000 00E8

0x4008 30E8

DIV

RW

32

0x0000 0000

0x0000 00EC

0x4008 30EC

DIVLDO

RW

32

0x0000 0000

0x0000 00F0

0x4008 30F0

TDCLDO

RW

32

0x0000 0000

0x0000 00F4

0x4008 30F4

DCOLDO0

RW

32

0x0000 0000

0x0000 00F8

0x4008 30F8

DCOLDO1

RW

32

0x0000 0000

0x0000 00FC

0x4008 30FC

PRE0

RW

32

0x0000 0000

0x0000 0100

0x4008 3100

PRE1

RW

32

0x0000 0000

0x0000 0104

0x4008 3104

PRE2

RW

32

0x0000 0000

0x0000 0108

0x4008 3108

PRE3

RW

32

0x0000 0000

0x0000 010C

0x4008 310C

CAL0

RW

32

0x0000 0000

0x0000 0110

0x4008 3110

CAL1

RW

32

0x0000 0000

0x0000 0114

0x4008 3114

CAL2

RW

32

0x0000 0000

0x0000 0118

0x4008 3118

CAL3

RW

32

0x0000 0000

0x0000 011C

0x4008 311C

MISC0

RW

32

0x0000 0000

0x0000 0120

0x4008 3120

MISC1

RW

32

0x0000 0000

0x0000 0124

0x4008 3124

LF0

RW

32

0x0000 0000

0x0000 0128

0x4008 3128

LF1

RW

32

0x0000 0000

0x0000 012C

0x4008 312C

PHEDISC

RW

32

0x0000 0000

0x0000 0130

0x4008 3130

PHINIT

RW

32

0x0000 0000

0x0000 0134

0x4008 3134

PLLMON0

RW

32

0x0000 0000

0x0000 0138

0x4008 3138

PLLMON1

RW

32

0x0000 0000

0x0000 013C

0x4008 313C

MOD0

RW

32

0x0000 0000

0x0000 0140

0x4008 3140

MOD1

RW

32

0x0000 0000

0x0000 0144

0x4008 3144

DTX0

RW

32

0x0000 0000

0x0000 0148

0x4008 3148

DTX1

RW

32

0x0000 0000

0x0000 014C

0x4008 314C

DTX2

RW

32

0x0000 0000

0x0000 0150

0x4008 3150

DTX3

RW

32

0x0000 0000

0x0000 0154

0x4008 3154

DTX4

RW

32

0x0000 0000

0x0000 0158

0x4008 3158

DTX5

RW

32

0x0000 0000

0x0000 015C

0x4008 315C

DTX6

RW

32

0x0000 0000

0x0000 0160

0x4008 3160

DTX7

RW

32

0x0000 0000

0x0000 0164

0x4008 3164

DTX8

RW

32

0x0000 0000

0x0000 0168

0x4008 3168

DTX9

RW

32

0x0000 0000

0x0000 016C

0x4008 316C

DTX10

RW

32

0x0000 0000

0x0000 0170

0x4008 3170

DTX11

RW

32

0x0000 0000

0x0000 0174

0x4008 3174

PLLM0L

RW

32

0x0000 0000

0x0000 0178

0x4008 3178

PLLM0H

RW

32

0x0000 0000

0x0000 017C

0x4008 317C

PLLM1L

RW

32

0x0000 0000

0x0000 0180

0x4008 3180

PLLM1H

RW

32

0x0000 0000

0x0000 0184

0x4008 3184

CALMCRS

RW

32

0x0000 0000

0x0000 0188

0x4008 3188

CALMMID

RW

32

0x0000 0000

0x0000 018C

0x4008 318C

REFDIV

RW

32

0x0000 0000

0x0000 0190

0x4008 3190

DLOCTL0

RW

32

0x0000 0000

0x0000 0198

0x4008 3198

DLOCTL1

RW

32

0x0000 0000

0x0000 01A0

0x4008 31A0

DCOOVR0

RW

32

0x0000 0000

0x0000 01A8

0x4008 31A8

DCOOVR1

RW

32

0x0000 0000

0x0000 01AC

0x4008 31AC

DTST

RW

32

0x0000 0000

0x0000 01B0

0x4008 31B0

DLOEV

RO

32

0x0000 0000

0x0000 01B4

0x4008 31B4

DTSTRD

RO

32

0x0000 0000

0x0000 01B8

0x4008 31B8

FDCOSPANLSB

RO

32

0x0000 0000

0x0000 01BC

0x4008 31BC

FDCOSPANMSB

RO

32

0x0000 0000

0x0000 01C0

0x4008 31C0

TDCCAL

RO

32

0x0000 0000

0x0000 01C4

0x4008 31C4

CALRES

RO

32

0x0000 0000

0x0000 01C8

0x4008 31C8

GPI

RO

32

0x0000 0000

0x0000 01CC

0x4008 31CC

MATHACCELIN

RW

32

0x0000 0000

0x0000 01D0

0x4008 31D0

LIN2LOGOUT

RO

32

0x0000 0000

0x0000 01D4

0x4008 31D4

DIVBY3OUT

RO

32

0x0000 0000

0x0000 01D8

0x4008 31D8

TIMCTL

RW

32

0x0000 0000

0x0000 01DC

0x4008 31DC

TIMINC

RW

32

0x0000 0000

0x0000 01E0

0x4008 31E0

TIMPER

RW

32

0x0000 0000

0x0000 01E4

0x4008 31E4

TIMCNT

RO

32

0x0000 0000

0x0000 01E8

0x4008 31E8

TIMCAPT

RO

32

0x0000 0000

0x0000 01EC

0x4008 31EC

TRCCTRL

WO

32

0x0000 0000

0x0000 01F0

0x4008 31F0

TRCSTAT

RO

32

0x0000 0000

0x0000 01F4

0x4008 31F4

TRCCMD

RW

32

0x0000 0000

0x0000 01F8

0x4008 31F8

TRCPAR0

RW

32

0x0000 0000

0x0000 01FC

0x4008 31FC

TRCPAR1

RW

32

0x0000 0000

0x0000 0200

0x4008 3200

GPOCTL

RW

32

0x0000 0000

0x0000 0204

0x4008 3204

ANAISOCTL

RW

32

0x0000 000F

0x0000 0208

0x4008 3208

DIVCTL

RW

32

0x0000 0000

0x0000 020C

0x4008 320C

RXCTRL

RW

32

0x0000 0000

0x0000 0210

0x4008 3210

MAGNACC0

RO

32

0x0000 0000

0x0000 0214

0x4008 3214

MAGNACC1

RO

32

0x0000 0000

0x0000 0218

0x4008 3218

RSSI

RW

32

0x0000 0000

0x0000 021C

0x4008 321C

RSSIMAX

RW

32

0x0000 0000

0x0000 0220

0x4008 3220

RFGAIN

RW

32

0x0000 0000

0x0000 0224

0x4008 3224

IFADCSTAT

RO

32

0x0000 0000

0x0000 0228

0x4008 3228

DIVSTA

RO

32

0x0000 0000

0x0000 022C

0x4008 322C

DIVIDENDL

WO

32

0x0000 0000

0x0000 0230

0x4008 3230

DIVIDENDH

WO

32

0x0000 0000

0x0000 0234

0x4008 3234

DIVISORL

RW

32

0x0000 0000

0x0000 0238

0x4008 3238

DIVISORH

RW

32

0x0000 0000

0x0000 023C

0x4008 323C

QUOTIENTL

RO

32

0x0000 0000

0x0000 0240

0x4008 3240

QUOTIENTH

RO

32

0x0000 0000

0x0000 0244

0x4008 3244

PRODUCTL

RO

32

0x0000 0000

0x0000 0248

0x4008 3248

PRODUCTH

RO

32

0x0000 0000

0x0000 024C

0x4008 324C

MULTSTA

RO

32

0x0000 0000

0x0000 0250

0x4008 3250

MULTCFG

RW

32

0x0000 0000

0x0000 0258

0x4008 3258

TOP:LRFDRFE Register Descriptions

TOP:LRFDRFE:ENABLE

Address Offset 0x0000 0000
Physical Address 0x4008 3000 Instance 0x4008 3000
Description RFE Enable
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 ACC1 Enables the Magnitude Accumulator 1
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
2 ACC0 Enables the Magnitude Accumulator 0
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
1 LOCTIM Enables the Local timer
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
0 TOPSM Enables the TOPsm (RFE)
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0

TOP:LRFDRFE:FWSRC

Address Offset 0x0000 0004
Physical Address 0x4008 3004 Instance 0x4008 3004
Description RFE Program Source Select
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 DATARAM Selects RAM to use for data storage
Value ENUM Name Description
0x0 RFERAM Use RFERAM for data
0x1 S2RRAM Use S2RRAM for data
RW 0
1 FWRAM Selects RAM to use for program memory
Value ENUM Name Description
0x0 RFERAM Run code from RFERAM
0x1 S2RRAM Run code from S2RRAM
RW 0
0 BANK Selects 2K bank within the program memory as FW source.
This controls MSB of address line towards program memory.
Value ENUM Name Description
0x0 ZERO Run code from bank 0
0x1 ONE Run code from bank 1
RW 0

TOP:LRFDRFE:INIT

Address Offset 0x0000 0008
Physical Address 0x4008 3008 Instance 0x4008 3008
Description RFE Initialization
Type WO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 ACC1 Synchronous reset to magnitude accumulator 1
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
2 ACC0 Synchronous reset to magnitude accumulator 0
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
1 LOCTIM Synchronous reset to local timer
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
0 TOPSM Synchronous reset to TOPsm (RFE)
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0

TOP:LRFDRFE:PDREQ

Address Offset 0x0000 000C
Physical Address 0x4008 300C Instance 0x4008 300C
Description RFE Power-down
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 TOPSMPDREQ Requests power down for TOPsm core. If the TOPsm has an ongoing memory access, the hardware will safely gate the clock after the transaction has completed.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0

TOP:LRFDRFE:EVT0

Address Offset 0x0000 0010
Physical Address 0x4008 3010 Instance 0x4008 3010
Description RFE Event Flags 0
Type RO
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 MAGNTHR Magnitude accumulator amplitude is above MAGNTHR theshold
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
13 S2RSTOP S2R has written to LRFDS2R:STOP.ADDR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
12 SYSTCMP2 Systimer compare event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
11 SYSTCMP1 Systimer compare event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
10 SYSTCMP0 Systimer compare event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
9 PBERFEDAT New data from PBE in PBEDATIN0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
8 MDMRFEDAT New data from MCE in MCEDATIN0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 DLO Event from DLO state machine
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 PBECMD New command from PBE in PBECMDIN
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 COUNTER Counter value reached in local timer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 MDMCMD New command from MCE in MCECMDIN
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 ACC1 Accumulation period completed in magnitude accumulator 1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 ACC0 Accumulation period completed in magnitude accumulator 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 TIMER Timer period expired in local timer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 RFEAPI New RFE API availabe in API
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE:EVT1

Address Offset 0x0000 0014
Physical Address 0x4008 3014 Instance 0x4008 3014
Description RFE Event Flags 1
Type RO
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 PREREFCLK Prescaled REFCLK event, controlled by DCOCTL0.LOOPUPD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
12 REFCLK REFCLK event from DLO
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
11 FBLWTHR Finecode below programmed threshold event from DLO state machine
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
10 FABVTHR Finecode above programmed threshold event from DLO state machine
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
9 LOCK Lock event from DLO state machine
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
8 LOL Loss of lock event from DLO state machine
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 GPI7 External input event line GPI7 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 GPI6 External input event line GPI6 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 GPI5 External input event line GPI5 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 GPI4 External input event line GPI4 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 GPI3 External input event line GPI3 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 GPI2 External input event line GPI2 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 GPI1 External input event line GPI1 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 GPI0 External input event line GPI0 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE:EVTMSK0

Address Offset 0x0000 0018
Physical Address 0x4008 3018 Instance 0x4008 3018
Description RFE Event Mask 0
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 MAGNTHR Enable mask for event EVT0.MAGNTHR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
13 S2RSTOP Enable mask for event EVT0.S2RSTOP
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
12 SYSTCMP2 Enable mask for event EVT0.SYSTCMP2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
11 SYSTCMP1 Enable mask for event EVT0.SYSTCMP1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
10 SYSTCMP0 Enable mask for event EVT0.SYSTCMP0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 PBERFEDAT Enable mask for event EVT0.PBERFEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 MDMRFEDAT Enable mask for event EVT0.MDMRFEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 DLO Enable mask for event EVT0.DLO
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 PBECMD Enable mask for event EVT0.PBECMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 COUNTER Enable mask for event EVT0.COUNTER
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 MDMCMD Enable mask for event EVT0.MDMCMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 ACC1 Enable mask for event EVT0.ACC1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 ACC0 Enable mask for event EVT0.ACC0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 TIMER Enable mask for event EVT0.TIMER
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 RFEAPI Enable mask for event EVT0.RFEAPI
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDRFE:EVTMSK1

Address Offset 0x0000 001C
Physical Address 0x4008 301C Instance 0x4008 301C
Description RFE Event Mask 1
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 PREREFCLK Enable mask for event EVT1.PREREFCLK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
12 REFCLK Enable mask for event EVT1.REFCLK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
11 FBLWTHR Enable mask for event EVT1.FBLWTHR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
10 FABVTHR Enable mask for event EVT1.FABVTHR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 LOCK Enable mask for event EVT1.LOCK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 LOL Enable mask for event EVT1.LOL
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 GPI7 Enable mask for event EVT1.GPI7
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 GPI6 Enable mask for event EVT1.GPI6
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 GPI5 Enable mask for event EVT1.GPI5
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 GPI4 Enable mask for event EVT1.GPI4
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 GPI3 Enable mask for event EVT1.GPI3
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 GPI2 Enable mask for event EVT1.GPI2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 GPI1 Enable mask for event EVT1.GPI1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 GPI0 Enable mask for event EVT1.GPI0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDRFE:EVTCLR0

Address Offset 0x0000 0020
Physical Address 0x4008 3020 Instance 0x4008 3020
Description RFE Event Clear 0
Type WO
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 MAGNTHR Clear event EVT0.MAGNTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
13 S2RSTOP Clear event EVT0.S2RSTOP
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
12 SYSTCMP2 Clear event EVT0.SYSTCMP2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
11 SYSTCMP1 Clear event EVT0.SYSTCMP1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
10 SYSTCMP0 Clear event EVT0.SYSTCMP0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
9 PBERFEDAT Clear event EVT0.PBERFEDAT
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
8 MDMRFEDAT Clear event EVT0.MDMRFEDAT
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
7 DLO Clear event EVT0.DLO
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 PBECMD Clear event EVT0.PBECMD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 COUNTER Clear event EVT0.COUNTER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 MDMCMD Clear event EVT0.MDMCMD
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 ACC1 Clear event EVT0.ACC1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 ACC0 Clear event EVT0.ACC0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 TIMER Clear event EVT0.TIMER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 RFEAPI Clear event EVT0.RFEAPI
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDRFE:EVTCLR1

Address Offset 0x0000 0024
Physical Address 0x4008 3024 Instance 0x4008 3024
Description RFE Event Clear 1
Type WO
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 PREREFCLK Clear event EVT1.PREREFCLK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
12 REFCLK Clear event EVT1.REFCLK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
11 FBLWTHR Clear event EVT1.FBLWTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
10 FABVTHR Clear event EVT1.FABVTHR
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
9 LOCK Clear event EVT1.LOCK
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
8 LOL Clear event EVT1.LOL
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
7 GPI7 Clear event EVT1.GPI7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 GPI6 Clear event EVT1.GPI6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 GPI5 Clear event EVT1.GPI5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 GPI4 Clear event EVT1.GPI4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 GPI3 Clear event EVT1.GPI3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 GPI2 Clear event EVT1.GPI2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 GPI1 Clear event EVT1.GPI1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 GPI0 Clear event EVT1.GPI0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDRFE:HFXTSTAT

Address Offset 0x0000 0028
Physical Address 0x4008 3028 Instance 0x4008 3028
Description HFXT Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT HFXT RF qualification
Value ENUM Name Description
0x0 NONQUAL Clock signal is not qualified
0x1 QUAL Clock signal is qualified
RO 0

TOP:LRFDRFE:RFSTATE

Address Offset 0x0000 0030
Physical Address 0x4008 3030 Instance 0x4008 3030
Description RF State
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Radio Status
Value ENUM Name Description
0x0 IDLE Radio is idle
0x1 SYNTH Synth is running
0x2 TX TX is active
0x3 RX RX is active
RW 0x0

TOP:LRFDRFE:API

Address Offset 0x0000 0048
Physical Address 0x4008 3048 Instance 0x4008 3048
Description API
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 PROTOCOLID Protocol ID
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0
3:0 RFECMD RFE Command
Value ENUM Name Description
0x0 ALLZEROS All bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE:CMDPAR0

Address Offset 0x0000 004C
Physical Address 0x4008 304C Instance 0x4008 304C
Description Command Parameter 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:CMDPAR1

Address Offset 0x0000 0050
Physical Address 0x4008 3050 Instance 0x4008 3050
Description Command Parameter 1
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:MSGBOX

Address Offset 0x0000 0054
Physical Address 0x4008 3054 Instance 0x4008 3054
Description Message Box For Command Status
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL RFE status as responser to API execution.

Field is readable to PBE in LRFDPBE:RFEMSGBOX.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:MCEDATOUT0

Address Offset 0x0000 0058
Physical Address 0x4008 3058 Instance 0x4008 3058
Description RFE-to-MCE Data Out 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data to send to MCE.

Write VAL to send data to MCE. A write triggers an LRFDMDM:EVT0.RFEDAT event in MCE. MCE reads VAL in LRFDMDM:RFEDATIN0.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:MCEDATIN0

Address Offset 0x0000 005C
Physical Address 0x4008 305C Instance 0x4008 305C
Description MCE-to-RFE Data In 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data received from MCE.

Read data that MCE writes to LRFDMDM:RFEDATAOUT0. A write to LRFDMDM:RFEDATAOUT0 sets EVT0.MDMRFEDAT event.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:MCECMDOUT

Address Offset 0x0000 0060
Physical Address 0x4008 3060 Instance 0x4008 3060
Description RFE-to-MCE Command
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command to send to the MCE.

A write to this register tiggers LRFDMDM:EVT1.RFECMD MCE event, and the command becomes readable to MCE in LRFDMDM:RFECMDIN.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDRFE:MCECMDIN

Address Offset 0x0000 0064
Physical Address 0x4008 3064 Instance 0x4008 3064
Description MCE-to-RFE Command
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command received from MCE.

MCE writes LRFDMDM:RFECMDOUT to send a command to RFE. This action sets EVT0.MDMCMD RFE event. RFE reads command from MCECMDIN.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE:PBEDATOUT0

Address Offset 0x0000 0068
Physical Address 0x4008 3068 Instance 0x4008 3068
Description RFE-to-PBE Data Out 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data to send to PBE.

Write VAL to send data to PBE. A write triggers an LRFDPBE:EVT0.RFEDAT event in PBE. PBE reads VAL in LRFDPBE:RFEDATIN0.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:PBEDATIN0

Address Offset 0x0000 006C
Physical Address 0x4008 306C Instance 0x4008 306C
Description PBE-to-RFE Data In 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data received from PBE.

Read data that PBE writes to LRFDPBE:RFEDATAOUT0. A write to LRFDPBE:RFEDATAOUT0 sets EVT0.PBERFEDAT event.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:PBECMDOUT

Address Offset 0x0000 0070
Physical Address 0x4008 3070 Instance 0x4008 3070
Description RFE-to-PBE Command
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command to send to the PBE.

A write to this register tiggers LRFDPBE:EVT0.RFECMD PBE event, and the command becomes readable to PBE in LRFDPBE:RFECMDIN.


Command to send to the PBE. Writing to this register will trigger an event in the PBE, and the command value written here will be readable in LRFDPBE:RFECMDIN register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDRFE:PBECMDIN

Address Offset 0x0000 0074
Physical Address 0x4008 3074 Instance 0x4008 3074
Description PBE-to-RFE Command
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command received from PBE.

PBE writes LRFDPBE:RFECMDOUT to send a command to RFE. This action sets EVT0.PBECMD RFE event. RFE reads command from PBECMDIN.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE:STRB

Address Offset 0x0000 0078
Physical Address 0x4008 3078 Instance 0x4008 3078
Description RFE FW Strobe

RFE writes register to trigger events towards System CPU, DMA, SYSTIM, or LRFDS2R module within the modem. You need to configure LRFDDBELL to route events to System CPU, DMA, or SYSTIM.
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 S2RTRG LRFDS2R arm/trigger
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 DMATRG DMA transfer trigger
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 SYSTCPT2 Systimer capture event 2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 SYSTCPT1 Systimer capture event 1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 SYSTCPT0 Systimer capture event 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 EVT1 Event 1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 EVT0 Event 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 CMDDONE Command done indication
Value ENUM Name Description
0x0 NO The bit is 0
0x1 YES The bit is 1
WO 0

TOP:LRFDRFE:MAGNTHRCFG

Address Offset 0x0000 0080
Physical Address 0x4008 3080 Instance 0x4008 3080
Description Magnitude Threshold Configuration

Register controls automatic comparison of magnitude with threshold.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 SEL Selects what MAGNACC is used in the compare with the threshold in MAGNTHR.
Value ENUM Name Description
0x0 MAGNACC0 Use MAGNACC0 in the compare against the theshold in MANGTHR
0x1 MAGNACC1 Use MAGNACC1 in the compare against the theshold in MANGTHR
RW 0
0 CTL Controls automatic comparison of magnitude with threshold
Value ENUM Name Description
0x0 DIS Disable automatic comparison with threshold (input of lin2log is driven by FW)
0x1 EN Enable automatic comparison of magntude with threshold (input of lin2log is driven by HW)
RW 0

TOP:LRFDRFE:MAGNTHR

Address Offset 0x0000 0084
Physical Address 0x4008 3084 Instance 0x4008 3084
Description Magnitude Threshold

Threshold to compare with magnitude accumulator amplitude.
MAGNTHRCFG selects accumulator to use for the compare operation.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Magnitude threshold value
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:RSSIOFFSET

Address Offset 0x0000 0088
Physical Address 0x4008 3088 Instance 0x4008 3088
Description RSSI Offset
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Offset to convert to dBm (unsigned). This is used by the RFE to adjust its RSSI calculations.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:GAINCTL

Address Offset 0x0000 008C
Physical Address 0x4008 308C Instance 0x4008 308C
Description Gain Control
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:2 BDE2DVGA DVGA settings for BDE2.

The DVGA control for BDE2 is shared with the MCE in its LRFDMDM:DEMMISC3.BDE2DVGA field.
Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
Value ENUM Name Description
0x0 GAIN1 Gain 1
0x1 GAIN2 Gain 2
0x2 GAIN4 Gain 4
0x3 GAIN8 Gain 8
RW 0b00
1:0 BDE1DVGA DVGA settings for BDE1.

The DVGA control for BDE1 is shared with the MCE in its LRFDMDM:DEMMISC3.BDE1DVGA field.
Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
Value ENUM Name Description
0x0 GAIN1 Gain 1
0x1 GAIN2 Gain 2
0x2 GAIN4 Gain 4
0x3 GAIN8 Gain 8
RW 0b00

TOP:LRFDRFE:MAGNCTL0

Address Offset 0x0000 0090
Physical Address 0x4008 3090 Instance 0x4008 3090
Description Magnitude Control 0

This register contains settings for magnitude estimation.
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 PERMODE Measurement type
Value ENUM Name Description
0x0 ONESHOT One-shot mode
0x1 PERIODIC Periodic mode
RW 0
11:8 SCL Scaling factor

Scaling factor = 1/2^(SCL).
Value ENUM Name Description
0x0 DIV1 1/1 (no scaling)
0x1 DIV2 1/2
0x2 DIV4 1/4
0x3 DIV8 1/8
0x4 DIV16 1/16
0x5 DIV32 1/32
0x6 DIV64 1/64
0x7 DIV128 1/128
0x8 DIV256 1/256
RW 0x0
7:0 PER Accumulation period in incoming samples
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:MAGNCTL1

Address Offset 0x0000 0094
Physical Address 0x4008 3094 Instance 0x4008 3094
Description Magnitude Control 1

This register contains settings for magnitude estimation.
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 PERMODE Measurement type
Value ENUM Name Description
0x0 ONESHOT One-shot mode
0x1 PERIODIC Periodic mode
RW 0
11:8 SCL Scaling factor

Scaling factor = 1/2^(SCL).
Value ENUM Name Description
0x0 DIV1 1/1 (no scaling)
0x1 DIV2 1/2
0x2 DIV4 1/4
0x3 DIV8 1/8
0x4 DIV16 1/16
0x5 DIV32 1/32
0x6 DIV64 1/64
0x7 DIV128 1/128
0x8 DIV256 1/256
RW 0x0
7:0 PER Accumulation period in incoming samples
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:SPARE0

Address Offset 0x0000 0098
Physical Address 0x4008 3098 Instance 0x4008 3098
Description Spare Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:SPARE1

Address Offset 0x0000 009C
Physical Address 0x4008 309C Instance 0x4008 309C
Description Spare Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:SPARE2

Address Offset 0x0000 00A0
Physical Address 0x4008 30A0 Instance 0x4008 30A0
Description Spare Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:SPARE3

Address Offset 0x0000 00A4
Physical Address 0x4008 30A4 Instance 0x4008 30A4
Description Spare Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:SPARE4

Address Offset 0x0000 00A8
Physical Address 0x4008 30A8 Instance 0x4008 30A8
Description Spare Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:SPARE5

Address Offset 0x0000 00AC
Physical Address 0x4008 30AC Instance 0x4008 30AC
Description Spare Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:LNA

Address Offset 0x0000 00B0
Physical Address 0x4008 30B0 Instance 0x4008 30B0
Description LNA Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SPARE Spare bits to analog reserved for future use
Value ENUM Name Description
0x0 DIS Disable IFAMP
0x1 EN Enable IFAMP
RW 0x00
7:4 TRIM LNA trim
Value ENUM Name Description
0x0 ZEROS All bits are zero
0xF ONES All bits are one
RW 0x0
3 BIAS BIAS current selection
Value ENUM Name Description
0x0 BGAP IPTAT bias currents are from bandgap
0x1 INT IPTAT bias currents are from bias circuit inside LRF_FRONTEND
RW 0
2:1 IB LNA bias current control

IB is trimmed at probe. Default is 1.
Value ENUM Name Description
0x0 MIN Minimum IB
0x3 MAX Maximum IB
RW 0b00
0 EN LNA enable
Value ENUM Name Description
0x0 OFF Disable LNA
0x1 ON Enable LNA
RW 0

TOP:LRFDRFE:IFAMPRFLDO

Address Offset 0x0000 00B4
Physical Address 0x4008 30B4 Instance 0x4008 30B4
Description IFAMPRFLDO Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:9 TRIM RFLDO output voltage trim

Default value: 84 (1.3V), 127 = Bypass.
Value ENUM Name Description
0x0 MIN Minimum output voltage
0x7E MAX Maximum output voltage
0x7F BYPASS Regulator is in bypass mode
RW 0b000 0000
8 EN Regulator enable
Value ENUM Name Description
0x0 DIS Disable regulator
0x1 EN Enable regulator
RW 0
7:4 AAFCAP AAF capacitor control
Value ENUM Name Description
0x0 MIN Smallest capacitance on IFAMP output. High BW.
0xF MAX Largest capacitance on IFAMP output. Low BW
RW 0x0
3:1 IFAMPIB IFAMP bias current control

Default is 2.
Value ENUM Name Description
0x0 MIN Minimum IB
0x7 MAX Max IB
RW 0b000
0 IFAMP IFAMP enable
Value ENUM Name Description
0x0 DIS Disable IFAMP
0x1 EN Enable IFAMP
RW 0

TOP:LRFDRFE:PA0

Address Offset 0x0000 00B8
Physical Address 0x4008 30B8 Instance 0x4008 30B8
Description PA Control 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 SPARE15 Reserved
Value ENUM Name Description
0x0 ZERO Bit is 0
0x1 ONE Bit is one
RW 0
14 MODE PA power mode
Value ENUM Name Description
0x0 LOW Low power mode, max 3 dBm
0x1 HIGH High power mode, max 8 dBm
RW 0
13:11 GAIN Gain control in 8dBm PA 1st stage
Value ENUM Name Description
0x0 MIN Minimum gain
0x7 MAX Maximum gain
RW 0b000
10:5 IB PA power control
Value ENUM Name Description
0x0 MIN Minimum output power
0x3F MAX Maximum output power
RW 0b00 0000
4:0 TRIM Bias Current Trim

Setting shall provide constant output power over process and temperature. Current changes linearily with setting.

Default value: 16
Value ENUM Name Description
0x0 MIN Minimum bias current
0x1F MAX Maximum bias current
RW 0b0 0000

TOP:LRFDRFE:PA1

Address Offset 0x0000 00BC
Physical Address 0x4008 30BC Instance 0x4008 30BC
Description PA Control 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:7 SPARE Spare bits to analog, reserved for future use.
Value ENUM Name Description
0x0 MIN Shortest ramp time
0x3 MAX Longest ramp time
RW 0b0 0000 0000
6 MIXATST Control of mixer outputs through ATEST
Value ENUM Name Description
0x0 DIS Mixers are not available on ATEST
0x1 EN Mixers are available on ATEST
RW 0
5 LDOITST Control of current test signal through ITEST
Value ENUM Name Description
0x0 DIS Current test signal not available through ITEST
0x1 EN Current test signal is available through ITEST
RW 0
4 LDOATST Control of LDO output voltage through ATEST
Value ENUM Name Description
0x0 DIS LDO output voltage not available through ATEST
0x1 EN LDO output voltage is available through ATEST
RW 0
3:2 RC Adjustment of on/off PA ramp time.
Value ENUM Name Description
0x0 MIN Shortest ramp time
0x3 MAX Longest ramp time
RW 0b00
1 RAMP PA RAMP control

Field can be set together with EN to ramp PA on.
Field must be cleared before EN to ramp PA down.
Value ENUM Name Description
0x0 DOWN Ramp down
0x1 UP Ramp up
RW 0
0 EN PA enable
Value ENUM Name Description
0x0 DIS Disable PA
0x1 EN Enable PA
RW 0

TOP:LRFDRFE:ULNA

Address Offset 0x0000 00C0
Physical Address 0x4008 30C0 Instance 0x4008 30C0
Description ULNA Control

TRX only
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SPARE Reserved for future use
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:IFADC0

Address Offset 0x0000 00C4
Physical Address 0x4008 30C4 Instance 0x4008 30C4
Description IFADC Configuration 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 EXTCLK IFADC external clock control

IFADC can use external clock from pad.
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
14:12 DITHERTRIM Dither current trim
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x7 ONES All the bits are 1
RW 0b000
11:10 DITHEREN Dither control

Enable a random noise generator to inject weak pseudo random noise into the ADC loop to randomize and smooth out possible idle tones.
NOTE: This field may only change during DTC-reset or while the clock is inactive!
Value ENUM Name Description
0x0 DIS All the bits are 0
0x1 ENS All the bits are 1
0x2 ENSD All the bits are 1
0x3 ENG All the bits are 1
RW 0b00
9 ADCIEN I modulator control
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 ADCQEN Q modulator control
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7:4 INT2ADJ GM trim

Trims the gm cell for the second integrator. Larger value means lower gm.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
3:2 AAFCAP AAF bandwidth trim
Value ENUM Name Description
0x0 DIS All the bits are 0
0x1 ENS All the bits are 1
0x2 ENSD All the bits are 1
0x3 ENG All the bits are 1
RW 0b00
1:0 RESERVED Reserved
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x3 ONES All the bits are 1
RW 0b00

TOP:LRFDRFE:IFADC1

Address Offset 0x0000 00C8
Physical Address 0x4008 30C8 Instance 0x4008 30C8
Description IFADC Configuration 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 NRZ Internal feedback DAC mode
Value ENUM Name Description
0x0 DIS The feedback DAC uses RZ mode
0x1 EN The feedback DAC uses NRZ mode. (Default)
RW 0
14:9 TRIM Feedback DAC trim

Larger trim means larger current.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x3F ONES All the bits are 1
RW 0b00 0000
8 RESERVED8 Enable the Q modulator
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 RSTN IFADC DTC reset
Value ENUM Name Description
0x0 EN DTCs are reset
0x1 DIS DTCs are not reset
RW 0
6 CLKGEN IFADC clock generator
Value ENUM Name Description
0x0 DIS Internal clock generator module is disabled
0x1 EN Internal clock generator module is enabled
RW 0
5 ADCDIGCLK IFADC clock to decimator
Value ENUM Name Description
0x0 DIS Clock to decimator disabled
0x1 EN Clock to decimator enabled
RW 0
4 ADCLFSROUT ADC test mode
Value ENUM Name Description
0x0 DIS The quantizer output is connected to the ADC output
0x1 EN The LFSR test output is connected to the ADC output
RW 0
3:1 LPFTSTMODE Currently not in use. For future test mode implementations.
Value ENUM Name Description
0x0 DIS All the bits are 0
0x1 EN All the bits are 1
RW 0b000
0 INVCLKOUT Control phase inversion of IFADC clock output
Value ENUM Name Description
0x0 DIS Keep default IFADC output clock phase
0x1 EN Invert IFADC output clock phase (default)
RW 0

TOP:LRFDRFE:IFADCLF

Address Offset 0x0000 00CC
Physical Address 0x4008 30CC Instance 0x4008 30CC
Description IFADC Loop Filter
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:12 FF3 GM trim for the third feedforward cell

Larger trim means lower gm.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
11:8 FF2 GM trim for the second feedforward cell

Larger trim means lower gm.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
7:4 FF1 GM trim for the first feedforward cell

Larger trim means lower gm.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0
3:0 INT3 GM trim for the third integrator

Larger trim means lower gm.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0xF ONES All the bits are 1
RW 0x0

TOP:LRFDRFE:IFADCQUANT

Address Offset 0x0000 00D0
Physical Address 0x4008 30D0 Instance 0x4008 30D0
Description IFADC Quantizer
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 CLKDLYTRIM Currently not in use. 2 bit signal to program the clock delay in the clock generator circuit.
Value ENUM Name Description
0x0 ZEROS All the bits are zero
0x3 ONES All the bits are one
RW 0b00
13:9 DBGCALVALIN Input test calibration value to quantizer calibration block, used in debug mode.
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x1F ONES All the bits are ONES
RW 0b0 0000
8 DBGCALLEG Select which leg to observe in calibration debug mode
Value ENUM Name Description
0x0 POS Positive leg
0x1 NEG Negative leg
RW 0
7:6 DBGCALMQ Quantizer calibration mode for Q modulator

This signal should have a large stability window, and is for internal use only!
Value ENUM Name Description
0x0 DBGCAL_QMODZ Disable quantizer calibration mode.(Default)
0x1 DBGCAL_QMODN Enable quantizer calibration mode for Negative comparator in Q modulator.
0x2 DBGCAL_QMODP Enable quantizer calibration mode for Positive comparator in Q modulator.
0x3 DBGCAL_QMODB UNCLEAR_Enable quantizer calibration mode.
RW 0b00
5:4 DBGCALMI Quantizer calibration mode for I modulator.

This signal should have a large stability window, and is for internal use only!
Value ENUM Name Description
0x0 DBGCAL_IMODZ Disable quantizer calibration mode.(Default)
0x1 DBGCAL_IMODN Enable quantizer calibration mode for Negative comparator in I modulator.
0x2 DBGCAL_IMODP Enable quantizer calibration mode for Positive comparator in I modulator.
0x3 DBGCAL_IMODB UNCLEAR_Enable quantizer calibration mode.
RW 0b00
3 AUTOCAL Auto calibration
Value ENUM Name Description
0x0 DIS Disable the auto calibration logic
0x1 EN Enable the auto calibration logic (Default)
RW 0
2:0 QUANTTHR Quantizer treshold voltage trim
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x7 ONES All the bits are 1
RW 0b000

TOP:LRFDRFE:IFADCALDO

Address Offset 0x0000 00D4
Physical Address 0x4008 30D4 Instance 0x4008 30D4
Description IFADC Analog LDO Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 ATESTVSSANA Connect VSSANA to atest
Value ENUM Name Description
0x0 DIS Not connected
0x1 EN Connected
RW 0
14 RESERVED Reserved for future use
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x1 ONES All the bits are ONES
RW 0
13:8 TRIMOUT Select which leg to observe in calibration debug mode
Value ENUM Name Description
0x0 ZEROS All the bits are zero
0x3F ONES All the bits are one
RW 0b00 0000
7 DUMMY Enable dummy load to improve performance for low load currents
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
6 ATESTOUT Connect LDO output voltage to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
5 ATSTLDOFB Connect LDO feedback to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
4 ATESTERRAMP Connect the error amplifier output to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
3 ITEST Connect test current to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
2 BYPASS Bypass LDO and short LDO output with vddana1p5v. The LDO needs to be enabled to use bypass.
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
1 CLAMP Clamp the LDO output with diodes to ground

Not used by analog when CTL or BYPASS are set.
Value ENUM Name Description
0x0 DIS Disabled. The LDO output is shorted to ground when disabled.
0x1 EN Enabled
RW 0
0 CTL Enable regulator for supplying analog domain of the adc
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0

TOP:LRFDRFE:IFADCDLDO

Address Offset 0x0000 00D8
Physical Address 0x4008 30D8 Instance 0x4008 30D8
Description IFADC Digital LDO Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 RESERVED Reserved for future use
Value ENUM Name Description
0x0 ZEROS All the bits are 0
0x3 ONES All the bits are ONES
RW 0b00
13:8 TRIMOUT Select which leg to observe in calibration debug mode
Value ENUM Name Description
0x0 ZEROS All the bits are zero
0x3F ONES All the bits are one
RW 0b00 0000
7 DUMMY Enable dummy load to improve performance for low load currents
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
6 ATESTOUT Connect LDO output voltage to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
5 ATSTBGP Connect bandgap voltage to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
4 ATESTERRAMP Connect the error amplifier output to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
3 ITEST Connect test current to ATEST
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
2 BYPASS Bypass LDO and short LDO output with vddana1p5v. The LDO needs to be enabled to use bypass.
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
1 CLAMP Clamp the LDO output with diodes to ground

Not used by analog when CTL or BYPASS are set.
Value ENUM Name Description
0x0 DIS Disabled. The LDO output is shorted to ground when disabled.
0x1 EN Enabled
RW 0
0 CTL Enable regulator for supplying digital domain of the adc
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0

TOP:LRFDRFE:IFADCTST

Address Offset 0x0000 00DC
Physical Address 0x4008 30DC Instance 0x4008 30DC
Description IFADC Test Configuration
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 EXTCURR Drive an external current
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
6 QCALDBIQ Comparator select for calibration data output

Also look at the description of IFADCQUANT.
Value ENUM Name Description
0x0 COMP0 Q Comparator
0x1 COMP1 I comparator
RW 0
5 QCALDBC Select which quantizer comparator to mux out calibration data from
Value ENUM Name Description
0x0 COMP0 Q Comparator
0x1 COMP1 I comparator
RW 0
4:0 SEL Select which internal net to probe via atb. This bus goes to a 6-32 bit decoder.
Value ENUM Name Description
0x0 NONE ADC_TEST_P and ADC_TEST_N tristated (Default)
0x1F EXTCLKN1 External ADC clock through ADC_TEST_N (N1 internally). The the clock should be a 200MHz sine wave (it is divided internally to 100MHz).
RW 0b0 0000

TOP:LRFDRFE:ATSTREFL

Address Offset 0x0000 00E0
Physical Address 0x4008 30E0 Instance 0x4008 30E0
Description Analog Test Low
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 MUXLSB ATEST mux 0 control
Value ENUM Name Description
0x0 DIS No atest selected
0x1 FE_OUTIP Frontend IF outip, voltage
0x2 FE_OUTIN Frontend IF outin, voltage
0x4 FE_OUTQP Frontend IF outqp, voltage
0x8 FE_OUTQN Frontend IF outqn, voltage
0x10 FE_OUTIP_2 Frontend IF outip, voltage
0x20 FE_OUTIN_2 Frontend IF outin, voltage
0x40 MIX_OUTIP MIX outip, voltage
0x80 MIX_OUTIN MIX outin, voltage
0x100 MIX_OUTQP MIX outqp, voltage
0x200 MIX_OUTQN MIX outqn, voltage
0x400 PA_PEAK_OUTP PA peak detector output p
0x800 PA_PEAK_OUTN PA peak detector output n
0x2000 LDO_ITEST LDO_ITEST itest out, current
0x4000 LDO_VTEST LDO_VTEST vtest out, current
0x8000 IFADC_ATB IFADC ATB
RW 0x0000

TOP:LRFDRFE:ATSTREFH

Address Offset 0x0000 00E4
Physical Address 0x4008 30E4 Instance 0x4008 30E4
Description Analog Test High
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 VREFBPDIS Bandgap reference bypass control
Value ENUM Name Description
0x0 BPEN Bandgap reference bypass enabled.
0x1 BPDIS Bandgap reference bypass disabled
RW 0
14:10 IREFTRIM LRF bias current trim
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x1F ONES All bits are ones
RW 0b0 0000
9 BIAS LRF reference system control
Value ENUM Name Description
0x0 DIS Disabled
0x1 EN Enabled
RW 0
8 OUTPUT2 ATEST output 2 control
Value ENUM Name Description
0x0 DIS Output is disabled
0x1 EN The output is enabled
RW 0
7 OUTPUT1 ATEST output 1 control
Value ENUM Name Description
0x0 DIS Output is disabled
0x1 EN The output is enabled
RW 0
6:0 MUXMSB ATEST mux 2 control
Value ENUM Name Description
0x0 DIS No atest selected
0x1 IFADC_ATB IFADC ATB
0x4 REFSYS_IREF REFSYS 4 uA output
0x8 DIVBUF_PMOS_BIAS DIVBUF DC bias voltage for pmos switches
0x10 DIVBUF_NMOS_BIAS DIVBUF DC bias voltage for nmos switches
RW 0b000 0000

TOP:LRFDRFE:DCO

Address Offset 0x0000 00E8
Physical Address 0x4008 30E8 Instance 0x4008 30E8
Description DCO

Register holds DCO control and spare bits for analog.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:9 MTDCSPARE Spare bits to MTDC
Value ENUM Name Description
0x0 EN DIVIDER = 2
0x1 DIS DIVIDER = 4 (for test purposes only)
RW 0b00
8:7 SPARE7 Spare
Value ENUM Name Description
0x0 ZERO Bit is zero
0x1 ONE Bit is one
RW 0b00
6:3 TAILRESTRIM Trim bits to set DCO-amplitude.

0x0: Disable DCO
0x1: Min DCO amplitude (min-current)
0xF: Max DCO amplitude (max current)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
2 RTRIMCAP RTRIM resistor cap control

Field enables cap across RTRIM resistor. This can improve phase-noise in some conditions, but can also result in DCO-instability (Not used).
Value ENUM Name Description
0x0 DIS Disable(default)
0x1 EN Enable
RW 0
1 CNRCAP Corner-lots frequency tuning control
Value ENUM Name Description
0x0 DEFAULT Default
0x1 _50MHZ 50 MHz
RW 0
0 CRSCAPCM Coarse cap common mode control
Value ENUM Name Description
0x0 DEFAULT Default
0x1 REDUCED Reduced common mode for greater reliability
RW 0

TOP:LRFDRFE:DIV

Address Offset 0x0000 00EC
Physical Address 0x4008 30EC Instance 0x4008 30EC
Description LO Divider
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 PDET Adds 50mV to PM and NM bias voltages
Value ENUM Name Description
0x0 DIS Peak detector mode disabled, normal functional mode
0x1 EN Peak detektor mode enabled, used in production test
RW 0
14:12 NMIREFTRIM Trim code for NMOS-Bias Voltage in the divider.

0x0: Min Speed
0x7: Max Speed

Default value: 0x4
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000
11:9 PMIREFTRIM Trim code for PMOS-Bias Voltage in the divider.

0x0: Min Speed
0x7: Max Speed

Default value: 0x4
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000
8 TXBBOOST Not connected
Value ENUM Name Description
0x0 DEFAULT Default drive strength
0x1 INCREASED High drive strength
RW 0
7 S1GFRC Not connected
Value ENUM Name Description
0x0 DIS Disable force S1G power switch
0x1 EN Enable force S1G power switch
RW 0
6:5 BUFGAIN Not connected
Value ENUM Name Description
0x0 MAX Maximum gain (default)
0x1 _80_PST 80% of maximum gain
0x2 DONT_USE Same as _80_PST
0x3 _60_PST 60% of maximum gain
RW 0b00
4 BIAS Not connected
Value ENUM Name Description
0x0 ALTERNATIVE Alternative bias (for test purposes)
0x1 DEFAULT Default bias
RW 0
3 OUT Divider output

Enable divider outputs to either sub-1GHz front-end or to 2.4 GHz front-end when any of the following equals ENABLE:
- DIVCTL.RXPH0DIV
- DIVCTL.RXPH90DIV
- DIVCTL.TXPH0DIV
- DIVCTL.TXPH180DIV
Value ENUM Name Description
0x0 FE_S1G Enable outputs going to sub-1GHz front-end
0x1 FE_2G4 Enable outputs going to 2.4GHz front-end
RW 0
2:0 RATIO Divider ratio

Field sets the divider ratio between DCO frequency, FDCO, and radio frequency, FRF.

FRF = FDCO / DIVIDER
Value ENUM Name Description
0x0 DIV2 DIVIDER = 2
0x1 DIV4 DIVIDER = 4 (for test purposes only)
0x2 DIV6 DIVIDER = 6
0x3 DIV12 DIVIDER = 12
0x4 DIV5 DIVIDER = 5
0x5 DIV10 DIVIDER = 10
0x6 DIV15 DIVIDER = 15
0x7 DIV30 DIVIDER = 30
RW 0b000

TOP:LRFDRFE:DIVLDO

Address Offset 0x0000 00F0
Physical Address 0x4008 30F0 Instance 0x4008 30F0
Description Divider LDO Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 SPARE15 Spare bit
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x1 ONES All bits are one
RW 0
14:8 VOUTTRIM VOUT trim code
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x7F ONES All bits are one
RW 0b000 0000
7 ITST ITEST block control
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0
6:4 TMUX TMUX control bits
Value ENUM Name Description
0x0 OFF Normal mode
0x1 GND ATEST output is grounded
0x2 LDO_OUT ATEST output is LDO output
0x4 VDDR ATEST output is VDDR
RW 0b000
3 SPARE3 Spare bit
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
2 MODE High BW operation control
Value ENUM Name Description
0x0 NORM Regular low bandwidth of LDO
0x1 FAST Regulator in high bandwidth mode
RW 0
1 BYPASS Regulator bypass
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
0 CTL Regulator control
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0

TOP:LRFDRFE:TDCLDO

Address Offset 0x0000 00F4
Physical Address 0x4008 30F4 Instance 0x4008 30F4
Description TDC LDO Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 ITESTCTL ITEST control

When enabled, it is possible to check current thorugh PASSFET. Scaled down 110:1
Value ENUM Name Description
0x0 DIS ITEST Disabled
0x1 EN ITEST enabled
RW 0
14:8 VOUTTRIM VOUT trim code
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x7F ONES All bits are one
RW 0b000 0000
7 ITESTBUFCTL ITEST BUFF block control

When enabled, it is possible to check current through buffer, scaled down 12:1.
Value ENUM Name Description
0x0 DIS ITEST mode in buffer is disabled
0x1 EN ITEST mode in buffer is enabled
RW 0
6:4 TMUX TMUX control bits
Value ENUM Name Description
0x0 OFF Normal mode
0x1 VDDA ATEST output is VDDA
0x2 LDO_OUT ATEST output is LDO output
0x4 VSSA ATEST output is VSSA
RW 0b000
3 PDSEL Selects between resistor or diode stack PD
Value ENUM Name Description
0x0 R R (default)
0x1 DIODE Diode stack
RW 0
2 MODE High BW operation control

Increase BW of slow loop (by increasing quiescent current).
Value ENUM Name Description
0x0 NORM Regular low bandwidth of LDO
0x1 FAST Regulator in high bandwidth mode
RW 0
1 BYPASS Regulator bypass
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
0 CTL Regulator control
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0

TOP:LRFDRFE:DCOLDO0

Address Offset 0x0000 00F8
Physical Address 0x4008 30F8 Instance 0x4008 30F8
Description DCO LDO Control 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 ITST ITEST block control
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 FIRST Enable first pass transistor
0x2 SECOND Enable second pass transistor
0x3 BOTH Enable both pass transistors
RW 0b00
13:8 SECONDTRIM Trim for second LDO
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x3F ONES All bits are one
RW 0b00 0000
7:4 FIRSTTRIM TRIM for first LDO
Value ENUM Name Description
0x0 ZEROS All bits are zero
0xF ONES All bits are one
RW 0x0
3 PDN Pulldown control
Value ENUM Name Description
0x0 DIS No Pulldown
0x1 EN Pulldown
RW 0
2 BYPFIRST Bypass first regulator
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
1 BYPBOTH Bypass LDO (both)
Value ENUM Name Description
0x0 DIS No bypass
0x1 EN Regulator is bypassed
RW 0
0 CTL Regulator control
Value ENUM Name Description
0x0 DIS Regulator is disabled
0x1 EN Regulator is enabled
RW 0

TOP:LRFDRFE:DCOLDO1

Address Offset 0x0000 00FC
Physical Address 0x4008 30FC Instance 0x4008 30FC
Description DCO LDO Control 1
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 REFSRC Select clock source to PLL
Value ENUM Name Description
0x0 XTAL PLL clock source is XTAL
0x1 BAW PLL clock source is BAW
RW 0
9:8 DIVATST Divider ATEST control
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x3 ONES All bits are one
RW 0b00
7 PERFM Performance mode control

When enabled, the LDO uses more current to reduce flicker noise.
Value ENUM Name Description
0x0 DIS Disabled (normal)
0x1 EN Enabled (performance)
RW 0
6 CHRGFILT Charge the filters
Value ENUM Name Description
0x0 DIS Charging disabled, normal operation
0x1 EN Charging enabled
RW 0
5:0 ATST ATEST block control
Value ENUM Name Description
0x0 LDO_OUT LDO output
0x1 FIRST_OUT First LDO output
0x20 VSSANA VSSANA
RW 0b00 0000

TOP:LRFDRFE:PRE0

Address Offset 0x0000 0100
Physical Address 0x4008 3100 Instance 0x4008 3100
Description Predivider Configuration 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 SPARE14 SPARE14
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
13:8 PLLDIV1 PLL reference frequency divider 1

The value of DLOCTL0.LOOPUPD decides if this reference frequency is used.

FREFCLK = FXTAL / PLLDIV1

Examples:
0: Illegal setting
1: Illegal setting
2: Divide by 2
...
63: Divide by 63

FREFCLK must be higher than or equal to 1 MHz in closed-loop state.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7:6 SPARE6 SPARE6
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
5:0 PLLDIV0 PLL reference frequency divider 0

The value of DLOCTL0.LOOPUPD decides if this reference frequency is used.

FREFCLK = FXTAL / PLLDIV0

Examples:
0: Illegal setting
1: Illegal setting
2: Divide by 2
...
63: Divide by 63

FREFCLK must be higher than or equal to 1 MHz in closed-loop state.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDRFE:PRE1

Address Offset 0x0000 0104
Physical Address 0x4008 3104 Instance 0x4008 3104
Description Predivider Configuration 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 IIRBW Loop IIR filter bandwidth
Value ENUM Name Description
0x0 K2 K=2
0x1 K4 K=4
0x2 K8 K=8
0x3 K16 K=16
RW 0b00
13 IIRORD IIR order
Value ENUM Name Description
0x0 FIRST Select first order IIR filter
0x1 SECOND Select second order IIR filter
RW 0
12:8 IIRDIV IIR divider

FIIRCLK = FCKVD64 / (IIRDIV+1)

Examples:

0: Clock is ckvd64/1
1: Clock is ckvd64/2
...
31: Clock is ckvd64/32
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 CALHSDDC TDC calibration setting for HSDDC
Value ENUM Name Description
0x0 NOGATE No duty-cycling
0x1 GATE Duty-cycling given by HSDDC
RW 0
5:0 HSDDC TDC high-speed digital duty cycle

The TDC high-speed clock can always run or be duty cycled to save current consumption. The minimum ON-time equals the reference clock source period (PER). In this case, the clock starts to toggle 1/2 * PER before positive edge of reference clock. If the clock runs for two periods, it starts to toggle 1.5 * PER before the positve edge of the reference clock. In any case, it toggles during the high time of reference clock source.

The field value must not be set higher than the minimum binary value of the active reference clock divider.

Encoding:
0: Enable clock to TDC always
1: Enable clock to TDC always
2: Enable clock to TDC for 1 PER
3. Enable clock to TDC for 2 PER
...
63: Enable clock to TDC for 62 PER
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDRFE:PRE2

Address Offset 0x0000 0108
Physical Address 0x4008 3108 Instance 0x4008 3108
Description Predivider Configuration 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:12 MIDCALDIVLSB Mid calibration divider LSB

This field determines the reference frequency used during the mid SAR calibration stages, according to:

FREFCLK = FXTAL / MIDCALDIV

Field encoding is unsigned integer:
0-7: Illegal setting
8: Divide by 8
9: Divide by 9
..
1023: Divide by 1023
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
11:6 CRSCALDIV Coarse calibration divider

This field determines the reference frequency used during the coarse SAR calibration stages, according to:

FREFCLK = FXTAL / CRSCALDIV

Field encoding is unsigned integer:
0-7: Illegal setting
8: Divide by 8
9: Divide by 9
..
63: Divide by 63
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
5:0 FSMDIV FSM divider

This field determines the clock frequency for FSM traversal through states that does not affect calibration, according to:

FFSM = FXTAL / FSMDIV

Field encoding is unsigned integer:
0-3: Illegal setting
4: Divide by 4
5: Divide by 5
..
63: Divide by 63
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDRFE:PRE3

Address Offset 0x0000 010C
Physical Address 0x4008 310C Instance 0x4008 310C
Description Predivider Configuration 3
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:5 FINECALDIV Fine calibration divider

This field determines the reference frequency used to measure the DCO gain (KDCO), according to:

FREFCLK = FXTAL / FINECALDIV

Field encoding is unsigned integer:
0-7: Illegal setting
8: Divide by 8
9: Divide by 9
..
4095: Divide by 4095

Use a lower reference frequency to increases the KDCO estimation accuracy at the cost of increased calibration time. The KDCO estimation takes approximately 2 periods of the configured frequency.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7FF ALLONES All the bits are 1
RW 0b000 0000 0000
4:0 MIDCALDIVMSB Mid calibration divider MSB

This field determines the reference frequency used during the mid SAR calibration stages, according to:

FREFCLK = FXTAL / MIDCALDIV

Field encoding is unsigned integer:
0-7: Illegal setting
8: Divide by 8
9: Divide by 9
..
1023: Divide by 1023
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000

TOP:LRFDRFE:CAL0

Address Offset 0x0000 0110
Physical Address 0x4008 3110 Instance 0x4008 3110
Description Calibration Configuration 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 SPARE15 SPARE15
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
14:8 FCSTART Fine code start

Fine code applied to DCO during all calibration states except during KDCO estimation. The start code is then applied to DCO at start of phase aquisition in state PLL_ST. Ensure that value is the aritmetic mean of CAL1.FCBOT and CAL1.FCTOP.

Field encoding is <7u>.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
7 CRS Coarse calibration control
Value ENUM Name Description
0x0 DIS Disable coarse calibration
0x1 EN Enable coarse calibration
RW 0
6 MID Mid calibration control
Value ENUM Name Description
0x0 DIS Disable mid calibration
0x1 EN Enable mid calibration
RW 0
5 KTDC KTDC estimation control

It's necessary to estimate the TDC gain to compute its' inverse, CAL2.KTDCINV. The latter is used to normalize TDC integer result into fractional CKVD periods.
Value ENUM Name Description
0x0 DIS Disable TDC estimation
0x1 EN Enable TDC estimation
RW 0
4 KDCO KDCO estimation control
Value ENUM Name Description
0x0 DIS Disable KDCO estimation
0x1 EN Enable KDCO estimation
RW 0
3:2 TDCAVG TDC average control

During TDC calibration the TDC measures a pulse of DLOCTL0.TDCSTOP duration. The measurement is repeated 2^CAL0.TDCAVG times by the FSM and the individual TDC results are accumulated and the final result is available in TDCCAL.VAL.
Value ENUM Name Description
0x0 REPEAT_1_TIME Repeat measurement 1 time
0x1 REPEAT_2_TIMES Repeat measurement 2 times
0x2 REPEAT_4_TIMES Repeat measurement 4 times
0x3 REPEAT_8_TIMES Repeat measurement 8 times
RW 0b00
1:0 TDC_SPARE TDC spare bits
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00

TOP:LRFDRFE:CAL1

Address Offset 0x0000 0114
Physical Address 0x4008 3114 Instance 0x4008 3114
Description Calibration Configuration 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 SPARE15 SPARE15
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
14:8 FCTOP Fine code top

Fine code applied to DCO during KDCO estimation in FSM state FINE_TOP_ST. Ensure that CAL0.FCSTART value is the aritmetic mean of CAL1.FCBOT and this value.

Field encoding is <7u>.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
7 SPARE7 SPARE7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
6:0 FCBOT Fine code bottom

Fine code applied to DCO during KDCO estimation in FSM state FINE_BOT_ST. Ensure that CAL0.FCSTART value is the aritmetic mean of this value and CAL1.FCTOP.

Field encoding is <7u>.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000

TOP:LRFDRFE:CAL2

Address Offset 0x0000 0118
Physical Address 0x4008 3118 Instance 0x4008 3118
Description Calibration Configuration 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 KTDCINV KTDC inverse

FW updates field with the inverse KTDC value before it enables KDCO estimation. KTDC value is availble in TDCCAL.VAL.

One CKVD clock period is normalized to phase of 2^16, hence FW calculates field value according to:

KTDCINV = 2^(16+CAL0.TDCAVG+DLOCTL0.TDCSTOP)/TDCCAL.VAL

Encoding is <0.16u>.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:CAL3

Address Offset 0x0000 011C
Physical Address 0x4008 311C Instance 0x4008 311C
Description Calibration Configuration 3
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DTXGAIN Addition path gain

The modulator resolution is given by:

MOD_RES = FRF / 2^(21+MOD0.CANPTHGAIN) Hz/LSB

This resolution is achieved when DC gain in addition and cancellation paths are equal. To achieve this condition, the addtion path gain must account for the estimated KDCO according to:

DTXGAIN = 2^14 * MOD_RES / KDCO = FRF / KDCO / 2^(7+MOD0.CANPTHGAIN)

Encoding is <2.14u>.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:MISC0

Address Offset 0x0000 0120
Physical Address 0x4008 3120 Instance 0x4008 3120
Description SDM and Delay Configuration 0
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 PHCPT Phase capture mode

Field decides if the phase capture mechanism is synchronous to phase valid signal or not. Default is synchronous mode (0).
Value ENUM Name Description
0x0 SYNC Phase capture mode is synchronous
0x1 ASYNC Phase capture mode is asyncrhonous
RW 0
12 TDCCALCORR Detect and correct errors in TDC value during calibration

Value shall remain static after DLOCTL0.RSTN equals 1.
Value ENUM Name Description
0x0 DIS Disable TDC error correction inside DLO.
0x1 EN Enable TDC error correction inside DLO.
RW 0
11 TDCMSBCORR TDC MSB error correction control

Value shall remain static after DLOCTL0.RSTN equals 1.
Value ENUM Name Description
0x0 DIS Disable TDC error correction inside DLO.
0x1 EN Enable TDC error correction inside DLO.
RW 0
10 SDMDEM SDM dynamic element matching control
Value ENUM Name Description
0x0 DIS Disable dynamic element matching
0x1 EN Enable dynamic element matching (recommended)
RW 0
9:8 DLYSDM SDM delay match configuration

Fine tune latency for integer part of fine code. The delay should match delay through SDM.
Value ENUM Name Description
0x0 CKVD16_0_PER Delay integer fine code by 0 CKVD16 clock periods
0x1 CKVD16_1_PER Delay integer fine code by 1 CKVD16 clock period
0x2 CKVD16_2_PER Delay integer fine code by 2 CKVD16 clock periods
0x3 CKVD16_3_PER Delay integer fine code by 3 CKVD16 clock periods
RW 0b00
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 DLYPHVALID Phase valid delay
Value ENUM Name Description
0x0 CKVD16_0_PER No additional delay on variable phase capture.
0x1 CKVD16_1_PER Delays the variable phase capture and hence the phase error calculation with 1 CKVD16 clock period.
RW 0
5:4 DLYCANCRS Cancellation path coarse delay

Coarse tune latency for cancellation path in relation to the addition path (when modulating). The final delay is the sum of coarse delay and fine delay.
Value ENUM Name Description
0x0 CKVD64_0_PER Delay by 0 CKVD64 clock periods
0x1 CKVD64_1_PER Delay by 1 CKVD64 clock period
0x2 CKVD64_2_PER Delay by 2 CKVD64 clock periods
0x3 CKVD64_3_PER Delay by 3 CKVD64 clock periods
RW 0b00
3:2 DLYCANFINE Cancellation path fine delay

Fine tune latency for cancellation path in relation to the addition path (when modulating). The final delay is the sum of coarse delay and fine delay.
Value ENUM Name Description
0x0 CKVD16_1_PER Delay by 1 CKVD16 clock periods
0x1 CKVD16_2_PER Delay by 2 CKVD16 clock period
0x2 CKVD16_3_PER Delay by 3 CKVD16 clock periods
0x3 CKVD16_4_PER Delay by 4 CKVD16 clock periods
RW 0b00
1:0 DLYADD Addition path delay

Field specifies additional latency on the modulation data towards antenna.
Value ENUM Name Description
0x0 CKVD64_0_PER Delay by 0 CKVD64 clock periods
0x1 CKVD64_1_PER Delay by 1 CKVD64 clock period
0x2 CKVD64_2_PER Delay by 2 CKVD64 clock periods
0x3 CKVD64_3_PER Delay by 3 CKVD64 clock periods
RW 0b00

TOP:LRFDRFE:MISC1

Address Offset 0x0000 0124
Physical Address 0x4008 3124 Instance 0x4008 3124
Description SDM and Delay Configuration 1
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 FCDEMCLK Bitmask to enable additive terms in INL correction

See implementation spec for details
Value ENUM Name Description
0x0 CKCD16 ckvd16 clock used for update upper and lower DWA DEM
0x1 CKVD64 ckvd64 clock used for update upper and lower DWA DEM
RW 0
13:12 FCDEMUPD Configures dynamic element matching of fine code
Value ENUM Name Description
0x0 DEFAULT Default: Update both DWAs always at rising edge of selected clock
0x1 PH_ERR phase_error[0]. (Phase error is 6.11s )
0x2 SDM SDM[1] (this value depends on DEM for SDM)
0x3 SDM_XOR_PH_ERR phase_error[0] xor SDM[1]
RW 0b00
11:6 TDCINL Bitmask to enable additive terms in INL correction

See implementation spec for details
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x3F ONES All bits are one
RW 0b00 0000
5 TDCINLCTL Enables INL correction of TDC
Value ENUM Name Description
0x0 DIS Disabled INL correction
0x1 EN Enables INL correction of TDC
RW 0
4 PHINIT Decides if there is known phase relationship between reference clock and RF
Value ENUM Name Description
0x0 KNOWN Known phase
0x1 UNKNOWN Unknown phase
RW 0
3 SDMOOVRCTL Force SDMOOVR towards DCO
Value ENUM Name Description
0x0 DIS Disable SDM output override
0x1 EN Enable SDM output override
RW 0
2:0 SDMOOVR SDM output code override

When MISC1.SDMOOVRCTL = EN, field value overrides the 3-bit SDM output to DCO.
When MISC1.SDMOOVRCTL = DIS, SDM takes 8-bit input and modulates the 3-bit output to DCO.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000

TOP:LRFDRFE:LF0

Address Offset 0x0000 0128
Physical Address 0x4008 3128 Instance 0x4008 3128
Description Loop Filter Configuration 0
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 KIPREC FIR integral gain precision

When numerical value of KI is lower than 16-1/256, high precision can be enabled.
FIR loop filter gets reinitialized with the current value whenever:
- DLO moves from calibration operation to closed-loop state.
- DLO moves from open-loop operation to closed-loop operation.
- DLO is in closed-loop operation and there is a change on loop control set. See DLOCTL0.LOOPUPD.
Value ENUM Name Description
0x0 LOW KI encoding is <12.0u>
0x1 HIGH KI encoding is <4.08>
RW 0
11:0 KI FIR integral gain

Field sets the integral gain in the FIR loop filter.

FIR_KI = pi^2 * f3db^2 / (FREF * KDCO * DF^2)

where DF is the desired damping factor. Lower damping factor gives lower phase margin in the loop. Typically damping factors in the range 0.75 to 1 is used. Note that equations above become more accurate when DF > 1.

Encoding is given by KIPREC setting. Examples:

When KIPREC = 0:

0x000: KI = 0
0x001: KI = 1
0xFFF: KI = 4095

When KIPREC = 1:

0x000: KI = 0x0.00 = 0.0
0x001: KI = 0x0.01 = 0.00390625
0x002: KI = 0x0.02 = 0.0078125
0x004: KI = 0x0.40 = 0.25
0x008: KI = 0x0.80 = 0.5
0xFF0: KI = 0xF.F0 = 15.9375
0xFFF: KI = 0xF.FF = 15.99609375

FIR loop filter gets reinitialized with the current value whenever:
- DLO moves from calibration operation to closed-loop state.
- DLO moves from open-loop operation to closed-loop operation.
- DLO is in closed-loop operation and there is a change on loop control set. See DLOCTL0.LOOPUPD.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RW 0x000

TOP:LRFDRFE:LF1

Address Offset 0x0000 012C
Physical Address 0x4008 312C Instance 0x4008 312C
Description Loop Filter Configuration 1
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:0 KP FIR proportional gain

Field sets the proportional gain in FIR loop filter.

FIR_KP = 2*pi* f3db / KDCO

Encoding is <14.0u>:
0x0000: Minimum proportional gain
0x3FFF: Maximum proportional gain

FIR loop filter gets reinitialized with the current value whenever DLO moves from calibration or open-loop operation to closed-loop operation.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FFF ALLONES All the bits are 1
RW 0b00 0000 0000 0000

TOP:LRFDRFE:PHEDISC

Address Offset 0x0000 0130
Physical Address 0x4008 3130 Instance 0x4008 3130
Description Phase Error Discard Configuration
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:10 CNT Phase error discard count

When phase error discarding is enabled, FIR loop filter does not update if:

abs(phase error) > PHEDISC_THR / 64

Update loop if this happens for CNT consecutive REFCLK periods.

Set DLOCTL1.PHEDISC = EN to enable phase error discarding.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
9:0 THR Phase error discard threshold

When phase error discarding is enabled, FIR loop filter does not update if:

abs(phase error) > PHEDISC_THR / 64

Update loop if this happens for CNT consecutive REFCLK periods.

Set DLOCTL1.PHEDISC = EN to enable phase error discarding.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDRFE:PHINIT

Address Offset 0x0000 0134
Physical Address 0x4008 3134 Instance 0x4008 3134
Description Phase Initialization Configuration
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 OFF Reference phase offset

Field initializes phase offset between CKVD and reference clock.

Encoding of field is <0.8u>.

Examples:
0x40: 25% of CKVD clock period
0x80: 50% of CKVD clock period
0xC0: 75% of CKVD clock period
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:PLLMON0

Address Offset 0x0000 0138
Physical Address 0x4008 3138 Instance 0x4008 3138
Description PLL Monitor Configuration 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 PHELOLCNT Phase error lock loss count

Loss of lock is indicated when abs(phase error) > PHELOLTHR / 2:

- for PHELOLCNT consecutive periods of REFCLK .
- and loop filter fincode overflows or underflows.

When either of these conditions occur DLOEV.LOL flag gets set in REFCLK domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for further description.
Value ENUM Name Description
0x0 REFCLK_16_PER Threshold count is 16 REFCLK periods
0x1 REFCLK_32_PER Threshold count is 32 REFCLK periods
0x2 REFCLK_64_PER Threshold count is 64 REFCLK periods
0x3 REFCLK_128_PER Threshold count is 128 REFCLK periods
RW 0b00
13:8 PHELOLTHR Phase error lock loss threshold

Loss of lock is indicated when abs(phase error) > PHELOLTHR / 2:

- for PLLMON0.PHELOLCNT consecutive periods of REFCLK .
- and loop filter fincode overflows or underflows.

When either of these conditions occur DLOEV.LOL flag gets set in REFCLK domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for further description.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:0 FCTHR Fine code threshold

Field sets two symmetric thresholds, with encoding <7.8u>:
FCLWTHR = {FCTHR, 8'b0}
FCUPTHR = {8'b0111111 - FCTHR), 8'b1}

The PLL monitor compares the final 15-bit fine code sent to DCO and SDM to these thresholds:

When fine code > FCUPTHR, DLOEV.FCABVTHR flag gets set in REFCLK domain.
When fine code < FCLWTHR, DLOEV.FCBLWTHR flag gets set in REFCLK domain.

In both cases synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for further description.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000

TOP:LRFDRFE:PLLMON1

Address Offset 0x0000 013C
Physical Address 0x4008 313C Instance 0x4008 313C
Description PLL Monitor Configuration 1
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:8 PHELOCKCNT Phase error lock count

Declare lock for PLL if:

abs(phase error) < PHELOCKTHR / 64

for PHELOCKCNT*4 consecutive periods of default REFCLK. When this happens DLOEV.LOCK flag gets set in REFCLK domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for further description.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
7:0 PHELOCKTHR Phase error lock threshold

Declare lock for PLL if:

abs(phase error) < PHELOCKTHR / 64

for PHELOCKCNT *4 consecutive periods of default REFCLK.When this happens DLOEV.LOCK flag gets set in REFCLK domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for further description.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:MOD0

Address Offset 0x0000 0140
Physical Address 0x4008 3140 Instance 0x4008 3140
Description Modulator Configuration 0
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:11 SCHEME Scheme

Field sets the modulation scheme of the DLO
Value ENUM Name Description
0x0 NC No connect

Modulator output does not add to frequencey control word from PLL.
0x1 INLOOP_MOD_FREF In-loop modulation with FREF resolution

MOD_RES = FREF / (DIVIDER/2) / 2^(15+CANPTHGAIN)

DIV.RATIO determines DIVIDER configuration. Scheme only supports closed-loop operation.
0x2 INLOOP_MOD_FRF In-loop modulation with FRF resolution

MOD_RES = FRF / 2^(21+CANPTHGAIN)
0x3 TWO_POINT_MOD_FRF 2-point modulation with FRF resolution

MOD_RES = FRF / 2^(21+CANPTHGAIN)

Scheme supports both open -and closed-loop operation. Scheme allows wider modulation bandwiths than INLOOP_MOD_FRF.
RW 0b00
10:8 SYMSHP Symbol shaper
Value ENUM Name Description
0x0 SHAPEDFSK Use generic 3 symbol shaper defined by SHAPECFG* registers.
0x1 ZIGBEE Use unshaped zigbee
0x2 PCWSPSK Use piecewise linear PSK shaper defined by SHAPECFG* registers.
0x3 SHAPEDZIGBEE Use Shaped 802.15.4 modulation
0x4 CHIRP Chirp modulation
RW 0b000
7:6 CANPTHGAIN Cancellation path gain

The cancellation phase is scaled by a configurable gain, which effectively sets the modulator frequency control word resolution. To calculate the resolution, use the binary value of this field in equations in SCHEME.
Value ENUM Name Description
0x0 TWO_POW_M_15 POW(2,-15)
0x1 TWO_POW_M_16 POW(2,-16)
0x2 TWO_POW_M_17 POW(2,-17)
0x3 TWO_POW_M_18 POW(2,-18)
RW 0b00
5:4 SHPGAIN Shape gain

Field sets the scaling factor for shape elements in DTX0 - DTX5. Both the scaling factor and shape element values are generated offline for a certain frequency deviation.
Value ENUM Name Description
0x0 X1 Shape gain = 1
0x1 X2 Shape gain = 2
0x2 X4 Shape gain = 4
0x3 X8 Shape gain = 8
RW 0b00
3:2 INTPFACT Interpolation factor

Field sets the interpolation factor of the shape filter.
Value ENUM Name Description
0x0 ILLEGAL0 Illegal, unsupported setting
0x1 INTP_BY_16 Interpolate by 16
0x2 INTP_BY_32 Interpolate by 32
0x3 ILLEGAL1 Illegal, unsupported setting
RW 0b00
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:LRFDRFE:MOD1

Address Offset 0x0000 0144
Physical Address 0x4008 3144 Instance 0x4008 3144
Description Modulator Configuration 1
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:0 FOFF Frequency Offset

Field configures the optional intermediate frequency (IF) used in TX or RX.

IF = FRF / 2^(21+CANPTHGAIN) * FOFF

Encoding is <12.0s>.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RW 0x000

TOP:LRFDRFE:DTX0

Address Offset 0x0000 0148
Physical Address 0x4008 3148 Instance 0x4008 3148
Description Digital TX Configuration 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP1 Shape element 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP0 Shape element 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX1

Address Offset 0x0000 014C
Physical Address 0x4008 314C Instance 0x4008 314C
Description Digital TX Configuration 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP3 Shape element 3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP2 Shape element 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX2

Address Offset 0x0000 0150
Physical Address 0x4008 3150 Instance 0x4008 3150
Description Digital TX Configuration 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP5 Shape element 5
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP4 Shape element 4
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX3

Address Offset 0x0000 0154
Physical Address 0x4008 3154 Instance 0x4008 3154
Description Digital TX Configuration 3
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP7 Shape element 7
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP6 Shape element 6
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX4

Address Offset 0x0000 0158
Physical Address 0x4008 3158 Instance 0x4008 3158
Description Digital TX Configuration 4
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP9 Shape element 9
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP8 Shape element 8
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX5

Address Offset 0x0000 015C
Physical Address 0x4008 315C Instance 0x4008 315C
Description Digital TX Configuration 5
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP11 Shape element 11
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP10 Shape element 10
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX6

Address Offset 0x0000 0160
Physical Address 0x4008 3160 Instance 0x4008 3160
Description Digital TX Configuration 6
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP13 Shape element 13
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP12 Shape element 12
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX7

Address Offset 0x0000 0164
Physical Address 0x4008 3164 Instance 0x4008 3164
Description Digital TX Configuration 7
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP15 Shape element 15
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP14 Shape element 14
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX8

Address Offset 0x0000 0168
Physical Address 0x4008 3168 Instance 0x4008 3168
Description Digital TX Configuration 8
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP17 Shape element 17
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP16 Shape element 16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX9

Address Offset 0x0000 016C
Physical Address 0x4008 316C Instance 0x4008 316C
Description Digital TX Configuration 9
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP19 Shape element 19
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP18 Shape element 18
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX10

Address Offset 0x0000 0170
Physical Address 0x4008 3170 Instance 0x4008 3170
Description Digital TX Configuration 10
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP21 Shape element 21
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP20 Shape element 20
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTX11

Address Offset 0x0000 0174
Physical Address 0x4008 3174 Instance 0x4008 3174
Description Digital TX Configuration 11
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 SHP23 Shape element 23
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 SHP22 Shape element 22
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:PLLM0L

Address Offset 0x0000 0178
Physical Address 0x4008 3178 Instance 0x4008 3178
Description PLL M0 Low
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:2 VALLSB PLLM0 value

Field sets the desired output frequency of the PLL, FRF, using the default PLL reference frequency, according to:

M-value = FRF * (DIVIDER/2) / FREF0

Field encoding is <12.18u>

PRE0.PLLDIV0 determines FREF0. DIV.RATIO determines DIVIDER.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FFF ALLONES All the bits are 1
RW 0b00 0000 0000 0000
1:0 SPARE0 SPARE0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00

TOP:LRFDRFE:PLLM0H

Address Offset 0x0000 017C
Physical Address 0x4008 317C Instance 0x4008 317C
Description PLL M0 High
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB PLLM0 value

Field sets the desired output frequency of the PLL, FRF, using the default PLL reference frequency, according to:

M-value = FRF * (DIVIDER/2) / FREF0

Field encoding is <12.18u>

PRE0.PLLDIV0 determines FREF0. DIV.RATIO determines DIVIDER.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:PLLM1L

Address Offset 0x0000 0180
Physical Address 0x4008 3180 Instance 0x4008 3180
Description PLL M1 Low
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:2 VALLSB PLLM1 value

Field sets the desired output frequency of the PLL, FRF, using the default PLL reference frequency, according to:

M-value = FRF * (DIVIDER/2) / FREF1

Field encoding is <12.18u>

PRE0.PLLDIV1 determines FREF1. DIV.RATIO determines DIVIDER.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FFF ALLONES All the bits are 1
RW 0b00 0000 0000 0000
1:0 SPARE0 SPARE0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00

TOP:LRFDRFE:PLLM1H

Address Offset 0x0000 0184
Physical Address 0x4008 3184 Instance 0x4008 3184
Description PLL M1 High
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB PLLM1 value

Field sets the desired output frequency of the PLL, FRF, using the default PLL reference frequency, according to:

M-value = FRF * (DIVIDER/2) / FREF1

Field encoding is <12.18u>

PRE0.PLLDIV1 determines FREF1. DIV.RATIO determines DIVIDER.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:CALMCRS

Address Offset 0x0000 0188
Physical Address 0x4008 3188 Instance 0x4008 3188
Description Calibration M Coarse
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Coarse SAR m-value

Field sets the desired output frequency of the PLL, FRF, during coarse SAR, according to:

VAL = FRF * (DIVIDER/2) / COARSE_CALIB_FREF

Field encoding is <16u>.

PRE2.CRSCALDIV determines COARSE_CALIB_FREF. DIV.RATIO determines DIVIDER.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:CALMMID

Address Offset 0x0000 018C
Physical Address 0x4008 318C Instance 0x4008 318C
Description Calibration M Mid
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Mid SAR m-value

Field sets the desired output frequency of the PLL, FRF, during mid SAR, according to:

VAL = FRF * (DIVIDER/2) / MID_CALIB_FREF

Field encoding is <16u>.

PRE2.MIDCALDIVLSB and PRE3.MIDCALDIVMSB determines MID_CALIB_FREF. DIV.RATIO determines DIVIDER.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:REFDIV

Address Offset 0x0000 0190
Physical Address 0x4008 3190 Instance 0x4008 3190
Description REFCLK Prescaler Load Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 LOAD Load value for 16-bit REFCLK prescaler

The REFCLK prescaler is used when DLOCTL0.LOOPUPD bit-2 = 1.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:DLOCTL0

Address Offset 0x0000 0198
Physical Address 0x4008 3198 Instance 0x4008 3198
Description DLO Control Register 0

This register contains dynamic signals, and can be updated when DLO is out of reset.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 TDCSTOP TDC stop configuration

During TDC calibration the value specifies the pulse duration used to calculate the TDC gain as number of CKVD periods (2 / FDCO). Value effectively sets the resolution of the FW-calculated CAL2.KTDCINV.

Otherwise, the TDC stop delay is programmable in units of CKVD clock periods. The stop delay is either static or randomly decided per reference clock period. The latter is referred to as TDC stop-time dithering.

000: TDC stops when flop 0 becomes 1. During TDC calibration pulse length is 1 CKVD period.
001: TDC stops when flop 1 becomes 1. During TDC calibration pulse length is 2 CKVD periods.
010: TDC stops when flop 2 becomes 1. During TDC calibration pulse length is 3 CKVD periods.
011: TDC stops when flop 3 becomes 1. During TDC calibration pulse length is 4 CKVD periods.
1xx: TDC stops when a randomly chosen flop becomes 1. Do not use for TDC calibration.
Value ENUM Name Description
0x0 CLOSED Closed-loop operation
0x1 OPEN Open-loop operation
RW 0b000
7 DTSTXTAL XTALBAW DTST interface control

Configure DTST interface in DTST when interface is disabled.
Value ENUM Name Description
0x0 ZERO Disable XTALBAW DTST interface
0x1 ONE Enable XTALBAW DTST interface
RW 0
6:4 LOOPUPD Loop update control

The PLL frequency and loop dynamics are controlled through a set of configurations of coarse and mid codes, TCD gain, reference clock divider, and feedback divider(PLLM). Registers for PLLM and reference clock dividers are duplicated to support REFCLK dithering, and/or loop BW gearing. These are set 0 and set 1. It is also possible to update all configurations at certain events to move the frequency around in the tuning range, and adjust the loop bandwidth at the same time. Basically:
- bit-0: Static control set select (manual switch-FW)
0 : select control set 0.
1 : select control set 1.
- bit-1: Dithering select (automatic switch-LFSR)
0: Functionality unused.
1: LFSR single bit output is used to select control set according to bit-0 select rules. Average F_REFCLK to be used in Ki equation is the harmonic mean, F_REFCLK = 2/[1/F_REFCLK0 + 1/F_REFCLK1].
- bit-2: Timer select (automatic switch-prescaler)
0: Functionality unused.
1: On every REFDIV.LOAD REFCLK event DLO toggles the control set select. FW can update the one not used.

There are restrictions on legal settings and transitions.
Value ENUM Name Description
0x0 DEF Use default FREF (PLLM0)
0x1 ALT Use alternate REF (PLLM1)
RW 0b000
3 PH3 Lock aquisition / calibration phase 3 control
Value ENUM Name Description
0x0 HALT Halt DLO FSM after DCO frequency span measurement

When DLO and RFE runs KDCO estimation, RFE must compute KDCO from the frequency span, and calculate loop filter settings to use before lock aquisition.
0x1 START Close the loop to aquire phase lock, i.e. phase 3 of calibration routine.
RW 0
2 PH2 KDCO estimation / calibration phase 2 control
Value ENUM Name Description
0x0 HALT Halt DLO FSM after TDC calibration measurement

When DLO and RFE runs TDC calibration, RFE must use calibration measurement to calculcate CAL2.KTDCINV.
0x1 START Start KDCO estimation, i.e. phase 2 of calibration routine.
RW 0
1 LOOPMODE Loop mode control
Value ENUM Name Description
0x0 CLOSED Closed-loop operation
0x1 OPEN Open-loop operation
RW 0
0 RSTN DLO reset

DLO active low reset. The DLO has several static inputs that all needs to be set prior to releasing reset.
Value ENUM Name Description
0x0 RESET DLO is reset
0x1 ACTIVE DLO is not held in reset
RW 0

TOP:LRFDRFE:DLOCTL1

Address Offset 0x0000 01A0
Physical Address 0x4008 31A0 Instance 0x4008 31A0
Description DLO Control Register 1

This register contains dynamic signals, and can be updated when DLO is out of reset.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 DCO DCO control
Value ENUM Name Description
0x0 DIS Disable DCO
0x1 EN Enable DCO
RW 0
14:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
7 FCDEM Finecode dynamic element match control
Value ENUM Name Description
0x0 DIS Disable DEM
0x1 EN Enable DEM
RW 0
6 DTSTCKVD CKVD DTST interface control

Configure DTST interface in DTST when interface is disabled.
Value ENUM Name Description
0x0 ZERO Disable CKVD DTST interface
0x1 ONE Enable CKVD DTST interface
RW 0
5 PHEDISC Phase error discarding control

Feature discards large phase errors from propagating into the loop filter. PHEDISC configures the behavior.
Value ENUM Name Description
0x0 DIS Disable phase error discard function
0x1 EN Enable phase error discard function
RW 0
4 PLLMON PLL monitor control

The PLL monitor detects the following PLL states in the variable clock domain:
- Lock (static)
- Loss of lock (dynamic)
- Fine code above threshold (static)
- Fine code below threshold (static)

The monitor signals the occurence of these conditions to the reference clock domain. This domain does positive edge detection for lock and loss-of-lock events, and synchronizes the threshold events. The IRQ to modem is high whenever reference clock domain events are high.

The lock and loss-of-lock flags are cleared individually in the reference clock domain. Disable the PLL monitor to reset the all event flags in the variable clock domain. PLL Lock and Loss of Lock flags are automatically cleared in the variable clock domain when transitioning from open-loop to closed-loop operation.

To clear Lock and Loss of Lock flags using this field, the DLO must operate in closed-loop mode, and a new value must be stable for at least 2 REFCLK periods.

Keep PLL monitor disabled during the calibration states.
Value ENUM Name Description
0x0 DIS Disable and reset PLL monitor
0x1 EN Enable PLL monitor
RW 0
3 IIR IIR control

Do not enable during lock aquisition.
Value ENUM Name Description
0x0 DIS Disable IIR filter
0x1 EN Enable IIR filter
RW 0
2 MOD Modulator control

Enable of MODISF (Modulator's Interpolating Shaping Filter)
Value ENUM Name Description
0x0 DIS Disable MODISF
0x1 EN Enable MODISF
RW 0
1 MODINIT Modulator Initialization
Value ENUM Name Description
0x0 DEACTIVATE Deactivate MODISF initialization
0x1 ACTIVATE Activate MODISF initialization
RW 0
0 MTDCRSTN MTDC reset
Value ENUM Name Description
0x0 RESET Reset MTDC
0x1 ACTIVE Release MTDC reset
RW 0

TOP:LRFDRFE:DCOOVR0

Address Offset 0x0000 01A8
Physical Address 0x4008 31A8 Instance 0x4008 31A8
Description DCO Override 0
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:8 MIDCODE Mid code override

When MIDCTL equals EN, field value overrides the DCO mid code, which sets the DCO mid row and column control. Special encoding:
MIDCODE[5:4]:
00: DCO mid row = 15
01: DCO mid row = 7
10: DCO mid row = 3
11: DCO mid row = 1

DCO mid column = 15-to_integer(MIDCODE[3:0])
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7:4 CRSCODE Coarse code override

When CRSCTL equals EN, field value overrides the DCO coarse control. This is required during debug and when coarse calibration is skipped, or we want to use other values during startup of ALO. Encoding is <4.0u>:

0xFF: min frequency
…
0x00: max frequency
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
3 FINECTL Fine code override control
Value ENUM Name Description
0x0 DIS Disable fine code override
0x1 EN Enable fine code override
RW 0
2 SDMICTL SDM input code override control
Value ENUM Name Description
0x0 DIS Disable SDM input code override
0x1 EN Enable SDM input code override
RW 0
1 MIDCTL Mid code override control
Value ENUM Name Description
0x0 DIS Disable mid code override
0x1 EN Enable mid code override
RW 0
0 CRSCTL Coarse code override
Value ENUM Name Description
0x0 DIS Disable coarse code override
0x1 EN Enable coarse code override
RW 0

TOP:LRFDRFE:DCOOVR1

Address Offset 0x0000 01AC
Physical Address 0x4008 31AC Instance 0x4008 31AC
Description DCO Override 1
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14:8 FINECODE Fine code override

When DCOOVR0.FINECTL equals EN, field value overrides the integer part of DCO fine code .

Encoding is <7.0u>:
0x00: Min
...
0x7F: MAX
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RW 0b000 0000
7:0 SDMICODE SDM input code override

When DCOOVR0.SDMICTL equals EN, field value overrides the fractional part of DCO fine code to SDM. Encoding is <0.8u>:
0x00: 0
...
0x7F: 0.99609375

The fractional value is added to the integer part.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:DTST

Address Offset 0x0000 01B0
Physical Address 0x4008 31B0 Instance 0x4008 31B0
Description Data Test

Configuration register for DTST interface that allows streaming of PLL signal values to LRFDS2R, and to select signal to read in DTSTRD.DATA.
Configuration must happen when DLOCTL0.DTSTXTAL and DLOCTL0.DTSTCKVD are 0.
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14:11 SPARE11 SPARE111
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
10:8 VARTGLDLY Variable domain toggle delay

Field sets delay on toggle launch compared to data launch. CLK equals launch clock for signal selected in SIG. It can be eiter CKVD16 or reference clock.
Value ENUM Name Description
0x0 CLK_0_PER Toggle lags data by 0 CKVD16 periods.
0x1 CLK_1_PER Toggle lags data by 1 CKVD16 periods.
0x2 CLK_2_PER Toggle lags data by 2 CKVD16 periods.
0x3 CLK_3_PER Toggle lags data by 3 CKVD16 periods.
0x4 CLK_4_PER Toggle lags data by 4 CKVD16 periods.
0x5 CLK_5_PER Toggle lags data by 5 CKVD16 periods.
0x6 CLK_6_PER Toggle lags data by 6 CKVD16 periods.
0x7 CLK_7_PER Toggle lags data by 7 CKVD16 periods.
RW 0b000
7 REFTGLDLY Reference domain toggle delay

Field sets delay on toggle launch compared to data launch. CLK equals launch clock for signal selected in SIG. It can be eiter CKVD16 or reference clock.
Value ENUM Name Description
0x0 CLK_0_PER Toggle lags data by 0 HFXT/BAW periods.
0x1 CLK_1_PER Toggle lags data by 1 HFXT/BAW periods.
RW 0
6 TRNSEQ Trainer sequence control

When trainer sequence is enabled, dtst data will not reflect SIG configuration. Instead, it will toggle between 0x5555 and 0xAAAA for every update uof the data specified by SIG.
Value ENUM Name Description
0x0 DIS Disable trainer sequence
0x1 EN Enable trainer sequence
RW 0
5 SPARE5 SPARE5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
4:0 SIG Signal Configuration

Selects which signal to route to DTST data port. Any change to MSB may cause modem to detect false toggle. Hence, the first sample must be discarded in modem after a change to MSB.

Whenever signal po_tdc_stop_dly_sel is sampled, discard the first three samples.

All bits in dtst_data vector originates from the same reference clock edge, unless otherwise noted.
Value ENUM Name Description
0x0 REF_NC_0 dtst_data = 0x0000
0x1 REF_FSMCAL dtst_data :

[15] : '0'
[14] : u_fsm/pi_pll_lock_ind
[13:10] : u_fsm/po_dsts_fsm_state
[9:6] : u_fsm/po_dtst_fsm_coarse
[5:0] : u_fsm/po_dtst_fsm_mid
0x2 REF_FERR_MAG dtst_data = u_fsm/po_dtst_fsm_ferr_mag

Format is14.2u. The signal is only updated for frequency measurements that affect the calibration result.
0x3 REF_NC_3 dtst_data = 0x0000
0x4 REF_NC_4 dtst_data = 0x0000
0x5 REF_NC_5 dtst_data = 0x0000
0x6 REF_NC_6 dtst_data = 0x0000
0x7 REF_NC_7 dtst_data = 0x0000
0x8 REF_NC_8 dtst_data = 0x0000
0x9 REF_NC_9 dtst_data = 0x0000
0xA REF_NC_10 dtst_data = 0x0000
0xB REF_NC_11 dtst_data = 0x0000
0xC REF_NC_12 dtst_data = 0x0000
0xD REF_NC_13 dtst_data = 0x0000
0xE REF_NC_14 dtst_data = 0x0000
0xF REF_NC_15 dtst_data = 0x0000
0x10 VAR_NC_0 dtst_data = 0x0000
0x11 VAR_PHERR_UPPER dtst_data = u_pll/phase_error[16:1]

Format is 6.10s.
0x12 VAR_PHERR_LOWER dtst_data :

[15] : u_pll/phase_error[16]
[14:0] : u_pll/phase_error[14:0]

Format is 5.11s. Phase error wraps if if too large.
0x13 VAR_PH_RAW dtst_data :

[15] ; u_pll/pi_tdc_msb_error
[14:11] : u_pll/pi_pi_cnt_lsb
[10:0] : u_pll/pi_tdc_data
0x14 VAR_PH_TDCCORR dtst_data :

[15] ; u_pll/pi_tdc_msb_error
[14:11] : u_pll/pi_pi_cnt_lsb
[10:0] : u_pll/tdc_data_corr
0x15 VAR_PH_COMP_PHERR_TDCSTOP dtst_data :

[15:14] : po_tdc_stop_dly_sel
[13] : u_pll/phase_error[16]
[12:9]: u_pll/phase_error[11:8]
[8:0] : u_pll/var_phase[14: 6]

[13:9] : phase error. Format is 2.3s.
[8:0] : variable phase. Format is 4.5u.
0x16 VAR_TDCSTOP_PHERR dtst_data :

[15:14] : po_tdc_stop_dly_sel
[13] u_pll/phase_error[16]
[12:0]: u_pll/phase_error[12:0]

[13:0] : phase_error. Format is 3.11s.
0x17 VAR_TDCSTOP_STATUS_TDC dtst_data :

[15:14] : po_tdc_stop_dly_sel
[13] : u_pll/pi_tdc_msb_error
[12] : u_pll/pll_loop_update
[11] : (u_pll/po_ckvd48_pllmon_lock XOR u_pll/po_ckvd48_pllmon_lol)
[10:0]: u_pll/pi_tdc_data

Note that [12:11] are samples from previous reference clock edge.
0x18 VAR_MPX_CAN dtst_data :

[15] : u_mpx/freq_can[16]
[14:0] : u_mpx/freq_can[14:0]

Format is 1.15s. This field holds how much phase DTX adds to DCO per reference frequency. This is a slice of the signals that goes to u_pll which is 3.18s. Hence, wrapping can occur.
0x19 VAR_LOCK_FINECODE dtst_data :

[15] : (u_pll/po_ckvd48_pllmon_lock XOR u_pll/po_ckvd48_pllmon_lol)
[14:0] : u_pll/po_ckvd16_finecode_pll
0x1A VAR_LOOP_UPD_FINECODE dtst_data :

[15] : (u_pll/pll_loop_update)
[14:0] : u_pll/po_ckvd16_finecode_pll
0x1B VAR_NC_11 dtst_data = 0x0000
0x1C VAR_NC_12 dtst_data = 0x0000
0x1D VAR_NC_13 dtst_data = 0x0000
0x1E VAR_NC_14 dtst_data = 0x0000
0x1F VAR_NC_15 dtst_data = 0x0000
RW 0b0 0000

TOP:LRFDRFE:DLOEV

Address Offset 0x0000 01B4
Physical Address 0x4008 31B4 Instance 0x4008 31B4
Description DLO FSM State and IRQ Flags
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 LOCK Lock

PLLMON1.PHELOCKCNT and PLLMON1.PHELOCKTHR configures the behaviour.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 LOL Loss of lock

PLLMON0.PHELOLCNT and PLLMON0.PHELOLTHR configures the behaviour.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 FCABVTHR Finecode above threshold

PLLMON0.FCTHR sets threshold.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 FCBLWTHR Finecode below threshold

PLLMON0.FCTHR sets threshold.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3:0 STATE DLO FSM state
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE:DTSTRD

Address Offset 0x0000 01B8
Physical Address 0x4008 31B8 Instance 0x4008 31B8
Description DTST Read
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Data selected by DTST.SIG when the DTST interface is enabled.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:FDCOSPANLSB

Address Offset 0x0000 01BC
Physical Address 0x4008 31BC Instance 0x4008 31BC
Description DCO Frequency Span
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL DCO frequency span
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:FDCOSPANMSB

Address Offset 0x0000 01C0
Physical Address 0x4008 31C0 Instance 0x4008 31C0
Description DCO Frequency Span
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 VAL DCO frequency span
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RO 0b000

TOP:LRFDRFE:TDCCAL

Address Offset 0x0000 01C4
Physical Address 0x4008 31C4 Instance 0x4008 31C4
Description TDC Calibration
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Value

Sum of inverter delays calculated by HW at the end of the TDC calibration. The number of delays summed is controlled by CAL0.TDCAVG and DLOCTL0.TDCSTOP. FW uses value to calculate CAL2.KTDCINV.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:CALRES

Address Offset 0x0000 01C8
Physical Address 0x4008 31C8 Instance 0x4008 31C8
Description Calibration Result
Type RO
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:4 MIDCODE Calibrated mid code
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RO 0b00 0000
3:0 CRSCODE Calibrated coarse code
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE:GPI

Address Offset 0x0000 01CC
Physical Address 0x4008 31CC Instance 0x4008 31CC
Description RFE Direct GPI Status
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 GPI7 Control GPI7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 GPI6 Control GPI6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 GPI5 Control GPI5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 GPI4 Control GPI4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 GPI3 Control GPI3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 GPI2 Control GPI2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 GPI1 Control GPI1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 GPI0 Control GPI0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE:MATHACCELIN

Address Offset 0x0000 01D0
Physical Address 0x4008 31D0 Instance 0x4008 31D0
Description Math Accellerator Input Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Input value in linear units
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:LIN2LOGOUT

Address Offset 0x0000 01D4
Physical Address 0x4008 31D4 Instance 0x4008 31D4
Description Lin2Log Output
Type RO
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6:0 LOGVAL Logarithmic output value

Logaritmic value of MATHACCELIN.VAL.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7F ALLONES All the bits are 1
RO 0b000 0000

TOP:LRFDRFE:DIVBY3OUT

Address Offset 0x0000 01D8
Physical Address 0x4008 31D8 Instance 0x4008 31D8
Description Divide By Three Output
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 DIV3 Divider output value

Calculation performed: MATHACCELIN.VAL/3

Supports input values <= 46, higher values are saturated.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDRFE:TIMCTL

Address Offset 0x0000 01DC
Physical Address 0x4008 31DC Instance 0x4008 31DC
Description Timer and Counter Control
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:8 CPTSRC Event capture source

Index selects the corresponding event from RFE event bus, EVT0 and EVT1.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7 CPTCTL Counter capture control

Upon selected capture event, the counter value will be captured into TIMCAPT.
Value ENUM Name Description
0x0 DIS Disable counter capture mode
0x1 EN Enable counter capture mode
RW 0
6:5 CNTRSRC Counter event source
Value ENUM Name Description
0x0 CLK Use clock
0x1 MAGN0 Use magnitude estimator 0 data enable
0x2 MAGN1 Use magnitude estimator 1 data enable
0x3 FREF Count FREF ticks
RW 0b00
4 CNTRCLR Counter clear value in TIMCNT.
Value ENUM Name Description
0x0 ZERO No action
0x1 ONE Clear counter value
RW 0
3 CNTRCTL 16-bit counter control

The counter will continue from its current value.
Value ENUM Name Description
0x0 DIS Disable counter
0x1 EN Enable counter
RW 0
2:1 TIMSRC Timer tick source
Value ENUM Name Description
0x0 CLK Use clock
0x1 MAGN0 Use magnitude estimator 0 data enable
0x2 MAGN1 Use magnitude estimator 1 data enable
0x3 FREF Count FREF ticks
RW 0b00
0 TIMCTL 16-bit timer control

It will generate a timer interrupt after TIMPER timer ticks. Note that the internal timer value is not readable from the RFE. If this is needed the counter should be used instead of the timer.
Value ENUM Name Description
0x0 DIS Disable timer and clear internal timer value
0x1 EN Enable timer
RW 0

TOP:LRFDRFE:TIMINC

Address Offset 0x0000 01E0
Physical Address 0x4008 31E0 Instance 0x4008 31E0
Description Counter Increment Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Programmable increment for the counter
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:TIMPER

Address Offset 0x0000 01E4
Physical Address 0x4008 31E4 Instance 0x4008 31E4
Description Timer/Counter Period Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Configurable 16 bit period that can be used for either the timer or the counter. In timer context, when timer value reach the timer period (i.e. it expires) a TIMER_IRQ event will occur, and the timer will restart from zero (until the timer is manually disabled). In counter context, a COUNTER_IRQ event will occur when the counter is equal to or higher than the period value.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:TIMCNT

Address Offset 0x0000 01E8
Physical Address 0x4008 31E8 Instance 0x4008 31E8
Description Counter Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL 16 bit value of counter
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:TIMCAPT

Address Offset 0x0000 01EC
Physical Address 0x4008 31EC Instance 0x4008 31EC
Description Counter Capture Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Captured value of counter
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:TRCCTRL

Address Offset 0x0000 01F0
Physical Address 0x4008 31F0 Instance 0x4008 31F0
Description Tracer Send Trigger
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 SEND Sends a command to the tracer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDRFE:TRCSTAT

Address Offset 0x0000 01F4
Physical Address 0x4008 31F4 Instance 0x4008 31F4
Description Tracer Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 BUSY Tracer busy status
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE:TRCCMD

Address Offset 0x0000 01F8
Physical Address 0x4008 31F8 Instance 0x4008 31F8
Description Tracer Commmand
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:8 PARCNT Number of parameters
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
7:0 PKTHDR Packet header
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:TRCPAR0

Address Offset 0x0000 01FC
Physical Address 0x4008 31FC Instance 0x4008 31FC
Description Tracer Command Parameter 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:TRCPAR1

Address Offset 0x0000 0200
Physical Address 0x4008 3200 Instance 0x4008 3200
Description Tracer Command Parameter 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:GPOCTL

Address Offset 0x0000 0204
Physical Address 0x4008 3204 Instance 0x4008 3204
Description Direct GPO Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 SEL7 Select GPO7 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO7
0x1 HW The pin is controlled by its HW source
RW 0
14 SEL6 Select GPO6 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO6
0x1 HW The pin is controlled by its HW source
RW 0
13 SEL5 Select GPO5 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO5
0x1 HW The pin is controlled by its HW source
RW 0
12 SEL4 Select GPO4 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO4
0x1 HW The pin is controlled by its HW source
RW 0
11 SEL3 Select GPO3 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO3
0x1 HW The pin is controlled by its HW source
RW 0
10 SEL2 Select GPO2 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO2
0x1 HW The pin is controlled by its HW source
RW 0
9 SEL1 Select GPO1 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO1
0x1 HW The pin is controlled by its HW source
RW 0
8 SEL0 Select GPO0 source
Value ENUM Name Description
0x0 SW The pin is controlled by GPOCTRL.GPO0
0x1 HW The pin is controlled by its HW source
RW 0
7 GPO7 Control GPO7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
6 GPO6 Control GPO6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
5 GPO5 Control GPO5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
4 GPO4 Control GPO4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
3 GPO3 Control GPO3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
2 GPO2 Control GPO2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
1 GPO1 Control GPO1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
0 GPO0 Control GPO0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0

TOP:LRFDRFE:ANAISOCTL

Address Offset 0x0000 0208
Physical Address 0x4008 3208 Instance 0x4008 3208
Description Analog Isolation and Reset Control
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4 ADCDIGRSTN Active low reset of ADC clock domain within Modem
Value ENUM Name Description
0x0 RESET Reset
0x1 ACTIVE Don't reset
RW 0
3 IFADC2SVTISO Isolation between IFADC and Modem
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1
2 DIV2IFADCISO Isolation between DIVBUF and IFADC
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1
1 MTDC2SVTISO Isolation between MTDC and Modem
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1
0 DIV2MTDCISO Isolation between DIVBUF and MTDC
Value ENUM Name Description
0x0 CONNECT Don't isolate
0x1 ISOLATE Isolate
RW 1

TOP:LRFDRFE:DIVCTL

Address Offset 0x0000 020C
Physical Address 0x4008 320C Instance 0x4008 320C
Description Divider Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 DIV2PH180 DIV2 PH180 path control

Enable DIV2 PH180 path
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
14 DIV2PH0 DIV2 PH0 path control

Enable DIV2 PH0 path
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
13 DIV2PH270 DIV2 PH270 path control

Enable DIV2 PH270 path
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
12 DIV2PH90 DIV2 PH90 path control

Enable DIV2 PH90 path
Value ENUM Name Description
0x0 DIS Disable path
0x1 EN Enable path
RW 0
11 SPARE11 Reserved
Value ENUM Name Description
0x0 ZERO Bit is 0
0x1 ONE Bit is one
RW 0
10 S1G20DBMMUX Not connected
Value ENUM Name Description
0x0 ENABLEN Enable mux
0x1 DISABLE Disable mux
RW 0
9 ADCDIV ADC divider control

Field enables divider that generates IFADC clock.
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
8 ENSYNTH Enables CKVD clock to MTDC
Value ENUM Name Description
0x0 DIS Clock is disabled
0x1 EN Clock is enabled
RW 0
7 TXPH18020DBMDIV Not connected
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
6 TXPH020DBMDIV Not connected
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
5 TXPH180DIV TX 180-phase divider control

Field enables divider that generates inverted TX RF signal to PA.
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
4 TXPH0DIV TX 0-phase divider control

Field enables divider that generates TX RF signal to PA.
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
3 RXPH90DIV RX quadrature-phase LO divider control

Field enables quadrature-phase RX LO divider.
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
2 RXPH0DIV RX in-phase LO divider control

Field enables in-phase RX LO divider.
Value ENUM Name Description
0x0 DIS Disable divider
0x1 EN Enable divider
RW 0
1 Spare1 Not connected, not used in LRF
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
0 EN Divider enable
Value ENUM Name Description
0x0 OFF Disable divider
0x1 ON Enable divider
RW 0

TOP:LRFDRFE:RXCTRL

Address Offset 0x0000 0210
Physical Address 0x4008 3210 Instance 0x4008 3210
Description RX Frontend Control
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 SPARE Reserved for future use
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
11:9 ATTN Attenuator Control
Value ENUM Name Description
0x0 NOATT No attenuation
0x1 _3DB 3dB attenuation
0x2 _6DB 6dB attenuation
0x3 _9DB 9dB attenuation
0x4 _12DB 12dB attenuation
0x5 _15DB 15dB attenuation
0x6 _18DB 18dB attenuation
0x7 _21DB 21dB attenuation
RW 0b000
8:4 IFAMPGC IFAMP Gain Control
Value ENUM Name Description
0x0 MIN15DB Set gain to MAX - 15 dB
0x1 MIN12DB Set gain to MAX - 12 dB
0x3 MIN9DB Set gain to MAX - 9 dB
0x7 MIN6DB Set gain to MAX - 6 dB
0xF MIN3DB Set gain to MAX - 3 dB
0x1F MAX Set IFAMP gain to MAX
RW 0b0 0000
3:0 LNAGAIN LNA Gain Control
Value ENUM Name Description
0x0 MIN12DB Set gain to MAX - 12 dB
0x1 MIN9DB Set gain to MAX - 9 dB
0x3 MIN6DB Set gain to MAX - 6 dB
0x7 MIN3DB Set gain to MAX - 3 dB
0xF MAX Set gain to MAX
RW 0x0

TOP:LRFDRFE:MAGNACC0

Address Offset 0x0000 0214
Physical Address 0x4008 3214 Instance 0x4008 3214
Description Magnitude Estimator 0 Accumulator Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Accumulated magnitude over the period
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:MAGNACC1

Address Offset 0x0000 0218
Physical Address 0x4008 3218 Instance 0x4008 3218
Description Magnitude Estimator 1 Accumulator Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Accumulated magnitude over the period
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:RSSI

Address Offset 0x0000 021C
Physical Address 0x4008 321C Instance 0x4008 321C
Description RSSI
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Current RSSI value (signed). If this register reads as -128 (0x80) it means that the value is not yet valid.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:RSSIMAX

Address Offset 0x0000 0220
Physical Address 0x4008 3220 Instance 0x4008 3220
Description RSSI Maximum Value
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Maximum RSSI value since start of measurements cycle. If this field reads as -128 (0x80) it means that the value is not yet valid.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:RFGAIN

Address Offset 0x0000 0224
Physical Address 0x4008 3224 Instance 0x4008 3224
Description RF Front-end Gain Value
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DBGAIN Current RF front-end gain, in dB
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDRFE:IFADCSTAT

Address Offset 0x0000 0228
Physical Address 0x4008 3228 Instance 0x4008 3228
Description IFADC Status
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 RESERVED7 Reserved for future use
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6:2 QUANTCALVAL Result of quantizer calibration. Valid only when calibration is done
Value ENUM Name Description
0x0 COMP0 Q Comparator
0x1 COMP1 I comparator
RO 0b0 0000
1 QUANTCALDONE Status of the quantizer calibration
Value ENUM Name Description
0x0 NOT_READY Calibration is not finished
0x1 READY Calibration is complete
RO 0
0 RESERVED0 Reserved for future use
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDRFE:DIVSTA

Address Offset 0x0000 022C
Physical Address 0x4008 322C Instance 0x4008 322C
Description Serial Divider Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT Indicates status of serial divider
Value ENUM Name Description
0x0 IDLE Serial divider is idle
0x1 BUSY Serial divider is busy and result is not available yet
RO 0

TOP:LRFDRFE:DIVIDENDL

Address Offset 0x0000 0230
Physical Address 0x4008 3230 Instance 0x4008 3230
Description Serial Divider Dividend
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB Dividend input (write only, reads as 0x0).
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
WO 0x0000

TOP:LRFDRFE:DIVIDENDH

Address Offset 0x0000 0234
Physical Address 0x4008 3234 Instance 0x4008 3234
Description Serial Divider Dividend
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB Dividend input (write only, reads as 0x0).
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
WO 0x0000

TOP:LRFDRFE:DIVISORL

Address Offset 0x0000 0238
Physical Address 0x4008 3238 Instance 0x4008 3238
Description Serial Divider Divisor

Register is also used for holding serial multiplier factor.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB Divisor input.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:DIVISORH

Address Offset 0x0000 023C
Physical Address 0x4008 323C Instance 0x4008 323C
Description Serial Divider Divisor

Register is also used for holding serial multiplier factor.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB Divisor input
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDRFE:QUOTIENTL

Address Offset 0x0000 0240
Physical Address 0x4008 3240 Instance 0x4008 3240
Description Serial Divider Quotient Low
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB Quotient output
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:QUOTIENTH

Address Offset 0x0000 0244
Physical Address 0x4008 3244 Instance 0x4008 3244
Description Serial Divider Quotient High
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB Quotient output
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:PRODUCTL

Address Offset 0x0000 0248
Physical Address 0x4008 3248 Instance 0x4008 3248
Description Product Low
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB Product of DIVISORL_VALLSB and DIVISORH_VALMSB
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:PRODUCTH

Address Offset 0x0000 024C
Physical Address 0x4008 324C Instance 0x4008 324C
Description Product High
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB Upper 16-bit of DIVISORL.VALLSB multiplied by DIVISORH.VALMSB
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDRFE:MULTSTA

Address Offset 0x0000 0250
Physical Address 0x4008 3250 Instance 0x4008 3250
Description Serial Multiplier Status
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT Multiplier result ready / HW multiplier idle
Value ENUM Name Description
0x0 IDLE Multiplier is idle
0x1 BUSY Multiplier is busy, result is not ready yet
RO 0

TOP:LRFDRFE:MULTCFG

Address Offset 0x0000 0258
Physical Address 0x4008 3258 Instance 0x4008 3258
Description Serial Multiplier Control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 MODE Controls unsigned / signed mode of serial multiplier
Value ENUM Name Description
0x0 UNSIGNED Multiplier assumes inputs are unsigned numbers
0x1 SIGNED Multiplier assumes inputs are signed numbers
RW 0


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