LRFDS2R

Instance: LRFDS2R
Component: LRFDS2R
Base address: 0x40085000


TOP:LRFDS2R Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CFG

RW

32

0x0000 0000

0x0000 0000

0x4008 5000

START

RW

32

0x0000 0000

0x0000 0004

0x4008 5004

STOP

RW

32

0x0000 0000

0x0000 0008

0x4008 5008

STAT

RO

32

0x0FFF 0000

0x0000 000C

0x4008 500C

TRIG

WO

32

0x0000 0000

0x0000 0010

0x4008 5010

TOP:LRFDS2R Register Descriptions

TOP:LRFDS2R:CFG

Address Offset 0x0000 0000
Physical Address 0x4008 5000 Instance 0x4008 5000
Description Sample2RAM Config Register
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 LAST0 When this bit is enabled, then the S2R will write all zeros, whenever it tries to write the stop address (instead of the regular value)
Value ENUM Name Description
0x0 DIS Writing all zeros to stop address is disabled
0x1 EN Writing all zeros to stop address is enabled
RW 0
4:3 TRIGMODE Trigger mode
Value ENUM Name Description
0x0 ONESHOT One shot mode, i.e. fill memory area once, from start to stop address, upon a manual trigger.
0x1 PERIODIC Periodic mode, i.e. fill memory area periodically, continuing at the start address after reaching the stop address, upon a manual trigger.
0x2 ONEVENT Trigger on event, i.e. fill memory area once, but wait for an event from the selected sample source.
RW 0b00
2:1 SEL Select sample source
Value ENUM Name Description
0x0 SYNTH Samples from frequency synthesizer's DTST interface.
0x1 ADCDIG Samples from ADCDIG.
0x2 FRONTEND Samples from frontend mux. The sample source is selected in LRFDMDM:DEMDEBUG.FRONTENDDEBUG register.
0x3 DECSTAGE Samples from decode stage mux. The sample source is selected in LRFDMDM:DEMDEBUG.DECSTAGEDEBUG register.
RW 0b00
0 CTL Sample2RAM module enable
Value ENUM Name Description
0x0 DIS Not enabled
0x1 EN Enabled
RW 0

TOP:LRFDS2R:START

Address Offset 0x0000 0004
Physical Address 0x4008 5004 Instance 0x4008 5004
Description Sample2RAM Start Address Register
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 ADDR Memory start address for where to dump the samples. The address is word oriented starting from the start of the MCERAM, then RFERAM, then PBERAM, then S2RRAM and then BUFRAM. Also note that S2R has write priority to the RAMs, so any attempt at simultaneously accessing the RAMs used by S2R while it is running may be unreliable (no arbitration/stall implemented), and should be avoided.

0 -> 1023 : MCERAM
1024 -> 2047 : RFERAM
2048 -> 3071 : PBERAM
3072 -> 4095 : S2RRAM
4096 -> 4479 : BUFRAM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDS2R:STOP

Address Offset 0x0000 0008
Physical Address 0x4008 5008 Instance 0x4008 5008
Description Sample2RAM Stop Address Register
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 ADDR Memory start address for where to dump the samples. The address is word oriented starting from the start of the MCERAM, then RFERAM, then PBERAM, then S2RRAM and then BUFRAM. Also note that S2R has write priority to the RAMs, so any attempt at simultaneously accessing the RAMs used by S2R while it is running may be unreliable (no arbitration/stall implemented), and should be avoided.

0 -> 1023 : MCERAM
1024 -> 2047 : RFERAM
2048 -> 3071 : PBERAM
3072 -> 4095 : S2RRAM
4096 -> 4479 : BUFRAM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDS2R:STAT

Address Offset 0x0000 000C
Physical Address 0x4008 500C Instance 0x4008 500C
Description Sample2RAM Status Register
Type RO
Bits Field Name Description Type Reset
31:28 RESERVED28 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
27:16 ADDRCNT Current address counter value
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RO 0xFFF
15:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
0 RUNNING S2R running status
Value ENUM Name Description
0x0 FALSE Not running
0x1 TRUE Running
RO 0

TOP:LRFDS2R:TRIG

Address Offset 0x0000 0010
Physical Address 0x4008 5010 Instance 0x4008 5010
Description Sample2RAM Trigger Register
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 TRIG Trigger a new sample capture (or arm it if the trigger mode is trigger on event)
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 ARM Trigger capture or arm module
WO 0


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