LRFDMDM

Instance: LRFDMDM
Component: LRFDMDM
Base address: 0x40082000


TOP:LRFDMDM Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

ENABLE

RW

32

0x0000 0000

0x0000 0000

0x4008 2000

FWSRC

RW

32

0x0000 0000

0x0000 0004

0x4008 2004

INIT

WO

32

0x0000 0000

0x0000 0008

0x4008 2008

DEMENABLE0

RW

32

0x0000 0000

0x0000 0010

0x4008 2010

DEMENABLE1

RW

32

0x0000 0000

0x0000 0014

0x4008 2014

DEMINIT0

WO

32

0x0000 0000

0x0000 0018

0x4008 2018

DEMINIT1

WO

32

0x0000 0000

0x0000 001C

0x4008 201C

STRB0

WO

32

0x0000 0000

0x0000 0020

0x4008 2020

STRB1

WO

32

0x0000 0000

0x0000 0024

0x4008 2024

EVT0

RO

32

0x0000 0000

0x0000 0028

0x4008 2028

EVT1

RO

32

0x0000 0000

0x0000 002C

0x4008 202C

EVT2

RO

32

0x0000 0000

0x0000 0030

0x4008 2030

EVTMSK0

RW

32

0x0000 0000

0x0000 0038

0x4008 2038

EVTMSK1

RW

32

0x0000 0000

0x0000 003C

0x4008 203C

EVTMSK2

RW

32

0x0000 0000

0x0000 0040

0x4008 2040

EVTCLR0

WO

32

0x0000 0000

0x0000 0048

0x4008 2048

EVTCLR1

WO

32

0x0000 0000

0x0000 004C

0x4008 204C

EVTCLR2

WO

32

0x0000 0000

0x0000 0050

0x4008 2050

PDREQ

RW

32

0x0000 0000

0x0000 0058

0x4008 2058

API

RO

32

0x0000 0000

0x0000 005C

0x4008 205C

CMDPAR0

RO

32

0x0000 0000

0x0000 0060

0x4008 2060

CMDPAR1

RO

32

0x0000 0000

0x0000 0064

0x4008 2064

CMDPAR2

RO

32

0x0000 0000

0x0000 0068

0x4008 2068

MSGBOX

RW

32

0x0000 0000

0x0000 006C

0x4008 206C

FREQ

RW

32

0x0000 0000

0x0000 0070

0x4008 2070

FIFOWR

RW

32

0x0000 0000

0x0000 0074

0x4008 2074

FIFORD

RO

32

0x0000 0000

0x0000 0078

0x4008 2078

FIFOWRCTRL

RW

32

0x0000 0000

0x0000 0080

0x4008 2080

FIFORDCTRL

RW

32

0x0000 0000

0x0000 0084

0x4008 2084

FIFOSTA

RO

32

0x0000 0000

0x0000 008C

0x4008 208C

RFEDATOUT0

RW

32

0x0000 0000

0x0000 0090

0x4008 2090

RFEDATIN0

RO

32

0x0000 0000

0x0000 0094

0x4008 2094

RFECMDOUT

RW

32

0x0000 0000

0x0000 0098

0x4008 2098

RFECMDIN

RO

32

0x0000 0000

0x0000 009C

0x4008 209C

PBEDATOUT0

RW

32

0x0000 0000

0x0000 00A0

0x4008 20A0

PBEDATIN0

RO

32

0x0000 0000

0x0000 00A4

0x4008 20A4

PBECMDOUT

RW

32

0x0000 0000

0x0000 00A8

0x4008 20A8

PBECMDIN

RO

32

0x0000 0000

0x0000 00AC

0x4008 20AC

LQIEST

RW

32

0x0000 0000

0x0000 00B0

0x4008 20B0

PBEEVTMUX

RW

32

0x0000 0000

0x0000 00B4

0x4008 20B4

SYSTIMEVTMUX0

RW

32

0x0000 0000

0x0000 00B8

0x4008 20B8

SYSTIMEVTMUX1

RW

32

0x0000 0000

0x0000 00BC

0x4008 20BC

ADCDIGCONF

RW

32

0x0000 0000

0x0000 00C0

0x4008 20C0

MODPRECTRL

RW

32

0x0000 0000

0x0000 00C4

0x4008 20C4

MODSYMMAP0

RW

32

0x0000 0000

0x0000 00C8

0x4008 20C8

MODSYMMAP1

RW

32

0x0000 0000

0x0000 00CC

0x4008 20CC

MODSOFTTX

RW

32

0x0000 0000

0x0000 00D0

0x4008 20D0

BAUD

RW

32

0x0000 0000

0x0000 00D4

0x4008 20D4

BAUDPRE

RW

32

0x0000 0000

0x0000 00D8

0x4008 20D8

MODMAIN

RW

32

0x0000 0000

0x0000 00DC

0x4008 20DC

DEMMISC0

RW

32

0x0000 0000

0x0000 00E0

0x4008 20E0

DEMMISC1

RW

32

0x0000 0000

0x0000 00E4

0x4008 20E4

DEMMISC2

RW

32

0x0000 0000

0x0000 00E8

0x4008 20E8

DEMMISC3

RW

32

0x0000 0000

0x0000 00EC

0x4008 20EC

DEMIQMC0

RW

32

0x0000 0000

0x0000 00F0

0x4008 20F0

DEMDSBU

RW

32

0x0000 0000

0x0000 00F4

0x4008 20F4

DEMCODC0

RW

32

0x0000 0000

0x0000 00F8

0x4008 20F8

DEMFIDC0

RW

32

0x0000 0000

0x0000 00FC

0x4008 20FC

DEMFEXB0

RW

32

0x0000 0000

0x0000 0100

0x4008 2100

DEMDSXB0

RW

32

0x0000 0000

0x0000 0104

0x4008 2104

DEMFIFE0

RW

32

0x0000 0000

0x0000 0108

0x4008 2108

DEMMAFI0

RW

32

0x0000 0000

0x0000 010C

0x4008 210C

DEMMAFI1

RW

32

0x0000 0000

0x0000 0110

0x4008 2110

DEMMAFI2

RW

32

0x0000 0000

0x0000 0114

0x4008 2114

DEMC1BE0

RW

32

0x0000 0000

0x0000 0118

0x4008 2118

DEMC1BE1

RW

32

0x0000 0000

0x0000 011C

0x4008 211C

DEMC1BE2

RW

32

0x0000 0000

0x0000 0120

0x4008 2120

SPARE0

RW

32

0x0000 0000

0x0000 0124

0x4008 2124

SPARE1

RW

32

0x0000 0000

0x0000 0128

0x4008 2128

SPARE2

RW

32

0x0000 0000

0x0000 012C

0x4008 212C

SPARE3

RW

32

0x0000 0000

0x0000 0130

0x4008 2130

DEMSWQU0

RW

32

0x0000 0000

0x0000 0134

0x4008 2134

DEMC1BEREF0

RW

32

0x0000 0000

0x0000 0138

0x4008 2138

DEMC1BEREF1

RW

32

0x0000 0000

0x0000 013C

0x4008 213C

DEMC1BEREF2

RW

32

0x0000 0000

0x0000 0140

0x4008 2140

DEMC1BEREF3

RW

32

0x0000 0000

0x0000 0144

0x4008 2144

MODCTRL

RW

32

0x0000 0000

0x0000 0148

0x4008 2148

MODPREAMBLE

RW

32

0x0000 0000

0x0000 014C

0x4008 214C

DEMFRAC0

RW

32

0x0000 0000

0x0000 0150

0x4008 2150

DEMFRAC1

RW

32

0x0000 0000

0x0000 0154

0x4008 2154

DEMFRAC2

RW

32

0x0000 0000

0x0000 0158

0x4008 2158

DEMFRAC3

RW

32

0x0000 0000

0x0000 015C

0x4008 215C

DEMCODC1

RW

32

0x0000 0000

0x0000 0160

0x4008 2160

DEMCODC2

RW

32

0x0000 0000

0x0000 0164

0x4008 2164

DEMFIDC1

RW

32

0x0000 0000

0x0000 0168

0x4008 2168

DEMFIDC2

RW

32

0x0000 0000

0x0000 016C

0x4008 216C

DEMFIFE1

RW

32

0x0000 0000

0x0000 0170

0x4008 2170

DEMMAFC0

RW

32

0x0000 0000

0x0000 0174

0x4008 2174

DEMMAFI4

RW

32

0x0000 0000

0x0000 0178

0x4008 2178

DEMSWIMBAL

RW

32

0x0000 0000

0x0000 017C

0x4008 217C

DEMSOFTPDIFF

RW

32

0x0000 0000

0x0000 0180

0x4008 2180

DEMDEBUG

RW

32

0x0000 0000

0x0000 0184

0x4008 2184

VITCTRL

RW

32

0x0000 0000

0x0000 0188

0x4008 2188

VITCOMPUTE

WO

32

0x0000 0000

0x0000 018C

0x4008 218C

VITAPMRDBACK

RO

32

0x0000 0000

0x0000 0190

0x4008 2190

VITSTATE

RO

32

0x0000 0000

0x0000 0194

0x4008 2194

VITBRMETRIC10

RW

32

0x0000 0000

0x0000 0198

0x4008 2198

VITBRMETRIC32

RW

32

0x0000 0000

0x0000 019C

0x4008 219C

VITBRMETRIC54

RW

32

0x0000 0000

0x0000 01A0

0x4008 21A0

VITBRMETRIC76

RW

32

0x0000 0000

0x0000 01A4

0x4008 21A4

TIMCTL

RW

32

0x0000 0000

0x0000 01E4

0x4008 21E4

TIMINC

RW

32

0x0000 0000

0x0000 01E8

0x4008 21E8

TIMPER

RW

32

0x0000 0000

0x0000 01EC

0x4008 21EC

TIMCNT

RO

32

0x0000 0000

0x0000 01F0

0x4008 21F0

TIMCAPT

RO

32

0x0000 0000

0x0000 01F4

0x4008 21F4

TIMEBASE

WO

32

0x0000 0000

0x0000 01F8

0x4008 21F8

COUNT1IN

RW

32

0x0000 0000

0x0000 01FC

0x4008 21FC

COUNT1RES

RO

32

0x0000 0000

0x0000 0200

0x4008 2200

BRMACC1

RO

32

0x0000 0000

0x0000 0208

0x4008 2208

BRMACC2

RO

32

0x0000 0000

0x0000 020C

0x4008 220C

MCETRCCTRL

WO

32

0x0000 0000

0x0000 0210

0x4008 2210

MCETRCSTAT

RO

32

0x0000 0000

0x0000 0214

0x4008 2214

MCETRCCMD

RW

32

0x0000 0000

0x0000 0218

0x4008 2218

MCETRCPAR0

RW

32

0x0000 0000

0x0000 021C

0x4008 221C

MCETRCPAR1

RW

32

0x0000 0000

0x0000 0220

0x4008 2220

RDCAPT0

WO

32

0x0000 0000

0x0000 0224

0x4008 2224

RDCAPT1

WO

32

0x0000 0000

0x0000 0228

0x4008 2228

FECAPT0

RW

32

0x0000 0000

0x0000 022C

0x4008 222C

FECAPT1

RW

32

0x0000 0000

0x0000 0230

0x4008 2230

DSCAPT0

RW

32

0x0000 0000

0x0000 0234

0x4008 2234

DSCAPT1

RW

32

0x0000 0000

0x0000 0238

0x4008 2238

DSCAPT2

RW

32

0x0000 0000

0x0000 023C

0x4008 223C

DSCAPT3

RW

32

0x0000 0000

0x0000 0240

0x4008 2240

DEMSWQU1

RW

32

0x0000 0000

0x0000 0244

0x4008 2244

GPOCTRL0

RW

32

0x0000 0000

0x0000 0248

0x4008 2248

GPOCTRL1

RW

32

0x0000 0000

0x0000 024C

0x4008 224C

RFERSSI

RO

32

0x0000 0000

0x0000 0250

0x4008 2250

RFEMAXRSSI

RO

32

0x0000 0000

0x0000 0254

0x4008 2254

RFEDBGAIN

RO

32

0x0000 0000

0x0000 0258

0x4008 2258

SYNC0

RO

32

0x0000 0000

0x0000 025C

0x4008 225C

SYNC1

RO

32

0x0000 0000

0x0000 0260

0x4008 2260

SYNC2

RO

32

0x0000 0000

0x0000 0264

0x4008 2264

SYNC3

RO

32

0x0000 0000

0x0000 0268

0x4008 2268

TOP:LRFDMDM Register Descriptions

TOP:LRFDMDM:ENABLE

Address Offset 0x0000 0000
Physical Address 0x4008 2000 Instance 0x4008 2000
Description Modem Enable Register
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 ADCDIG Enables the ADC Digital interface
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
4 DEMODULATOR Enables the Demodulator
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
3 MODULATOR Enables the Modulator
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
2 TIMEBASE Enables the Modem Timebase
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
1 TXRXFIFO Enables the TX/RX FIFO
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
0 TOPSM Enables the TOPsm (MCE)
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0

TOP:LRFDMDM:FWSRC

Address Offset 0x0000 0004
Physical Address 0x4008 2004 Instance 0x4008 2004
Description MCE program source select register
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 DATARAM Selects which RAM will be used for data storage
Value ENUM Name Description
0x0 MDMRAM Use MDMRAM for data
0x1 S2RRAM Use S2RRAM for data
RW 0
1 FWRAM Select which RAM we run FW from
Value ENUM Name Description
0x0 MDMRAM Run code from MDMRAM
0x1 S2RRAM Run code from S2RRAM
RW 0
0 BANK Sets the MSB of the address to the memory holding the program
Value ENUM Name Description
0x0 ZERO Run code from bank 0
0x1 ONE Run code from bank 1
RW 0

TOP:LRFDMDM:INIT

Address Offset 0x0000 0008
Physical Address 0x4008 2008 Instance 0x4008 2008
Description Modem Initialize Register
Type WO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 ADCDIG Synch reset ADC Digital interface
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
4 DEMODULATOR Synch reset Demodulator
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
3 MODULATOR Synch reset Modulator
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
2 TIMEBASE Synch reset Modem Timebase
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
1 TXRXFIFO Synch reset TX/RX FIFO
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
0 TOPSM Synch reset TOPsm (MCE)
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0

TOP:LRFDMDM:DEMENABLE0

Address Offset 0x0000 0010
Physical Address 0x4008 2010 Instance 0x4008 2010
Description Demodulator Enable Register 0
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 FRAC Enables the fractional resampler
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
7 FIDC Enables the fine DC estimator
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
6 CHFI Enables the channel filter
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
5 BDEC Enables the cascaded dec-by-2 stages (bde1 and bde2)
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
4 IQMC Enables the IQ mismatch compensation
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
3 MGE1 Enables the magnitude estimator engine #1
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
2 MGE0 Enables the magnitude estimator engine #0
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
1 CODC Enables the coarse DC estimator
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
0 CMIX Enables the N/1024 complex mixer
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0

TOP:LRFDMDM:DEMENABLE1

Address Offset 0x0000 0014
Physical Address 0x4008 2014 Instance 0x4008 2014
Description Demodulator Enable Register 1
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 VITE Enables the Viterbi module
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
12 MLSE Enables the MLSE module
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
11 SOFD Enables the soft decision module
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
10 SWQU Enables the sync word qualifier
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
9 MAFC Enables the manual frequency compensation module
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
8 MAFI Enables the matched filter
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
7 FIFE Enables the fine frequency offset estimator
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
6 PDIF Enables the phase differentiation
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
5 CA2P Enables the cart 2 polar conversion
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
4 C1BE Enables the correlation 1-bit engine
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
3 LQIE Enables the LQI engine
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
2 F4BA Enables the clock-domain crossing fifo
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
1 STIM Enables the symbol timing tracker
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0
0 DSBU Enables the dynamic sample buffer
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable module
RW 0

TOP:LRFDMDM:DEMINIT0

Address Offset 0x0000 0018
Physical Address 0x4008 2018 Instance 0x4008 2018
Description Demodulator Initialize Register 0
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 FRAC Synch reset fractional resampler
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
7 FIDC Synch reset fine DC estimator
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
6 CHFI Synch reset channel filter
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
5 BDEC Synch reset cascaded dec-by-2 stages (bde1 and bde2)
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
4 IQMC Synch reset IQ mismatch compensation
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
3 MGE1 Synch reset magnitude estimator engine #1
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
2 MGE0 Synch reset magnitude estimator engine #0
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
1 CODC Synch reset coarse DC estimator
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
0 CMIX Synch reset N/1024 complex mixer
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0

TOP:LRFDMDM:DEMINIT1

Address Offset 0x0000 001C
Physical Address 0x4008 201C Instance 0x4008 201C
Description Demodulator Initialize Register 1
Type WO
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 VITE Synch reset Viterbi Module
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
12 MLSE Synch reset MLSE module
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
11 SOFD Synch reset soft decision module
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
10 SWQU Synch reset sync word qualifyer
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
9 MAFC Synch reset manual frequency compensation module
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
8 MAFI Synch reset matched filter
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
7 FIFE Synch reset fine frequency offset estimator
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
6 PDIF Synch reset phase differentiation
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
5 CA2P Synch reset cart 2 polar conversion
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
4 C1BE Synch reset correlation 1-bit engine
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
3 LQIE Synch reset LQI engine
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
2 F4BA Synch reset clock-domain crossing fifo
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
1 STIM Synch reset symbol timing tracker
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0
0 DSBU Synch reset dynamic sample buffer
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESET Reset module
WO 0

TOP:LRFDMDM:STRB0

Address Offset 0x0000 0020
Physical Address 0x4008 2020 Instance 0x4008 2020
Description Modem Command Engine (MCE) Strobe Register 0
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 TIMBADVANCE Advance the timebase one 4baud sample, so the current symbol will have three 4baud samples.
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 ON The bit is 1
WO 0
10 TIMBSTALL Stall the timebase one 4baud sample, so the current symbol will have five 4baud samples.
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 ON The bit is 1
WO 0
9 EVT5 Firmware defined
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
8 EVT4 Firmware defined
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
7 MLSETERM Terminate MLSE unit
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
6 EVT3 Firmware defined
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 EVT2 Firmware defined SYSTIMER event 2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 EVT1 Firmware defined SYSTIMER event 1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 EVT0 Firmware defined SYSTIMER event 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 TIMBALIGN Align the 1baud to the next 4baud event
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 ON The bit is 1
WO 0
1 DSBURST Restart DSBU
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 RESTART Restart module
WO 0
0 CMDDONE Signal command done to CPE
Value ENUM Name Description
0x0 NO The bit is 0
0x1 YES The bit is 1
WO 0

TOP:LRFDMDM:STRB1

Address Offset 0x0000 0024
Physical Address 0x4008 2024 Instance 0x4008 2024
Description Modem Command Engine (MCE) Strobe Register 1
Type WO
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 S2RTRG Arm/Trigger the S2R module
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
12 DMATRG FW triggered DMA transfer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
11 SYSTCAPT2 Systimer capture event 2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
10 SYSTCAPT1 Systimer capture event 1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
9 SYSTCAPT0 Systimer capture event 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
8 C1BEPEAKAB Restart C1BE peak A and B search
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
7 C1BEPEAKC Restart C1BE peak C search (corr C is corr A+B combined = 64 symbols = 256 samples)
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 C1BEPEAKB Restart C1BE peak B search (32 symbols = 128 samples)
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 C1BEPEAKA Restart C1BE peak A search (32 symbols = 128 samples)
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 C1BEADVANCE Speed up correlator autocopy with one sample
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 C1BESTALL Slow down correlator autocopy with one sample
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2:1 C1BEROT Correlator rotate command to shift reg B
Value ENUM Name Description
0x0 ROT0 No additional rotation (normal shift-right mode)
0x1 ROT1R Rotate 1 sample to the right
0x2 ROT1L Rotate 1 sample to the left
0x3 ROT16R Rotate 16 samples to the right
WO 0b00
0 C1BECOPY Copy contents of shift reg A into shift reg B
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDMDM:EVT0

Address Offset 0x0000 0028
Physical Address 0x4008 2028 Instance 0x4008 2028
Description MCE Event Flag Register 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 PBEDAT New data from PBE received in PBEDATIN0 register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
14 PBECMD New command from PBE received in PBECMDIN register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
13 RFEDAT New data from RFE received in RFEDATIN0 register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
12 BDEC BDEC output enable event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
11 FRAC FRAC output enable event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
10 SYSTIMEVT2 Event 2 from SYSTIMER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
9 SYSTIMEVT1 Event 1 from SYSTIMER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
8 SYSTIMEVT0 Event 0 from SYSTIMER
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 FIFOWR A write to the modem FIFO (via FIFOWR register), probably by CPE.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 COUNTER Counter value reached in local timer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 RFECMD New command from RFE received in RFECMDIN register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 FIFOOVFL Modem FIFO overflow error event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 FIFOUNFL Modem FIFO underflow error event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 CLKEN4BAUD Clock enable event at 4 times baud rate
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 TIMER Timer period expired in local timer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 MDMAPI New command from PBE has been written in API register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDMDM:EVT1

Address Offset 0x0000 002C
Physical Address 0x4008 202C Instance 0x4008 202C
Description MCE Event Flag Register 1
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 REFCLK PLL REFCLK tick
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 S2RSTOP S2R module has written to the STOP_ADDRESS register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 SWQUFALSESYNC Sync word qualifier rejected sync due to bit errors (happens if a correlator event was incorrect due to noise).
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 SWQUSYNCED Sync word qualifier detected sync word
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 CLKENBAUDF Clock enable event at flushed baud rate
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 FIFORVALID Modem FIFO has valid data so a new word can be read from it, via FIFORD.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 FIFOWREADY Modem FIFO is ready for more data so a new word can be written to it, via FIFOWR register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 CLKENBAUD Clock enable event at baud rate
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 PREAMBLEDONE Preamble done interrupt from modulator
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDMDM:EVT2

Address Offset 0x0000 0030
Physical Address 0x4008 2030 Instance 0x4008 2030
Description MCE Event Flag Register 2
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 GPI1 External input event line GPI1 from IOC
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
14 GPI0 External input event line GPI0 from IOC. (Also, when loopback mode is enabled in DEMDEBUG.LOOPBACKMODE, this input line represents the symbols fed to the demodulator's decode stage).
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
12 C1BEBLOADED C1BE correlator B loaded (by auto-copy function)
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
11 C1BECMBANY C1BE correlator AB combined, any peak detect: (abs(corr A) > thr A) and (abs(corr B) > thr B). Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
10 C1BECMBNEG C1BE correlator AB combined, negative peak detect: (corr A < -thr A) and (corr B < -thr B). Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
9 C1BECMBPOS C1BE correlator AB combined, positive peak detect: (corr A > thr A) and (corr B > thr B). Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
8 C1BECANY C1BE correlator C, any peak detect: abs(corr C) > thr C. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 C1BECNEG C1BE correlator C, negative peak detect: corr C < -thr C. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 C1BECPOS C1BE correlator C, positive peak detect: corr C > thr C. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 C1BEBANY C1BE correlator B, any peak detect: abs(corr B) > thr B. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 C1BEBNEG C1BE correlator B, negative peak detect: corr B < -threshold B. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 C1BEBPOS C1BE correlator B, positive peak detect: corr B > threshold B. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 C1BEAANY C1BE correlator A, any peak detect: abs(corr A) > thr A. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 C1BEANEG C1BE correlator A, negative peak detect: corr A < -thr A. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 C1BEAPOS C1BE correlator A, positive peak detect: corr A > thr A. Event occurs one sample after actual peak.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDMDM:EVTMSK0

Address Offset 0x0000 0038
Physical Address 0x4008 2038 Instance 0x4008 2038
Description MCE Event Mask Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 PBEDAT Enable mask for event EVT0.PBEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
14 PBECMD Enable mask for event EVT0.PBECMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
13 RFEDAT Enable mask for event EVT0.RFEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
12 BDEC Enable mask for event EVT0.BDEC
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
11 FRAC Enable mask for event EVT0.FRAC
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
10 SYSTIMEVT2 Enable mask for event EVT0.SYSTIMEVT2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 SYSTIMEVT1 Enable mask for event EVT0.SYSTIMEVT1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 SYSTIMEVT0 Enable mask for event EVT0.SYSTIMEVT0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 FIFOWR Enable mask for event EVT0.FIFOWR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 COUNTER Enable mask for event EVT0.COUNTER
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 RFECMD Enable mask for event EVT0.RFECMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 FIFOOVFL Enable mask for event EVT0.FIFOOVFL
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 FIFOUNFL Enable mask for event EVT0.FIFOUNFL
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 CLKEN4BAUD Enable mask for event EVT0.CLKEN4BAUD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 TIMER Enable mask for event EVT0.TIMER
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 MDMAPI Enable mask for event EVT0.MDMAPI
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDMDM:EVTMSK1

Address Offset 0x0000 003C
Physical Address 0x4008 203C Instance 0x4008 203C
Description MCE Event Mask Register 1
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 REFCLK Enable mask for EVT1.REFCLK
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 S2RSTOP Enable mask for EVT1.S2RSTOP
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 SWQUFALSESYNC Enable mask for event EVT1.SWQUFALSESYNC
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 SWQUSYNCED Enable mask for event EVT1.SWQUSYNCED
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 CLKENBAUDF Enable mask for event EVT1.CLKENBAUDF
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 FIFORVALID Enable mask for event EVT1.FIFORVALID
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 FIFOWREADY Enable mask for event EVT1.FIFOWREADY
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 CLKENBAUD Enable mask for event EVT1.CLKENBAUD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 PREAMBLEDONE Enable mask for event EVT1.PREAMBLEDONE
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDMDM:EVTMSK2

Address Offset 0x0000 0040
Physical Address 0x4008 2040 Instance 0x4008 2040
Description MCE Event Mask Register 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 GPI1 Enable mask for event EVT2.GPI1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
14 GPI0 Enable mask for event EVT2.GPI0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
12 C1BEBLOADED Enable mask for event EVT2.C1BEBLOADED
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
11 C1BECMBANY Enable mask for event EVT2.C1BECMBANY
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
10 C1BECMBNEG Enable mask for event EVT2.C1BECMBNEG
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 C1BECMBPOS Enable mask for event EVT2.C1BECMBPOS
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 C1BECANY Enable mask for event EVT2.C1BECANY
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 C1BECNEG Enable mask for event EVT2.C1BECNEG
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 C1BECPOS Enable mask for event EVT2.C1BECPOS
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 C1BEBANY Enable mask for event EVT2.C1BEBANY
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 C1BEBNEG Enable mask for event EVT2.C1BEBNEG
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 C1BEBPOS Enable mask for event EVT2.C1BEBPOS
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 C1BEAANY Enable mask for event EVT2.C1BEAANY
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 C1BEANEG Enable mask for event EVT2.C1BEANEG
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 C1BEAPOS Enable mask for event EVT2.C1BEAPOS
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDMDM:EVTCLR0

Address Offset 0x0000 0048
Physical Address 0x4008 2048 Instance 0x4008 2048
Description MCE Event Clear Register 0
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 PBEDAT Clear event EVT0.PBEDAT
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
14 PBECMD Clear event EVT0.PBECMD
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
13 RFEDAT Clear event EVT0.RFEDAT
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
12 BDEC Clear event EVT0.BDEC
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
11 FRAC Clear event EVT0.FRAC
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
10 SYSTIMEVT2 Clear event EVT0.SYSTIMEVT2
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
9 SYSTIMEVT1 Clear event EVT0.SYSTIMEVT1
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
8 SYSTIMEVT0 Clear event EVT0.SYSTIMEVT0
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
7 FIFOWR Clear event EVT0.FIFOWR
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
6 COUNTER Clear event EVT0.COUNTER
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
5 RFECMD Clear event EVT0.RFECMD
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
4 FIFOOVFL Clear event EVT0.FIFOOVFL
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
3 FIFOUNFL Clear event EVT0.FIFOUNFL
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
2 CLKEN4BAUD Clear event EVT0.CLKEN4BAUD
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
1 TIMER Clear event EVT0.TIMER
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
0 MDMAPI Clear event EVT0.MDMAPI
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0

TOP:LRFDMDM:EVTCLR1

Address Offset 0x0000 004C
Physical Address 0x4008 204C Instance 0x4008 204C
Description MCE Event Clear Register 1
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 REFCLK Clear event EVT1.REFCLK
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
7 S2RSTOP Clear event EVT1.S2RSTOP
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
6 SWQUFALSESYNC Clear event EVT1.SWQUFALSESYNC
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
5 SWQUSYNCED Clear event EVT1.SWQUSYNCED
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
4 CLKENBAUDF Clear event EVT1.CLKENBAUDF
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
3 FIFORVALID Clear event EVT1.FIFORVALID
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
2 FIFOWREADY Clear event EVT1.FIFOWREADY
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
1 CLKENBAUD Clear event EVT1.CLKENBAUD
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
0 PREAMBLEDONE Clear event EVT1.PREAMBLEDONE
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0

TOP:LRFDMDM:EVTCLR2

Address Offset 0x0000 0050
Physical Address 0x4008 2050 Instance 0x4008 2050
Description MCE Event Clear Register 2
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 GPI1 Clear event EVT2.GPI1
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
14 GPI0 Clear event EVT2.GPI0
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
12 C1BEBLOADED Clear event EVT2.C1BEBLOADED
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
11 C1BECMBANY Clear event EVT2.C1BECMBANY
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
10 C1BECMBNEG Clear event EVT2.C1BECMBNEG
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
9 C1BECMBPOS Clear event EVT2.C1BECMBPOS
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
8 C1BECANY Clear event EVT2.C1BECANY
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
7 C1BECNEG Clear event EVT2.C1BECNEG
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
6 C1BECPOS Clear event EVT2.C1BECPOS
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
5 C1BEBANY Clear event EVT2.C1BEBANY
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
4 C1BEBNEG Clear event EVT2.C1BEBNEG
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
3 C1BEBPOS Clear event EVT2.C1BEBPOS
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
2 C1BEAANY Clear event EVT2.C1BEAANY
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
1 C1BEANEG Clear event EVT2.C1BEANEG
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
0 C1BEAPOS Clear event EVT2.C1BEAPOS
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0

TOP:LRFDMDM:PDREQ

Address Offset 0x0000 0058
Physical Address 0x4008 2058 Instance 0x4008 2058
Description Modem Power Down Request Register
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 TOPSMPDREQ Requests power-down for TOPsm core. If the TOPsm has an ongoing memory access, the hardware will safely gate the clock after the transaction has completed.
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0

TOP:LRFDMDM:API

Address Offset 0x0000 005C
Physical Address 0x4008 205C Instance 0x4008 205C
Description Modem API Command Register
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 PROTOCOLID Protocol ID
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0
3:0 MDMCMD Modem command
Value ENUM Name Description
0x0 ALLZEROS All bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDMDM:CMDPAR0

Address Offset 0x0000 0060
Physical Address 0x4008 2060 Instance 0x4008 2060
Description Modem API Command Parameter 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0, software defined function
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:CMDPAR1

Address Offset 0x0000 0064
Physical Address 0x4008 2064 Instance 0x4008 2064
Description Modem API Command Parameter 1
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1, software defined function
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:CMDPAR2

Address Offset 0x0000 0068
Physical Address 0x4008 2068 Instance 0x4008 2068
Description Modem API Command Parameter 2
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 2, software defined function
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:MSGBOX

Address Offset 0x0000 006C
Physical Address 0x4008 206C Instance 0x4008 206C
Description Modem Command Status Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Diverse status, error, report bits from MCE. Readable as well in PBE. Controlled by software.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:FREQ

Address Offset 0x0000 0070
Physical Address 0x4008 2070 Instance 0x4008 2070
Description Frequency Offset
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 OFFSET Frequency Offset from MCE, controlled by software
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:FIFOWR

Address Offset 0x0000 0074
Physical Address 0x4008 2074 Instance 0x4008 2074
Description Modem FIFO Write Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 PAYLOADIN FIFO write port. The actual port size is configurable in FIFOWRCTRL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:FIFORD

Address Offset 0x0000 0078
Physical Address 0x4008 2078 Instance 0x4008 2078
Description Modem FIFO Read Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 PAYLOADOUT FIFO read port. The actual port size is configurable in FIFORDCTRL
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:FIFOWRCTRL

Address Offset 0x0000 0080
Physical Address 0x4008 2080 Instance 0x4008 2080
Description Modem FIFO Write Configuration
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:4 FIFOWRPORT FIFO write port mapping
Value ENUM Name Description
0x0 MDMFIFOWR The FIFOWR register is used for write access
0x1 MODEM Modem has write access
0x2 PBE PBE has write access
RW 0b00
3:0 WORDSZWR Actual bits in every word write access
Value ENUM Name Description
0x0 BITS1 1 bit
0x1 BITS2 2 bits
0x2 BITS3 3 bits
0x3 BITS4 4 bits
0x4 BITS5 5 bits
0x5 BITS6 6 bits
0x6 BITS7 7 bits
0x7 BITS8 8 bits
0x8 BITS9 9 bits
0x9 BITS10 10 bits
0xA BITS11 11 bits
0xB BITS12 12 bits
0xC BITS13 13 bits
0xD BITS14 14 bits
0xE BITS15 15 bits
0xF BITS16 16 bits
RW 0x0

TOP:LRFDMDM:FIFORDCTRL

Address Offset 0x0000 0084
Physical Address 0x4008 2084 Instance 0x4008 2084
Description Modem FIFO Read Configuration
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:4 FIFORDPORT FIFO read port mapping
Value ENUM Name Description
0x0 MDMFIFORD The FIFORD register is used for read access
0x1 MODEM Modem has read access
0x2 PBE PBE has read access
RW 0b00
3:0 WORDSZRD Actual bits in every word read access
Value ENUM Name Description
0x0 BITS1 1 bit
0x1 BITS2 2 bits
0x2 BITS3 3 bits
0x3 BITS4 4 bits
0x4 BITS5 5 bits
0x5 BITS6 6 bits
0x6 BITS7 7 bits
0x7 BITS8 8 bits
0x8 BITS9 9 bits
0x9 BITS10 10 bits
0xA BITS11 11 bits
0xB BITS12 12 bits
0xC BITS13 13 bits
0xD BITS14 14 bits
0xE BITS15 15 bits
0xF BITS16 16 bits
RW 0x0

TOP:LRFDMDM:FIFOSTA

Address Offset 0x0000 008C
Physical Address 0x4008 208C Instance 0x4008 208C
Description Modem FIFO Status Flags
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 OVERFLOW FIFO overflow error. If this flag is asserted the modem FIFO must be re-initialized with INIT.TXRXFIFO to clear it. Note that re-initializing will flush the FIFO.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 ALMOSTFULL FIFO is almost full. Asserts when the FIFO fill level is above the almost full threshold.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 ALMOSTEMPTY FIFO is almost empty. Asserts when the FIFO fill level is below the almost empty threshold.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 UNDERFLOW FIFO underflow error. If this flag is asserted the modem FIFO must be re-initialized with INIT.TXRXFIFO to clear it.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 RXVALID A full data word is valid and can be read in FIFORD register read port.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 TXREADY The FIFOWR register write port is ready to receive a data word.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDMDM:RFEDATOUT0

Address Offset 0x0000 0090
Physical Address 0x4008 2090 Instance 0x4008 2090
Description MCE-to-RFE Send Data Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data to send to RFE. Writing to this register will trigger an event in the RFE, and the command value written here will be readable in LRFDRFE:MCEDATIN0 register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:RFEDATIN0

Address Offset 0x0000 0094
Physical Address 0x4008 2094 Instance 0x4008 2094
Description RFE-to-MCE Receive Data Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data received from RFE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:RFECMDOUT

Address Offset 0x0000 0098
Physical Address 0x4008 2098 Instance 0x4008 2098
Description MCE-to-RFE Send Command Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command to send to RFE. Writing to this register will trigger an event in the RFE, and the command value written here will be readable in LRFDRFE:MCECMDIN register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDMDM:RFECMDIN

Address Offset 0x0000 009C
Physical Address 0x4008 209C Instance 0x4008 209C
Description RFE-to-MCE Receive Command Register
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command received from RFE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDMDM:PBEDATOUT0

Address Offset 0x0000 00A0
Physical Address 0x4008 20A0 Instance 0x4008 20A0
Description MCE-to-PBE Send Data Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data to send to PBE. Writing to this register will trigger an event in the PBE, and the command value written here will be readable in LRFDPBE:MCEDATIN0 register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:PBEDATIN0

Address Offset 0x0000 00A4
Physical Address 0x4008 20A4 Instance 0x4008 20A4
Description PBE-to-MCE Receive Data Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data received from PBE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:PBECMDOUT

Address Offset 0x0000 00A8
Physical Address 0x4008 20A8 Instance 0x4008 20A8
Description MCE-to-PBE Send Command Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command to send to PBE. Writing to this register will trigger an event in the PBE, and the command value written here will be readable in LRFDPBE:MCECMDIN register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDMDM:PBECMDIN

Address Offset 0x0000 00AC
Physical Address 0x4008 20AC Instance 0x4008 20AC
Description PBE-to-MCE Receive Command Register
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command received from PBE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDMDM:LQIEST

Address Offset 0x0000 00B0
Physical Address 0x4008 20B0 Instance 0x4008 20B0
Description Link quality indicator
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL LQI Estimate value to PBE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:PBEEVTMUX

Address Offset 0x0000 00B4
Physical Address 0x4008 20B4 Instance 0x4008 20B4
Description PBE event mux
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:0 SEL Select one internal event and route to the PBE for usage in the event-unit there
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDMDM:SYSTIMEVTMUX0

Address Offset 0x0000 00B8
Physical Address 0x4008 20B8 Instance 0x4008 20B8
Description SYSTIME event mux 0
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:6 SEL1 Selects one source to send to the systimer output event 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
5:0 SEL0 Selects one source to send to the systimer output event 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDMDM:SYSTIMEVTMUX1

Address Offset 0x0000 00BC
Physical Address 0x4008 20BC Instance 0x4008 20BC
Description SYSTIME event mux 1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:0 SEL2 Selects one source to send to the systimer output event 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000

TOP:LRFDMDM:ADCDIGCONF

Address Offset 0x0000 00C0
Physical Address 0x4008 20C0 Instance 0x4008 20C0
Description ADC Digital Interface Configuration
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 QBRANCHEN Enables Q component data branch in ADCDIG
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
0 IBRANCHEN Enables I component data branch in ADCDIG
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0

TOP:LRFDMDM:MODPRECTRL

Address Offset 0x0000 00C4
Physical Address 0x4008 20C4 Instance 0x4008 20C4
Description Modulator Preamble Control
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 REPS Number of preamble repetitions of preamble pattern
Value ENUM Name Description
0x0 REPS1 1 repetition (i.e. only once)
0x1 REPS2 2 repetitions
0x2 REPS3 3 repetitions
0x3 REPS4 4 repetitions
0x4 REPS5 5 repetitions
0x5 REPS6 6 repetitions
0x6 REPS7 7 repetitions
0x7 REPS8 8 repetitions
0x8 REPS9 9 repetitions
0x9 REPS10 10 repetitions
0xA REPS11 11 repetitions
0xB REPS12 12 repetitions
0xC REPS13 13 repetitions
0xD REPS14 14 repetitions
0xE REPS15 15 repetitions
0xF REPS16 16 repetitions
RW 0x0
3:0 SIZE Preamble pattern size in bits
Value ENUM Name Description
0x3 BITS4 4 bits
0x7 BITS8 8 bits
0xF BITS16 16 bits
RW 0x0

TOP:LRFDMDM:MODSYMMAP0

Address Offset 0x0000 00C8
Physical Address 0x4008 20C8 Instance 0x4008 20C8
Description Modulator Symbol Mapping Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:12 SYM3 Decimal value for bits '11'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
11:8 SYM2 Decimal value for bits '10'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
7:4 SYM1 Decimal value for bit '1'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
3:0 SYM0 Decimal value for bit '0'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDMDM:MODSYMMAP1

Address Offset 0x0000 00CC
Physical Address 0x4008 20CC Instance 0x4008 20CC
Description Modulator Symbol Mapping Register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:12 SYM7 Decimal value for bits '111'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
11:8 SYM6 Decimal value for bits '110'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
7:4 SYM5 Decimal value for bits '101'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
3:0 SYM4 Decimal value for bits '100'
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDMDM:MODSOFTTX

Address Offset 0x0000 00D0
Physical Address 0x4008 20D0 Instance 0x4008 20D0
Description Modulator Soft Symbol Transmit
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 SOFTSYMBOL Soft symbol {-7..+7} used when MODCTRL.SOFTTXENABLE is enabled.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDMDM:BAUD

Address Offset 0x0000 00D4
Physical Address 0x4008 20D4 Instance 0x4008 20D4
Description Modem Baud Rate Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 RATEWORD Rate word (bits [20:5]). The 5 LSBs of the 21-bit rate word are defined in BAUDPRE.EXTRATEWORD register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:BAUDPRE

Address Offset 0x0000 00D8
Physical Address 0x4008 20D8 Instance 0x4008 20D8
Description Modem Baud Rate Prescaler Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:13 ALIGNVALUE Align value for timebase after sync
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RW 0b000
12:8 EXTRATEWORD Extended Rate Word (bits [4:0]). These are the 5 LSBs extending the 16 MSBs configured in BAUD.RATEWORD to form a 21 bit rate word.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
7:0 PRESCALER Prescaler value, range 1 to 255
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:MODMAIN

Address Offset 0x0000 00DC
Physical Address 0x4008 20DC Instance 0x4008 20DC
Description Modulator Main Config Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:2 FECSELECT Forward Error Correction Selection. Used for some signal-wiring in modulator and demodulator.
Value ENUM Name Description
0x0 NOSEL No FEC encoding selected
0x1 IEEE15_4 IEEE 802.15.4
0x2 RESERVED Reserved
0x3 BLR Bluetooth LE coded long range compatible FEC
RW 0b00
1:0 MODLEVELS Number of modulation levels
Value ENUM Name Description
0x0 LVL2 2 levels
0x1 LVL4 4 levels
0x2 LVL8 8 levels
RW 0b00

TOP:LRFDMDM:DEMMISC0

Address Offset 0x0000 00E0
Physical Address 0x4008 20E0 Instance 0x4008 20E0
Description Demodulator Config Register 0
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 CMIXN Signed factor of mixer phasor, Fmix=n*Fs/1024 , where n in range [-512, 511]
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDMDM:DEMMISC1

Address Offset 0x0000 00E4
Physical Address 0x4008 20E4 Instance 0x4008 20E4
Description Demodulator Config Register 1
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:8 CDCTGAINMA Gives the gain mantissa of the CDC P/Q tracker
Value ENUM Name Description
0x0 ALLZEROS When CDCTGAINMA is set to zero, the tracker loop is disabled.
0x1F ALLONES Maximum gain mantissa.
RW 0b0 0000
7:5 CDCTGAINEX Gives the gain exponent of the CDC P/Q tracker
Value ENUM Name Description
0x0 ALLZEROS When CDCTGAINEX is set to all zeroes, the CDCGAINMA multiplier is 4
0x7 ALLONES When CDCTGAINEX is set to all zeroes, the CDCGAINMA multiplier is 512
RW 0b000
4 CDCCOLRST Collision restart for CDC FIFO
Value ENUM Name Description
0x0 DIS Do not enable collision detect and restart feature
0x1 EN Enable collision detect and restart feature
RW 0
3:2 MGE1SRCSEL Source select magnitude estimator 1
Value ENUM Name Description
0x0 FIDC Output of the FIDC (x4 samples)
0x1 FEXB1 Output of the FEXB, as selected by DEMFEXB0.OUT2SRCSEL register
0x2 CHFI Output of CHFI
RW 0b00
1:0 CHFIBW Select bandwidth (cut-off frequency) of demodulator channel filter
Value ENUM Name Description
0x0 BW0_5 0.5 * Fs. Using FIR filter with taps [3 0 -9 0 20 0 -46 0 160 256 160 0 -46 0 20 0 -9 0 3].
0x1 BW0_3333 0.33333 * Fs. Using FIR filter with taps [0 4 6 0 -16 -25 0 65 138 170 138 65 0 -25 -16 0 6 4 0].
0x2 BW0_41667 0.41667 * Fs. Using FIR filter with taps [-1 -4 2 12 4 -25 -31 38 154 213 154 38 -31 -25 4 12 2 -4 -1].
0x3 BW0_29 0.29 * Fs. Using FIR filter with taps [2 3 1 -8 -18 -14 17 72 126 149 126 72 17 -14 -18 -8 1 3 2].
RW 0b00

TOP:LRFDMDM:DEMMISC2

Address Offset 0x0000 00E8
Physical Address 0x4008 20E8 Instance 0x4008 20E8
Description Demodulator Config Register 2
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 MLSERUN Enable maximum likelihood sequence estimation (MLSE) desicions
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
13:12 MAFCGAIN Set gain in MAFC. Multiplies symbols with 2^N before symbol recovery stage
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
11 STIMBYPASS Use to bypass STIM estimator
Value ENUM Name Description
0x0 DIS Perform both estimation and correct timing
0x1 EN Perform estimation only (no timing correction)
RW 0
10 STIMESTONLY Only perform symbol timing error estimation in STIM, without doing timing correction
Value ENUM Name Description
0x0 DIS Perform both estimation and correct timing
0x1 EN Perform estimation only (no timing correction)
RW 0
9:7 STIMTEAPERIOD Symbol timing error accumulator period (4 to 128 symbols) in STIM
Value ENUM Name Description
0x0 SYM4 4 symbols
0x1 SYM8 8 symbols
0x2 SYM16 16 symbols
0x3 SYM32 32 symbols
0x4 SYM64 64 symbols
0x5 SYM128 128 symbols
RW 0b000
6:4 STIMTEAGAIN Symbol timing error accumulator gain in STIM
Value ENUM Name Description
0x0 DIV512 Gain is 1/512
0x1 DIV256 Gain is 1/256
0x2 DIV128 Gain is 1/128
0x3 DIV64 Gain is 1/64
0x4 DIV32 Gain is 1/32
0x5 DIV16 Gain is 1/16
0x6 DIV8 Gain is 1/8
0x7 DIV4 Gain is 1/4
RW 0b000
3 PDIFLINPREDEN Enable linear predictor in PDIF at CORDIC output
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
2 PDIFDESPECK Enable despeckler in PDIF at CORDIC output
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 PDIFIQCONJEN Conjugate the complex I/Q signal in PDIF
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
0 PDIFLIMITRANGE Limit range on maximal PDIF output, i.e. instantaneous frequency sample
Value ENUM Name Description
0x0 DIS Allow full 8-bit range, i.e. +/- 128
0x1 EN Limit the range to 7-bit, i.e. +/- 64
RW 0

TOP:LRFDMDM:DEMMISC3

Address Offset 0x0000 00EC
Physical Address 0x4008 20EC Instance 0x4008 20EC
Description Demodulator Config Register 3
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14:13 BDE2DVGA DVGA settings for BDE2. The DVGA control for BDE2 is shared with the RFE in its LRFDRFE:GAINCTRL.BDE2DVGA register.
Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
Value ENUM Name Description
0x0 GAIN1 Gain 1
0x1 GAIN2 Gain 2
0x2 GAIN4 Gain 4
0x3 GAIN8 Gain 8
RW 0b00
12 BDE1FILTMODE BDE1 Filter only mode. When enabled, BDE1 lp filters in signal path, but no decimation occurs.
Value ENUM Name Description
0x0 DIV1 Decimate by 1 (no decimation)
0x1 DIV2 Decimate by 2
RW 0
11:10 LQIPERIOD LQI measurement period
Value ENUM Name Description
0x0 SYM16 16 symbols
0x1 SYM64 64 symbols
0x2 SYM256 256 symbols
0x3 SYM1024 1024 symbols
RW 0b00
9:8 BDE1DVGA DVGA settings for BDE1. The DVGA control for BDE1 is shared with the RFE in its LRFDRFE:GAINCTRL.BDE1DVGA register.
Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
Value ENUM Name Description
0x0 GAIN1 Gain 1
0x1 GAIN2 Gain 2
0x2 GAIN4 Gain 4
0x3 GAIN8 Gain 8
RW 0b00
7 BDE1NUMSTAGES BDE1 decimation filter setting
Value ENUM Name Description
0x0 DIV1 Decimate by 1 (no decimation)
0x1 DIV2 Decimate by 2
RW 0
6:5 PDIFDECIM Additional decimation in PDIF
Value ENUM Name Description
0x0 DIV1 No decimation
0x1 DIV2 Decimate by 2
0x2 DIV4 Decimate by 4
RW 0b00
4:0 BDE2DECRATIO BDE2 decimation filter setting
Value ENUM Name Description
0x0 DIV1 Decimate by 1 (no decimation)
0x1 DIV2 Decimate by 2
0x2 DIV4 Decimate by 4
0x3 DIV8 Decimate by 8
RW 0b0 0000

TOP:LRFDMDM:DEMIQMC0

Address Offset 0x0000 00F0
Physical Address 0x4008 20F0 Instance 0x4008 20F0
Description Demodulator I/Q Mismatch Compensation Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 GAINFACTOR Gain factor to compensate for unequal gains between the I and Q signal paths in the analog RF front-end.
The compensation is done by scaling the I path amplitude (no compensation of Q path).
The gain factor is given as an unsigned number in the range [0,255] corresponding to gain factor range [0,2],
where value 128 gives gain factor 1.0 (no gain). Any gain compensation is applied in a stage after the phase compensation.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 PHASEFACTOR Phase factor to compensate for unorthogonal I and Q signals.
The phase factor is given as a signed number in the range [-128,127] corresponding to phase factor range [-0.5, 0.496],
where the phase factor can be calculated as phase_factor = tan(phase_error).
This gives an available phase error compensation range of [-26.6, 26.4] degrees.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMDSBU

Address Offset 0x0000 00F4
Physical Address 0x4008 20F4 Instance 0x4008 20F4
Description Dynamic Sample Buffer Config Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 DSBUAVGLENGTH Length for moving average of the newest DSBU samples.
The buffer can hold up to 256 samples. Length of 255 is maximum.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 DSBUDELAY Output delay from sample buffer, as offset between write and read pointers.
The buffer can hold up to 256 samples. Delay of 0 means maximum.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMCODC0

Address Offset 0x0000 00F8
Physical Address 0x4008 20F8 Instance 0x4008 20F8
Description Demodulator Coarse DC Offset Estimator Register 0
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 ESTSEL Select which estimator to show as readable output
Value ENUM Name Description
0x0 ACC Read back latest accumulator estimate
0x1 IIR Read back latest IIR estimate
RW 0
10:9 COMPSEL Select estimator to use for coarse DC offset compensation
Value ENUM Name Description
0x0 MANUAL Use manually programmable values from DEMCODC1 registers
0x2 ACC Compensate with latest accumulator estimate
0x3 IIR Compensate with latest IIR estimate
RW 0b00
8 IIRUSEINITIAL When enabled, a configurable value is loaded to initialize IIR filter when CODC estimator is re-initialized.
Value ENUM Name Description
0x0 DIS Initialize IIR filter with value zero
0x1 EN Use the manual compensation values in DEMCODC1 for initialization
RW 0
7:5 IIRGAIN Adjust first-order IIR filter adaptation which controls filter bandwidth.
Value ENUM Name Description
0x0 OFF Filter disabled
0x1 DIV16 Use 1/16 IIR adaptation
0x2 DIV32 Use 1/32 IIR adaptation
0x3 DIV64 Use 1/64 IIR adaptation
0x4 DIV128 Use 1/128 IIR adaptation
0x5 DIV256 Use 1/256 IIR adaptation
0x6 DIV512 Use 1/512 IIR adaptation
0x7 DIV1024 Use 1/1024 IIR adaptation
RW 0b000
4 IIREN Enable first-order IIR filter inside CODC
Value ENUM Name Description
0x0 OFF Disable IIR estimator
0x1 ON Enable IIR estimator
RW 0
3 ACCMODE Accumulator estimator mode
Value ENUM Name Description
0x0 SINGLE Generate a single DC estimate only, then stop
0x1 CONT Generate new DC estimates continuously
RW 0
2:1 ACCPERIOD Integration period for accumulator estimator
Value ENUM Name Description
0x0 SMPL8 8 samples
0x1 SMPL32 32 samples
0x2 SMPL128 128 samples
0x3 SMPL512 512 samples
RW 0b00
0 ACCEN Enable accumulator based estimator inside CODC
Value ENUM Name Description
0x0 OFF Disable accumulator estimator
0x1 ON Enable accumulator estimator
RW 0

TOP:LRFDMDM:DEMFIDC0

Address Offset 0x0000 00FC
Physical Address 0x4008 20FC Instance 0x4008 20FC
Description Demodulator Fine DC Offset Estimator Register 0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:4 COMPSEL Select estimator to use for fine DC offset compensation
Value ENUM Name Description
0x0 MANUAL Use manually programmable values from DEMFIDC1 registers
0x2 ACC Compensate with latest accumulator estimate
RW 0b00
3:2 ACCPERIOD Integration period for accumulator estimator
Value ENUM Name Description
0x0 SMPL8 8 samples
0x1 SMPL32 32 samples
0x2 SMPL128 128 samples
0x3 SMPL512 512 samples
RW 0b00
1 ACCMODE Accumulator estimator mode
Value ENUM Name Description
0x0 SINGLE Generate a single DC estimate only, then stop
0x1 CONT Generate new DC estimates continuously
RW 0
0 ACCEN Enable accumulator based estimator inside FIDC
Value ENUM Name Description
0x0 OFF Disable accumulator estimator
0x1 ON Enable accumulator estimator
RW 0

TOP:LRFDMDM:DEMFEXB0

Address Offset 0x0000 0100
Physical Address 0x4008 2100 Instance 0x4008 2100
Description Demodulator Front-End Crossbar Register 0
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 OUT2PASSTHROUGH Front-end crossbar output #2 is direct passthrough of the crossbar input
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
12:11 OUT2SRCSEL Source select for XBAR output #2 (towards magnitude estimation engine MGE0)
Value ENUM Name Description
0x0 CODC Source is coarse DC remover (CODC)
0x1 CMIX Source is complex N*Fs/1024 mixer (CMIX)
0x2 BDE1 Source is complex N*Fs/1024 mixer (CMIX)
RW 0b00
10 OUT1PASSTHROUGH Front-end crossbar output #1 is direct passthrough of the crossbar input
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
9:8 OUT1SRCSEL Source select for XBAR output #1 (main output, towards BDE2 and rest of demodulator)
Value ENUM Name Description
0x0 CODC Source is coarse DC remover (CODC)
0x1 CMIX Source is complex N*Fs/1024 mixer (CMIX)
0x2 BDE1 Source is complex N*Fs/1024 mixer (CMIX)
RW 0b00
7:6 B4SRCSEL Not used
Value ENUM Name Description
0x0 ZEROS Source is complex N*Fs/1024 mixer (ZEROS)
0x3 ONES Source is complex N*Fs/1024 mixer (ONES)
RW 0b00
5:4 B3SRCSEL Source select for BDE1 (XBAR block #3)
Value ENUM Name Description
0x0 INPUT Source is crossbar main input
0x1 CODC Source is complex N*Fs/1024 mixer (CMIX)
0x2 CMIX Source is complex N*Fs/1024 mixer (CMIX)
RW 0b00
3:2 B2SRCSEL Source select for CMIX (XBAR block #2)
Value ENUM Name Description
0x0 INPUT Source is crossbar main input
0x1 CODC Source is coarse DC remover (CODC)
0x2 BDE1 Source is coarse DC remover (CODC)
RW 0b00
1:0 B1SRCSEL Source select for CODC (XBAR block #1)
Value ENUM Name Description
0x0 INPUT Source is crossbar main input
0x1 CMIX Source is complex N*Fs/1024 mixer (CMIX)
0x2 BDE1 Source is complex N*Fs/1024 mixer (CMIX)
RW 0b00

TOP:LRFDMDM:DEMDSXB0

Address Offset 0x0000 0104
Physical Address 0x4008 2104 Instance 0x4008 2104
Description Demodulator Decode Stage Crossbar Register 0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 OUT2PASSTHROUGH Crossbar output #2 is direct passthrough of the crossbar input
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
4 OUT1PASSTHROUGH Crossbar output #1 is direct passthrough of the crossbar input
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
3 OUTSRCSEL2 Source select XBAR output, branch 1 (baud branch)
Value ENUM Name Description
0x0 FIFE Source is fine frequency offset estimator (FIFE)
0x1 MAFI Source is matched filter (MAFI)
RW 0
2 OUTSRCSEL1 Source select for XBAR output, branch 2 (flushed branch)
Value ENUM Name Description
0x0 FIFE Source is fine frequency offset estimator (FIFE)
0x1 MAFI Source is matched filter (MAFI)
RW 0
1 B2SRCSEL Source select for MAFI (XBAR block #2)
Value ENUM Name Description
0x0 INPUT Source is crossbar main input
0x1 FIFE Source is fine frequency offset estimator (FIFE)
RW 0
0 B1SRCSEL Source select for FIFE (XBAR block #1)
Value ENUM Name Description
0x0 INPUT Source is crossbar main input
0x1 MAFI Source is matched filter (MAFI)
RW 0

TOP:LRFDMDM:DEMFIFE0

Address Offset 0x0000 0108
Physical Address 0x4008 2108 Instance 0x4008 2108
Description Demodulator Fine Frequency Offset Estimator Register 0
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 FINEFOESEL Select which estimator to show as readable output
Value ENUM Name Description
0x0 IIR Latest IIR estimate
0x1 ACC Latest accumulator estimate
RW 0
10:9 FOCFFSEL Select which estimate source to be used in feed-forward compensation point
Value ENUM Name Description
0x0 IIR Compensate with latest IIR estimate
0x1 ACC Compensate with latest accumulator estimate
0x2 MANUAL Use programmable manual value from register bank. (Note: an input register is not implemented, so the manual compensation value is tied to '0')
RW 0b00
8 ACCCNTMODE Accumulator estimator mode
Value ENUM Name Description
0x0 SINGLE Generate a single frequency offset estimate only, then stop
0x1 CONT Generate new frequency offset estimates continuously
RW 0
7:6 ACCPERIOD Integration period for accumulator
Value ENUM Name Description
0x0 PER64 64 samples
0x1 PER128 128 samples
0x2 PER256 256 samples
0x3 PER512 512 samples
RW 0b00
5 ACCEN Enable accumulator based frequency offset estimator inside FIFE
Value ENUM Name Description
0x0 OFF Disable accumulator estimator
0x1 ON Enable accumulator estimator
RW 0
4 IIRUSEINITIAL When enabled, a configurable value is loaded to initialize IIR filter when FIFE estimator is re-initialized.
Value ENUM Name Description
0x0 DIS Initialize IIR filter with value zero
0x1 EN Use the manual compensation value in DEMFIFE1 for initialization
RW 0
3:1 IIRGAIN Adjust first-order IIR filter adaptation which controls filter bandwidth
Value ENUM Name Description
0x0 OFF Filter disabled
0x1 DIV16 Use 1/16 IIR adaptation
0x2 DIV32 Use 1/32 IIR adaptation
0x3 DIV64 Use 1/64 IIR adaptation
0x4 DIV128 Use 1/128 IIR adaptation
0x5 DIV256 Use 1/256 IIR adaptation
0x6 DIV512 Use 1/512 IIR adaptation
0x7 DIV1024 Use 1/1024 IIR adaptation
RW 0b000
0 IIREN Enable first-order IIR filter based freq offset estimator inside FIFE
Value ENUM Name Description
0x0 OFF Disable IIR estimator
0x1 ON Enable IIR estimator
RW 0

TOP:LRFDMDM:DEMMAFI0

Address Offset 0x0000 010C
Physical Address 0x4008 210C Instance 0x4008 210C
Description Demodulator Matched Filter Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 C1C7 Filter coefficient c1 (and c7)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 C0C8 Filter coefficient c0 (and c8)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMMAFI1

Address Offset 0x0000 0110
Physical Address 0x4008 2110 Instance 0x4008 2110
Description Demodulator Matched Filter Register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 C3C5 Filter coefficient c3 (and c5)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 C2C6 Filter coefficient c2 (and c6)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMMAFI2

Address Offset 0x0000 0114
Physical Address 0x4008 2114 Instance 0x4008 2114
Description Demodulator Matched Filter Register 2
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8:0 C4 Filter coefficient c4. The matched filter will have unity gain when the sum of all coefficients c0 to c8 equals 512.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FF ALLONES All the bits are 1
RW 0b0 0000 0000

TOP:LRFDMDM:DEMC1BE0

Address Offset 0x0000 0118
Physical Address 0x4008 2118 Instance 0x4008 2118
Description Demodulator Correlator 1-bit Engine Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:11 MASKB Mask for correlator B to select the correlator length to use.
The number specifies number of nibbles (i.e. 4-bit block, which typically corresponds to one symbol)
of the correlator holding the oldest samples that will be ignored in computations.
When set to zero, the full 128 sample (=32 symbol) correlator length will be used.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
10:6 MASKA Mask for correlator A to select the correlator length to use.
The number specifies number of nibbles (i.e. 4-bit block, which typically corresponds to one symbol)
of the correlator holding the oldest samples that will be ignored in computations.
When set to zero, the full 128 sample (=32 symbol) correlator length will be used.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
5:4 CASCCONF Correlator cascade configuration
Value ENUM Name Description
0x0 SINGLE Correlator B not used
0x1 SERIAL Connect correlators in series (A -> B)
0x2 PARALLEL Connect correlators in parallel
RW 0b00
3:0 COPYCONF Control auto copy of contents from corr A to corr B
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDMDM:DEMC1BE1

Address Offset 0x0000 011C
Physical Address 0x4008 211C Instance 0x4008 211C
Description Demodulator Correlator 1-bit Engine Register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 THRESHOLDB Correlation threshold value for correlator B
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 THRESHOLDA Correlation threshold value for correlator A
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMC1BE2

Address Offset 0x0000 0120
Physical Address 0x4008 2120 Instance 0x4008 2120
Description Demodulator Correlator 1-bit Engine Register 2
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 PARLOADCONF Configuration to control peak event generation (applies to correlators A, B, D, E)
Value ENUM Name Description
0x0 ATOB Trigger peak event on all peaks above threshold
0x1 ATOD Trigger peak event only if peak is highest in correlator since search start
RW 0
9:8 PEAKCONF Configuration to control peak event generation (applies to correlators A, B, D, E)
Value ENUM Name Description
0x0 THRESH Trigger peak event on all peaks above threshold
0x1 BEST Trigger peak event only if peak is highest in correlator since search start
0x2 BESTAB Trigger peak event for combined highest peak search for corr "A and B" and "D and E" in pairs
RW 0b00
7:0 THRESHOLDC Correlation threshold value for correlator C (corr C is A+B concatenated)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:SPARE0

Address Offset 0x0000 0124
Physical Address 0x4008 2124 Instance 0x4008 2124
Description Modem Spare 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:SPARE1

Address Offset 0x0000 0128
Physical Address 0x4008 2128 Instance 0x4008 2128
Description Modem Spare 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:SPARE2

Address Offset 0x0000 012C
Physical Address 0x4008 212C Instance 0x4008 212C
Description Modem Spare 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:SPARE3

Address Offset 0x0000 0130
Physical Address 0x4008 2130 Instance 0x4008 2130
Description Modem Spare 3
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Spare register for use by firmware
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMSWQU0

Address Offset 0x0000 0134
Physical Address 0x4008 2134 Instance 0x4008 2134
Description Demodulator Sync Word Qualifier Register 0
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 SYNCMODE 0: Search for A and B in parallell
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
6 AUTOMAFC Let sync word qualifier automatically control the manual frequency offset compensation (MAFC) block when it is running.
Value ENUM Name Description
0x0 OFF Keep manual control over MAFC
0x1 ON Give control to sync word qualifier
RW 0
5 RUN Start/stop sync word qualifier.
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
4:0 REFLEN Bit length of sync word qualifier reference vector, constituted by (reflen + 1) most significant bits of sync word A and/or B.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000

TOP:LRFDMDM:DEMC1BEREF0

Address Offset 0x0000 0138
Physical Address 0x4008 2138 Instance 0x4008 2138
Description Correlator reference register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CAR15C0 Corr A reference bits 15:0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMC1BEREF1

Address Offset 0x0000 013C
Physical Address 0x4008 213C Instance 0x4008 213C
Description Correlator reference register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CAR31C16 Corr A reference bits 31:16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMC1BEREF2

Address Offset 0x0000 0140
Physical Address 0x4008 2140 Instance 0x4008 2140
Description Correlator reference register 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CBR15C0 Corr B reference bits 15:0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMC1BEREF3

Address Offset 0x0000 0144
Physical Address 0x4008 2144 Instance 0x4008 2144
Description Correlator reference register 3
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CBR31C16 Corr B reference bits 31:16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:MODCTRL

Address Offset 0x0000 0148
Physical Address 0x4008 2148 Instance 0x4008 2148
Description Dynamic Modem Control Signals from MCE
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 DSBUSEL Select DSBU input source. It is not valid anymore. This bitfield is reserved for future use.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
10 HDISMODE Enable Hilbert discriminator mode for data descicion
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 PARBITQUALEN Enable Parallel Bit Qualifier (read DEMC1BEA)
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
8:7 STIMMODE Controls STIM module for different modes
Value ENUM Name Description
0x0 NORMAL Normal Mode
0x1 LATE STIM starts late
0x2 EARLY STIM starts early
RW 0b00
6 C1BEMODE Controls the C1BE mode
Value ENUM Name Description
0x0 NORMAL Normal mode
0x1 EARLYLATE Set the C1BE in special early/late mode
RW 0
5 SOFTPDIFFMODE Enable Soft PDIFF mode for RX
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 SOFTTXENABLE Enable SOFT TX mode, controlled via MODSOFTTX
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
3 FECENABLE Global FEC modes enable
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
2 FEC5TERMINATE Goes into termination mode in 5Mbps TX FEC. This bitfield is not valid anymore.
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0
1 TONEINSERT Inserts a tone
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 PREAMBLEINSERT Inserts preamble
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDMDM:MODPREAMBLE

Address Offset 0x0000 014C
Physical Address 0x4008 214C Instance 0x4008 214C
Description Dynamic Modulator Preamble Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 WORD 16 bit preamble word pattern. The LSB is transmitted first
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMFRAC0

Address Offset 0x0000 0150
Physical Address 0x4008 2150 Instance 0x4008 2150
Description Demodulator Fractional Resampler Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 P15C0 Downsampler P[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q.
The hardware requires the resampling factor P/Q to be in the range [1/4, 1],
i.e. only down-sampling with a factor in the range [1,4] is supported.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMFRAC1

Address Offset 0x0000 0154
Physical Address 0x4008 2154 Instance 0x4008 2154
Description Demodulator Fractional Resampler Register 1
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:0 P27C16 Downsampler P[27:16]
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RW 0x000

TOP:LRFDMDM:DEMFRAC2

Address Offset 0x0000 0158
Physical Address 0x4008 2158 Instance 0x4008 2158
Description Demodulator Fractional Resampler Register 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 Q15C0 Downsampler Q[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q.
The hardware requires the resampling factor P/Q to be in the range [1/4, 1],
i.e. only down-sampling with a factor in the range [1,4] is supported.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:DEMFRAC3

Address Offset 0x0000 015C
Physical Address 0x4008 215C Instance 0x4008 215C
Description Demodulator Fractional Resampler Register 3
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:0 Q27C16 Downsampler Q[27:16]
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFF ALLONES All the bits are 1
RW 0x000

TOP:LRFDMDM:DEMCODC1

Address Offset 0x0000 0160
Physical Address 0x4008 2160 Instance 0x4008 2160
Description Demodulator Coarse DC Offset Estimator Register 1
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 COMPIVAL Compensation value, I branch
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDMDM:DEMCODC2

Address Offset 0x0000 0164
Physical Address 0x4008 2164 Instance 0x4008 2164
Description Demodulator Coarse DC Offset Estimator Register 2
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 COMPQVAL Compensation value, Q branch
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDMDM:DEMFIDC1

Address Offset 0x0000 0168
Physical Address 0x4008 2168 Instance 0x4008 2168
Description Demodulator Fine DC Offset Estimator Register 1
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 COMPIVAL Compensation value for I path
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDMDM:DEMFIDC2

Address Offset 0x0000 016C
Physical Address 0x4008 216C Instance 0x4008 216C
Description Demodulator Fine DC Offset Estimator Register 2
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 COMPQVAL Compensation value for Q path
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDMDM:DEMFIFE1

Address Offset 0x0000 0170
Physical Address 0x4008 2170 Instance 0x4008 2170
Description Demodulator Fine Frequency Offset Estimator Register 1
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 FOCFBREGVAL Value for feed-back compensation point (signed)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMMAFC0

Address Offset 0x0000 0174
Physical Address 0x4008 2174 Instance 0x4008 2174
Description Demodulator Manual Frequency Compensation Register 0
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 COMPVAL Value for manual compensation (signed)
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMMAFI4

Address Offset 0x0000 0178
Physical Address 0x4008 2178 Instance 0x4008 2178
Description Demodulator Matched Filter Register 4
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 TERMVAL Input value to terminate matched filter with. Writing to this register triggers the termination.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMSWIMBAL

Address Offset 0x0000 017C
Physical Address 0x4008 217C Instance 0x4008 217C
Description Demodulator Sync Word DC Imbalance Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 IMBALB DC imbalance in sync word B, applied via SWQU upon C1BE correlator A peak event
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 IMBALA DC imbalance in sync word A, applied via SWQU upon C1BE correlator B peak event
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMSOFTPDIFF

Address Offset 0x0000 0180
Physical Address 0x4008 2180 Instance 0x4008 2180
Description Demodulator Soft PDIFF Value Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Replaces PDIFF output when in Soft PDIFF Mode. Can be used for manually feeding samples (e.g. on-off-keying (OOK) samples from RFE) into the demodulator decode stage.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMDEBUG

Address Offset 0x0000 0184
Physical Address 0x4008 2184 Instance 0x4008 2184
Description Demodulator Debug Register
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:9 LOOPBACKPIN Choose which GPI pin is connected to loopback
Value ENUM Name Description
0x0 GPI0 GPI0 connected to loopback
0x1 GPI1 GPI1 connected to loopback
0x2 GPI2 GPI2 connected to loopback
0x3 GPI3 GPI3 connected to loopback
0x4 GPI4 GPI4 connected to loopback
0x5 GPI5 GPI5 connected to loopback
0x6 GPI6 GPI6 connected to loopback
0x7 GPI7 GPI7 connected to loopback
RW 0b000
8 DECSTAGETRIGGER Set high to trigger event to S2R module. Need to be written low again (no HW clear)
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
7:5 DECSTAGEDEBUG Selects which decode stage signal source to dump for debugging via S2R module.
The decode stage samples are signed 8-bit samples,
packed into 32-bit words with the oldest sample as the most significant byte.
Value ENUM Name Description
0x0 NOSEL No source selected
0x1 PDIF Dump PDIF output samples
0x2 FIFE Dump PDIF output samples
0x3 MAFI Dump MAFI output samples
0x4 C1BE Dump C1BE correlator A value (truncated to 8 LSBs only, may overflow if correlator value is +128).
0x5 MAFC Dump MAFC output samples
0x6 STIM Dump STIM output samples
0x7 SOFD Dump SOFD output samples
RW 0b000
4 FRONTENDTRIGGER Set high to trigger event to S2R module. Need to be written low again (no HW clear)
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
3:1 FRONTENDDEBUG Selects which front-end stage signal source to dump for debugging via S2R module.
The front-end stage samples are signed 16-bit samples from both I and Q signal path,
packed together into 32-bit words with the I sample as the 16 MSB and Q sample as the 16 LSB.
Value ENUM Name Description
0x0 NOSEL No source selected
0x1 IQMC Dump IQMC output samples
0x2 BDE1 Dump BDE1 output samples
0x3 FEXB2 Dump FEXB output #2 samples, as selected by DEMFEXB0.OUT2SRCSEL register
0x4 BDE2 Dump BDE2 output samples
0x5 CHFI Dump CHFI output samples
0x6 FRAC Dump FRAC output samples
0x7 FIDC Dump FRAC output samples
RW 0b000
0 LOOPBACKMODE Enables loopback mode
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0

TOP:LRFDMDM:VITCTRL

Address Offset 0x0000 0188
Physical Address 0x4008 2188 Instance 0x4008 2188
Description Viterbi Control Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:6 METRSEL Selects which HW module is connected to viterbi decoder
Value ENUM Name Description
0x0 MET5M Use 5Mbps Metrics
0x1 PHAC Use PHAC Metrics
0x2 SOFD Use SOFD Metrics
0x3 MLSE Use MLSE Metrics
RW 0b00
5:2 APMRDBACKSEL Selects the APM to read back via VITAPMRDBACK register.
Value ENUM Name Description
0x0 NOSEL No selection
0x8 APM0 View APM 0
0x9 APM1 View APM 1
0xA APM2 View APM 2
0xB APM3 View APM 3
0xC APM4 View APM 4
0xD APM5 View APM 5
0xE APM6 View APM 6
0xF APM7 View APM 7
RW 0x0
1 ACSITERATIONS Number of iterations per ACS element
Value ENUM Name Description
0x0 CODE12 2 iterations per ACS (2 branches, 1/2 codes)
0x1 CODE23 4 iterations per ACS (4 branches, 2/3 codes)
RW 0
0 METRICS Select Metrics
Value ENUM Name Description
0x0 HW Use HW metrics as defined by VITCTRL.METRSEL bits
0x1 SOFT Use soft Metrics (register based)
RW 0

TOP:LRFDMDM:VITCOMPUTE

Address Offset 0x0000 018C
Physical Address 0x4008 218C Instance 0x4008 218C
Description Viterbi Compute Register
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 START Initiates a compute cycle
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDMDM:VITAPMRDBACK

Address Offset 0x0000 0190
Physical Address 0x4008 2190 Instance 0x4008 2190
Description Viterbi APM Readback Register
Type RO
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 VALUE APM for element i (selected in VITCTRL register).
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RO 0b00 0000 0000

TOP:LRFDMDM:VITSTATE

Address Offset 0x0000 0194
Physical Address 0x4008 2194 Instance 0x4008 2194
Description Viterbi State Register
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 VALUE Current Winning State
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x7 ALLONES All the bits are 1
RO 0b000

TOP:LRFDMDM:VITBRMETRIC10

Address Offset 0x0000 0198
Physical Address 0x4008 2198 Instance 0x4008 2198
Description Viterbi Branch Metric 1 and 0 Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 MET1 Branch Metric 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 MET0 Branch Metric 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:VITBRMETRIC32

Address Offset 0x0000 019C
Physical Address 0x4008 219C Instance 0x4008 219C
Description Viterbi Branch Metric 3 and 2 Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 MET3 Branch Metric 3
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 MET2 Branch Metric 2
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:VITBRMETRIC54

Address Offset 0x0000 01A0
Physical Address 0x4008 21A0 Instance 0x4008 21A0
Description Viterbi Branch Metric 5 and 4 Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 MET5 Branch Metric 5
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 MET4 Branch Metric 4
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:VITBRMETRIC76

Address Offset 0x0000 01A4
Physical Address 0x4008 21A4 Instance 0x4008 21A4
Description Viterbi Branch Metric 7 and 6 Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 MET7 Branch Metric 7
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 MET6 Branch Metric 6
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:TIMCTL

Address Offset 0x0000 01E4
Physical Address 0x4008 21E4 Instance 0x4008 21E4
Description Modem Timer and Counter Control Register
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:8 CPTSRC Selects bit number from event bus for a counter capture. Event number in range 0 to 63
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3F ALLONES All the bits are 1
RW 0b00 0000
7 CPTCTL Enable counter capture on event. Upon a capture event, the counter value will be captured in TIMCAPT register.
Value ENUM Name Description
0x0 DIS Disable capture mode for counter
0x1 EN Enable capture mode for counter
RW 0
6:5 CNTRSRC Select event source for counter
Value ENUM Name Description
0x0 CLK Use clock
0x1 CLKBAUD Use baud event
0x2 CLK4BAUD Use 4xBaud event
0x3 CLK4BAUDF Use 4xBaud flushed event
RW 0b00
4 CNTRCLR Clear counter value in TIMCNT to zero when this bit is set to 1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
3 CNTRCTL Enable 16-bit counter when set to 1. The counter will continue from its current value.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
2:1 TIMSRC Select timer tick source for timer
Value ENUM Name Description
0x0 CLK Clock
0x1 CLKBAUD Baud
0x2 CLK4BAUD 4xBaud
0x3 CLK4BAUDF 4xBaud flushed
RW 0b00
0 TIMCTL Enable 16-bit timer. It will generate a timer interrupt after TIMPER timer ticks.
Note that the internal timer value is not readable from the MCE. If this is needed the counter should be used instead of the timer.
Value ENUM Name Description
0x0 DIS Will disable timer and clear internal timer value
0x1 EN Will enable timer
RW 0

TOP:LRFDMDM:TIMINC

Address Offset 0x0000 01E8
Physical Address 0x4008 21E8 Instance 0x4008 21E8
Description Modem Counter Increment Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Programmable counter increment. For each counter event: TIMCNT + 1).
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:TIMPER

Address Offset 0x0000 01EC
Physical Address 0x4008 21EC Instance 0x4008 21EC
Description Modem Timer/Counter Period Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Configurable 16 bit period that can be used for either the timer or the counter.
In timer context, when timer value reach the timer period (i.e. it expires) a TIMER_IRQ event will occur,
and the timer will restart from zero (until the timer is manually disabled).
In counter context, a COUNTER_IRQ event will occur when the counter is equal to or higher than the period value.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:TIMCNT

Address Offset 0x0000 01F0
Physical Address 0x4008 21F0 Instance 0x4008 21F0
Description Modem Counter Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL 16 bit counter value that can be read by the MCE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:TIMCAPT

Address Offset 0x0000 01F4
Physical Address 0x4008 21F4 Instance 0x4008 21F4
Description Modem Counter Capture Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Captured value of counter
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:TIMEBASE

Address Offset 0x0000 01F8
Physical Address 0x4008 21F8 Instance 0x4008 21F8
Description Modem Timebase Control Register
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 FLUSH Starts a flushing process
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDMDM:COUNT1IN

Address Offset 0x0000 01FC
Physical Address 0x4008 21FC Instance 0x4008 21FC
Description Local Count Ones Input Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Input data, which we shall find the number of 1's in
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:COUNT1RES

Address Offset 0x0000 0200
Physical Address 0x4008 2200 Instance 0x4008 2200
Description Local Count Ones Result Register
Type RO
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:0 VAL Number of 1's in the COUNT1IN register
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RO 0b0 0000

TOP:LRFDMDM:BRMACC1

Address Offset 0x0000 0208
Physical Address 0x4008 2208 Instance 0x4008 2208
Description Local Branch Metric Accelerator Module Register 1
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 METRIC01 Metric to 01 (-1 +1) symbol. Immediately calculated when BRMACC0 register is written.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00
7:0 METRIC00 Metric to 00 (-1 -1) symbol. Immediately calculated when BRMACC0 register is written.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDMDM:BRMACC2

Address Offset 0x0000 020C
Physical Address 0x4008 220C Instance 0x4008 220C
Description Local Branch Metric Accelerator Module Register 2
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 METRIC11 Metric to 11 (+1 +1) symbol. Immediately calculated when BRMACC0 register is written.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00
7:0 METRIC10 Metric to 10 (+1 -1) symbol. Immediately calculated when BRMACC0 register is written.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDMDM:MCETRCCTRL

Address Offset 0x0000 0210
Physical Address 0x4008 2210 Instance 0x4008 2210
Description MCE Tracer Send Trigger Register
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 SEND Sends a command to the tracer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDMDM:MCETRCSTAT

Address Offset 0x0000 0214
Physical Address 0x4008 2214 Instance 0x4008 2214
Description MCE Tracer Status Register
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 BUSY Checks if the tracer is busy
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDMDM:MCETRCCMD

Address Offset 0x0000 0218
Physical Address 0x4008 2218 Instance 0x4008 2218
Description MCE Tracer Command Register
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:8 PARCNT Number of parameters
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
7:0 PKTHDR Packet header
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:MCETRCPAR0

Address Offset 0x0000 021C
Physical Address 0x4008 221C Instance 0x4008 221C
Description MCE Tracer Command Parameter Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:MCETRCPAR1

Address Offset 0x0000 0220
Physical Address 0x4008 2220 Instance 0x4008 2220
Description MCE Tracer Command Parameter Register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDMDM:RDCAPT0

Address Offset 0x0000 0224
Physical Address 0x4008 2224 Instance 0x4008 2224
Description Modem Readback Capture Register 0
Type WO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 CHFI Capture CHFI output samples into FECAPT0 and FECAPT1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 BDE2 Capture BDE2 output samples into FECAPT0 and FECAPT1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 FIDC Capture FIDC output samples into FECAPT0 and FECAPT1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 FRAC Capture FRAC output samples into FECAPT0 and FECAPT1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 MGEX Capture MGE1 and MGE2 output values into FECAPT0 and FECAPT1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 CODC Capture CODC output samples into FECAPT0 and FECAPT1.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDMDM:RDCAPT1

Address Offset 0x0000 0228
Physical Address 0x4008 2228 Instance 0x4008 2228
Description Modem Readback Capture Register 1
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 C1BEX2 Capture C1BE B correlation peak x[n-1] value into DSCAPT0 RC register.
Capture C1BE B correlation peak value into DSCAPT1 RC register.
Capture C1BE B correlation peak x[n+1] value into DSCAPT2 RC register.
Capture C1BE B qual value into DSCAPT3 RC register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
10 C1BEX1 Capture C1BE A correlation peak x[n-1] value into DSCAPT0 RC register.
Capture C1BE A correlation peak value into DSCAPT1 RC register.
Capture C1BE A correlation peak x[n+1] value into DSCAPT2 RC register.
Capture C1BE A qual value into DSCAPT3 RC register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
9 C1BEX0 Capture C1BE A values into DSCAPT0 RC register
Capture C1BE B values into DSCAPT1 RC register
Capture C1BE C values into DSCAPT2 RC register
Capture C1BE Corr Peak C into DSCAPT3 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
8 SOFD Capture SOFD soft symbol into DSCAPT0 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
7 LQIE Capture LQIE value into DSCAPT0 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
6 STIM Capture STIM Events value into DSCAPT0 RC register bit 50.
Capture STIM Delta value into DSCAPT1 RC register bit 3:0.
Capture STIM Gardner Error(9:8) into DSCAPT1 RC register bit 7:6.
Capture STIM Gardner Error(7:0) into DSCAPT2 RC register.
Capture STIM output sample into DSCAPT3 RC register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 FIFE Capture FIFE sample into DSCAPT0 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 PDIF Capture PDIF sample into DSCAPT0 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
3 CA2P Capture CA2P sample into DSCAPT0 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
2 MAFI Capture MAFI sample into DSCAPT0 RC register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 DSBU Capture DSBU read pointer into DSCAPT0 register
Capture DSBU write pointer into DSCAPT1 register
Capture DSBU average value into DSCAPT2 register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 MLSEBIT Capture MLSE bit into DSCAPT0 register
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDMDM:FECAPT0

Address Offset 0x0000 022C
Physical Address 0x4008 222C Instance 0x4008 222C
Description Frontend capture readback register 0
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 VAL Readback value, I channel
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDMDM:FECAPT1

Address Offset 0x0000 0230
Physical Address 0x4008 2230 Instance 0x4008 2230
Description Frontend capture readback register 1
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12:0 VAL Readback value, Q channel
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1FFF ALLONES All the bits are 1
RW 0b0 0000 0000 0000

TOP:LRFDMDM:DSCAPT0

Address Offset 0x0000 0234
Physical Address 0x4008 2234 Instance 0x4008 2234
Description Decoding stage capture register 0
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Readback channel 0 after writing to RDCAPT1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DSCAPT1

Address Offset 0x0000 0238
Physical Address 0x4008 2238 Instance 0x4008 2238
Description Decoding stage capture register 1
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Readback channel 1 after writing to RDCAPT1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DSCAPT2

Address Offset 0x0000 023C
Physical Address 0x4008 223C Instance 0x4008 223C
Description Decoding stage capture register 2
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Readback channel 2 after writing to RDCAPT1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DSCAPT3

Address Offset 0x0000 0240
Physical Address 0x4008 2240 Instance 0x4008 2240
Description Decoding stage capture register 3
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Readback channel 3 after writing to RDCAPT1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDMDM:DEMSWQU1

Address Offset 0x0000 0244
Physical Address 0x4008 2244 Instance 0x4008 2244
Description Demodulator sync word qualifier register 1
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:2 MAFCCOMPVAL Frequency Offset value computed by SWQU
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00
1 SWSEL Shows which sync word had a peak event and was selected for sync word qualification test.
This is to tell which sync word was detected when radio operates in receive mode with dual sync word search.
Value ENUM Name Description
0x0 A The C1BE emitted a correlator A peak event and SWQU selected sync word A for qualification test (or no SWQU sync word test has been performed yet)
0x1 B The C1BE emitted a correlator B peak event and SWQU selected sync word B for qualification test
RO 0
0 SYNCED Reads as '1' when the sync word specified by DEMSWQU1.SWSEL has passed qualification, otherwise '0'.
Note that the sync word qualification is only performed on MSB portion of the reference vector,
as specified in DEMSWQU0.REFLEN register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDMDM:GPOCTRL0

Address Offset 0x0000 0248
Physical Address 0x4008 2248 Instance 0x4008 2248
Description Control of the MCE GPO signals [0:7]
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 GPO7 Direct control of MCE_GPO(7) :
00 : FW source 7
01: HW source 7
10: HW source 15
11: Reserved
Value ENUM Name Description
0x0 SW7 Output GPOCTRL1.SW
0x1 TOPSM_WAIT Output hardware clk
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
13:12 GPO6 Direct control of MCE_GPO(6) :
00 : FW source 6
01: HW source 6
10: HW source 14
11: Reserved
Value ENUM Name Description
0x0 SW6 Output GPOCTRL1.SW
0x1 TRANSPARENT_OUT The bit is 1
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
11:10 GPO5 Direct control of MCE_GPO(5) :
00 : FW source 5
01: HW source 5
10: HW source 13
11: Reserved
Value ENUM Name Description
0x0 SW5 Output GPOCTRL1.SW
0x1 DEM_OUT_WORD The bit is 1
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
9:8 GPO4 Direct control of MCE_GPO(4) :
00 : FW source 4
01: HW source 4
10: HW source 12
11: Reserved
Value ENUM Name Description
0x0 SW4 Output GPOCTRL1.SW
0x1 CORR_PEAK_C The bit is 1
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
7:6 GPO3 Direct control of MCE_GPO(3) :
00 : FW source 3
01: HW source 3
10: HW source 11
11: Reserved
Value ENUM Name Description
0x0 SW3 Output GPOCTRL1.SW
0x1 CORR_PEAK_B The bit is 1
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
5:4 GPO2 Direct control of MCE_GPO(2) :
00 : FW source 2
01: HW source 2
10: HW source 10
11: Reserved
Value ENUM Name Description
0x0 SW2 Output GPOCTRL1.SW
0x1 CORR_PEAK_A The bit is 1
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
3:2 GPO1 Direct control of MCE_GPO(1) :
00 : FW source 1
01: HW source 1
10: HW source 9
11: Reserved
Value ENUM Name Description
0x0 SW1 Output GPOCTRL1.SW
0x1 HWCLK1 Output Loopback symbol on pin MDMGPO1
0x2 TWO HW source 2
0x3 THREE HW Source 3
RW 0b00
1:0 GPO0 Direct control of MCE_GPO(0) :
00 : FW source 0
01: HW source 0
10: HW source 8
11: Reserved
Value ENUM Name Description
0x0 SW0 Output GPOCTRL1.SW
0x1 HWCLK0 Output hardware clock on pin MDMGPO0
0x2 LOOPBACK HW source 2
0x3 THREE HW Source 3
RW 0b00

TOP:LRFDMDM:GPOCTRL1

Address Offset 0x0000 024C
Physical Address 0x4008 224C Instance 0x4008 224C
Description Software controlled GPO register for GPO pins [7:0]. Drive modem GPO outputs when GPOCTRLX = "00"
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 HWCLKSTRETCH Control strech for hwclk0 and hwclk1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0b00
13:11 HWCLKMUX1 Select clock source for hwclk1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0b000
10:8 HWCLKMUX0 Select clock source for hwclk0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0b000
7:0 SW Software controlled GPO
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0x00

TOP:LRFDMDM:RFERSSI

Address Offset 0x0000 0250
Physical Address 0x4008 2250 Instance 0x4008 2250
Description RFE received signal strength indicator
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Current RSSI estimate
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDMDM:RFEMAXRSSI

Address Offset 0x0000 0254
Physical Address 0x4008 2254 Instance 0x4008 2254
Description RFE received signal strength indicator
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Highest RSSI since start of reception
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDMDM:RFEDBGAIN

Address Offset 0x0000 0258
Physical Address 0x4008 2258 Instance 0x4008 2258
Description RFE front end gain setting
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Current gain setting
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDMDM:SYNC0

Address Offset 0x0000 025C
Physical Address 0x4008 225C Instance 0x4008 225C
Description Modem Sync Word Register 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWA15C0 Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as most signicant bits of sync word A.
The sync word is expected to be transmitted/received in LSB to MSB order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:SYNC1

Address Offset 0x0000 0260
Physical Address 0x4008 2260 Instance 0x4008 2260
Description Modem Sync Word Register 1
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWA31C16 Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as most significant bits of sync word A.
The sync word is expected to be transmitted/received in LSB to MSB order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:SYNC2

Address Offset 0x0000 0264
Physical Address 0x4008 2264 Instance 0x4008 2264
Description Modem Sync Word Register 2
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWB15C0 Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as most significant bits of sync word B.
The sync word is expected to be transmitted/received in LSB to MSB order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDMDM:SYNC3

Address Offset 0x0000 0268
Physical Address 0x4008 2268 Instance 0x4008 2268
Description Modem Sync Word Register 3
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWB31C16 Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as most significant bits of sync word B.
The sync word is expected to be transmitted/received in LSB to MSB order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000


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