LRFDPBE

Instance: LRFDPBE
Component: LRFDPBE
Base address: 0x40081000


TOP:LRFDPBE Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

ENABLE

RW

32

0x0000 0000

0x0000 0000

0x4008 1000

FWSRC

RW

32

0x0000 0000

0x0000 0004

0x4008 1004

INIT

WO

32

0x0000 0000

0x0000 0008

0x4008 1008

STROBES0

WO

32

0x0000 0000

0x0000 000C

0x4008 100C

IRQ

WO

32

0x0000 0000

0x0000 0010

0x4008 1010

EVT0

RO

32

0x0000 0000

0x0000 0014

0x4008 1014

EVT1

RO

32

0x0000 0000

0x0000 0018

0x4008 1018

EVTMSK0

RW

32

0x0000 0000

0x0000 001C

0x4008 101C

EVTMSK1

RW

32

0x0000 0000

0x0000 0020

0x4008 1020

EVTCLR0

WO

32

0x0000 0000

0x0000 0024

0x4008 1024

EVTCLR1

WO

32

0x0000 0000

0x0000 0028

0x4008 1028

PDREQ

RW

32

0x0000 0000

0x0000 002C

0x4008 102C

API

RW

32

0x0000 0000

0x0000 0030

0x4008 1030

MCEDATOUT0

RW

32

0x0000 0000

0x0000 0034

0x4008 1034

MCEDATIN0

RO

32

0x0000 0000

0x0000 0038

0x4008 1038

MCECMDOUT

RW

32

0x0000 0000

0x0000 003C

0x4008 103C

MCECMDIN

RO

32

0x0000 0000

0x0000 0040

0x4008 1040

MDMAPI

RW

32

0x0000 0000

0x0000 0044

0x4008 1044

MDMMSGBOX

RO

32

0x0000 0000

0x0000 0048

0x4008 1048

FREQ

RO

32

0x0000 0000

0x0000 004C

0x4008 104C

MDMLQI

RO

32

0x0000 0000

0x0000 0050

0x4008 1050

RFEDATOUT0

RW

32

0x0000 0000

0x0000 0054

0x4008 1054

RFEDATIN0

RO

32

0x0000 0000

0x0000 0058

0x4008 1058

RFECMDOUT

RW

32

0x0000 0000

0x0000 005C

0x4008 105C

RFECMDIN

RO

32

0x0000 0000

0x0000 0060

0x4008 1060

RFEAPI

RW

32

0x0000 0000

0x0000 0064

0x4008 1064

RFECMDPAR0

RW

32

0x0000 0000

0x0000 0068

0x4008 1068

RFECMDPAR1

RW

32

0x0000 0000

0x0000 006C

0x4008 106C

RFEMSGBOX

RO

32

0x0000 0000

0x0000 0070

0x4008 1070

RFERSSI

RO

32

0x0000 0000

0x0000 0074

0x4008 1074

RFERSSIMAX

RO

32

0x0000 0000

0x0000 0078

0x4008 1078

RFERFGAIN

RO

32

0x0000 0000

0x0000 007C

0x4008 107C

MDMSYNCAL

RW

32

0x0000 0000

0x0000 0080

0x4008 1080

MDMSYNCAH

RW

32

0x0000 0000

0x0000 0084

0x4008 1084

MDMSYNCBL

RW

32

0x0000 0000

0x0000 0088

0x4008 1088

MDMSYNCBH

RW

32

0x0000 0000

0x0000 008C

0x4008 108C

MDMCMDPAR0

RW

32

0x0000 0000

0x0000 0090

0x4008 1090

MDMCMDPAR1

RW

32

0x0000 0000

0x0000 0094

0x4008 1094

MDMCMDPAR2

RW

32

0x0000 0000

0x0000 0098

0x4008 1098

POLY0L

RW

32

0x0000 0000

0x0000 00A0

0x4008 10A0

POLY0H

RW

32

0x0000 0000

0x0000 00A4

0x4008 10A4

POLY1L

RW

32

0x0000 0000

0x0000 00A8

0x4008 10A8

POLY1H

RW

32

0x0000 0000

0x0000 00AC

0x4008 10AC

PHACFG

RW

32

0x0000 0000

0x0000 00B0

0x4008 10B0

FCFG0

RW

32

0x0000 0021

0x0000 00B4

0x4008 10B4

FCFG1

RW

32

0x0000 0000

0x0000 00B8

0x4008 10B8

FCFG2

RW

32

0x0000 0000

0x0000 00BC

0x4008 10BC

FCFG3

RW

32

0x0000 0000

0x0000 00C0

0x4008 10C0

FCFG4

RW

32

0x0000 0000

0x0000 00C4

0x4008 10C4

FCFG5

RW

32

0x0000 0000

0x0000 00C8

0x4008 10C8

RXFWBTHRS

RW

32

0x0000 0000

0x0000 00CC

0x4008 10CC

RXFRBTHRS

RW

32

0x0000 0000

0x0000 00D0

0x4008 10D0

TXFWBTHRS

RW

32

0x0000 0000

0x0000 00D4

0x4008 10D4

TXFRBTHRS

RW

32

0x0000 0000

0x0000 00D8

0x4008 10D8

TIMCTL

RW

32

0x0000 0000

0x0000 00DC

0x4008 10DC

TIMPRE

RW

32

0x0000 0000

0x0000 00E0

0x4008 10E0

TIMPER0

RW

32

0x0000 0000

0x0000 00E4

0x4008 10E4

TIMPER1

RW

32

0x0000 0000

0x0000 00E8

0x4008 10E8

TIMCAPT0

RO

32

0x0000 0000

0x0000 00EC

0x4008 10EC

TIMCAPT1

RO

32

0x0000 0000

0x0000 00F0

0x4008 10F0

TRCCTL

WO

32

0x0000 0000

0x0000 0100

0x4008 1100

TRCSTAT

RO

32

0x0000 0000

0x0000 0104

0x4008 1104

TRCCMD

RW

32

0x0000 0000

0x0000 0108

0x4008 1108

TRCPAR0

RW

32

0x0000 0000

0x0000 010C

0x4008 110C

TRCPAR1

RW

32

0x0000 0000

0x0000 0110

0x4008 1110

GPOCTRL

RW

32

0x0000 0000

0x0000 0114

0x4008 1114

MDMFWR

RW

32

0x0000 0000

0x0000 0118

0x4008 1118

MDMFRD

RO

32

0x0000 0000

0x0000 011C

0x4008 111C

MDMFWRCTL

RW

32

0x0000 0000

0x0000 0120

0x4008 1120

MDMFRDCTL

RW

32

0x0000 0000

0x0000 0124

0x4008 1124

MDMFCFG

RW

32

0x0000 0000

0x0000 0128

0x4008 1128

MDMFSTA

RO

32

0x0000 0000

0x0000 012C

0x4008 112C

PHASTA

RO

32

0x0000 0000

0x0000 0134

0x4008 1134

LFSR0L

RW

32

0x0000 FFFF

0x0000 0138

0x4008 1138

LFSR0H

RW

32

0x0000 FFFF

0x0000 013C

0x4008 113C

LFSR0BRL

RW

32

0x0000 FFFF

0x0000 0140

0x4008 1140

LFSR0BRH

RW

32

0x0000 FFFF

0x0000 0144

0x4008 1144

LFSR1L

RW

32

0x0000 FFFF

0x0000 0148

0x4008 1148

LFSR1H

RW

32

0x0000 FFFF

0x0000 014C

0x4008 114C

LFSR1BRL

RW

32

0x0000 FFFF

0x0000 0150

0x4008 1150

LFSR1BRH

RW

32

0x0000 FFFF

0x0000 0154

0x4008 1154

LFSR0INL

WO

32

0x0000 0000

0x0000 0158

0x4008 1158

LFSR0N

RW

32

0x0000 0000

0x0000 015C

0x4008 115C

LFSR0INM

WO

32

0x0000 0000

0x0000 0160

0x4008 1160

PHAOUT0

RW

32

0x0000 0000

0x0000 0164

0x4008 1164

LFSR1INL

WO

32

0x0000 0000

0x0000 0168

0x4008 1168

LFSR1N

RW

32

0x0000 0000

0x0000 016C

0x4008 116C

LFSR1INM

WO

32

0x0000 0000

0x0000 0170

0x4008 1170

PHAOUT0BR

RO

32

0x0000 0000

0x0000 0174

0x4008 1174

SYSTIM0L

RO

32

0x0000 0000

0x0000 0180

0x4008 1180

SYSTIM0H

RO

32

0x0000 0000

0x0000 0184

0x4008 1184

SYSTIM1L

RO

32

0x0000 0000

0x0000 0188

0x4008 1188

SYSTIM1H

RO

32

0x0000 0000

0x0000 018C

0x4008 118C

SYSTIM2L

RO

32

0x0000 0000

0x0000 0190

0x4008 1190

SYSTIM2H

RO

32

0x0000 0000

0x0000 0194

0x4008 1194

GPI

RO

32

0x0000 0000

0x0000 0198

0x4008 1198

FCMD

WO

32

0x0000 0000

0x0000 01A0

0x4008 11A0

FSTAT

RO

32

0x0000 0000

0x0000 01A4

0x4008 11A4

RXFWP

RW

32

0x0000 0000

0x0000 01A8

0x4008 11A8

RXFRP

RW

32

0x0000 0000

0x0000 01AC

0x4008 11AC

RXFSWP

RW

32

0x0000 0000

0x0000 01B0

0x4008 11B0

RXFSRP

RW

32

0x0000 0000

0x0000 01B4

0x4008 11B4

TXFWP

RW

32

0x0000 0000

0x0000 01B8

0x4008 11B8

TXFRP

RW

32

0x0000 0000

0x0000 01BC

0x4008 11BC

TXFSWP

RW

32

0x0000 0000

0x0000 01C0

0x4008 11C0

TXFSRP

RW

32

0x0000 0000

0x0000 01C4

0x4008 11C4

RXFWRITABLE

RO

32

0x0000 0000

0x0000 01C8

0x4008 11C8

RXFREADABLE

RO

32

0x0000 0000

0x0000 01CC

0x4008 11CC

TXFWRITABLE

RO

32

0x0000 0000

0x0000 01D0

0x4008 11D0

TXFREADABLE

RO

32

0x0000 0000

0x0000 01D4

0x4008 11D4

RXFBRD

RO

32

0x0000 0000

0x0000 01D8

0x4008 11D8

RXFBWR

WO

32

0x0000 0000

0x0000 01DC

0x4008 11DC

TXFBRD

RO

32

0x0000 0000

0x0000 01E0

0x4008 11E0

TXFBWR

WO

32

0x0000 0000

0x0000 01E4

0x4008 11E4

RXFHRD

RO

32

0x0000 0000

0x0000 01E8

0x4008 11E8

RXFHWR

WO

32

0x0000 0000

0x0000 01EC

0x4008 11EC

TXFHRD

RO

32

0x0000 0000

0x0000 01F0

0x4008 11F0

TXFHWR

WO

32

0x0000 0000

0x0000 01F4

0x4008 11F4

TOP:LRFDPBE Register Descriptions

TOP:LRFDPBE:ENABLE

Address Offset 0x0000 0000
Physical Address 0x4008 1000 Instance 0x4008 1000
Description Packet Building Engine Enable Register.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 MDMF Modem fifo, OR'ed with equivalent siganl in modem
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 LOCTIM Enables the Local timer
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 TOPSM Enables the TOPsm (PBE)
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDPBE:FWSRC

Address Offset 0x0000 0004
Physical Address 0x4008 1004 Instance 0x4008 1004
Description PBE program source select register
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 DATARAM Selects which RAM will be used for data storage
Value ENUM Name Description
0x0 PBERAM Use PBERAM for data
0x1 S2RRAM Use S2RRAM for data
RW 0
1 FWRAM Select which RAM we run FW from
Value ENUM Name Description
0x0 PBERAM Run code from PBERAM
0x1 S2RRAM Run code from S2RRAM
RW 0
0 BANK Sets the MSB of the address to the memory holding the program.
Value ENUM Name Description
0x0 ZERO Run code from bank 0
0x1 ONE Run code from bank 1
RW 0

TOP:LRFDPBE:INIT

Address Offset 0x0000 0008
Physical Address 0x4008 1008 Instance 0x4008 1008
Description Packet Building Engine Initialization Register
Type WO
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4 RFE Do an INIT of the TOPSM in RFE, OR'ed with equivalent signal in RFE
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 RESET The bit is 1
WO 0
3 MDM Do an INIT of the TOPSM in MDM, OR'ed with equivalent signal in MDM
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 RESET The bit is 1
WO 0
2 MDMF Modem FIFO, OR'ed with equivalent signal in MDM
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 RESET The bit is 1
WO 0
1 LOCTIM Synch reset Local timer
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 RESET The bit is 1
WO 0
0 TOPSM Synch reset TOPsm (PBE)
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 RESET The bit is 1
WO 0

TOP:LRFDPBE:STROBES0

Address Offset 0x0000 000C
Physical Address 0x4008 100C Instance 0x4008 100C
Description Packet Building Engine (PBE) Strobe Register 0
Type WO
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6 TIMCAPT1 PBE timer 1 capture strobe
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
5 TIMCAPT0 PBE timer 0 capture strobe
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
4 S2RTRIG Arm/Trigger the S2R module
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 ARM The bit is 1
WO 0
3 DMATRIG FW triggered DMA transfer
Value ENUM Name Description
0x0 NO_EFFECT The bit is 0
0x1 ARM The bit is 1
WO 0
2 SYSTCAPT2 Systimer capture 2 strobe 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
1 SYSTCAPT1 Systimer capture1 strobe 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0
0 SYSTCAPT0 Systimer capture 0 strobe 0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDPBE:IRQ

Address Offset 0x0000 0010
Physical Address 0x4008 1010 Instance 0x4008 1010
Description Packet Building Engine (PBE) interrupt generation register
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 SOFT15 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
14 SOFT14 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
13 SOFT13 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
12 SOFT12 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
11 SOFT11 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
10 SOFT10 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
9 SOFT9 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
8 SOFT8 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
7 SOFT7 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
6 SOFT6 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
5 SOFT5 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
4 SOFT4 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
3 SOFT3 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
2 SOFT2 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
1 SOFT1 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0
0 SOFT0 Software defined interrupt
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
WO 0

TOP:LRFDPBE:EVT0

Address Offset 0x0000 0014
Physical Address 0x4008 1014 Instance 0x4008 1014
Description PBE Event Flag Register 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 MDMFAEMPTY Modem fifo is emptied below the empty threshold
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
14 S2RSTOP S2R has written to the STOP_ADDRESS location
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
13 FIFOERR Error event from fifo
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
12 MDMFAFULL Modem fifo is filled above the threshold
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
11 SYSTCMP2 Systimer compare event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
10 SYSTCMP1 Systimer compare event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
9 SYSTCMP0 Systimer compare event
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
8 MDMMSGBOX New command status from MCE received in MDMMSGBOX register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 RFEMSGBOX New command status from RFE received in RFEMSGBOX register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 RFEDAT New data from RFE received in RFEDATIN0 register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 RFECMD New command from RFE received in RFECMDIN register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 MDMDAT New data from MCE received in MCEDATIN0 register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 MDMCMD New command from MCE received in MCECMDIN register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 TIMER1 Counter value reached in local timer.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 TIMER0 Timer period expired in local timer.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 PBEAPI New command from CPE has been written in API register.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDPBE:EVT1

Address Offset 0x0000 0018
Physical Address 0x4008 1018 Instance 0x4008 1018
Description PBE Event Flag Register 1
Type RO
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 TXRDBTHR The TX FIFO contains TXFRBTHRS or more readable bytes.
Value ENUM Name Description
0x0 BELOW The TX FIFO contains less than the threshold TXFRBTHRS readable bytes.
0x1 MET The TX FIFO contains TXFRBTHRS or more readable bytes.
RO 0
11 TXWRBTHR The TX FIFO contains TXFWBTHRS or more writable bytes.
Value ENUM Name Description
0x0 BELOW The TX FIFO contains less than the threshold TXFWBTHRS writable bytes.
0x1 MET The TX FIFO contains TXFWBTHRS or more writable bytes.
RO 0
10 RXRDBTHR The RX FIFO contains RXFRBTHRS or more readable bytes.
Value ENUM Name Description
0x0 BELOW The TX FIFO contains less than the threshold TXFRBTHRS readable bytes.
0x1 MET The TX FIFO contains TXFRBTHRS or more readable bytes.
RO 0
9 RXWRBTHR The RX FIFO contains RXFWBTHRS or more writable bytes.
Value ENUM Name Description
0x0 BELOW The RX FIFO contains less than the threshold RXFWBTHRS writable bytes.
0x1 MET The RX FIFO contains RXFWBTHRS or more writable bytes.
RO 0
8 MDMPROG Programmable event from modem
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
7 PBEGPI7 External input event line GPI7 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 PBEGPI6 External input event line GPI6 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 PBEGPI5 External input event line GPI5 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 PBEGPI4 External input event line GPI4 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 PBEGPI3 External input event line GPI3 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 PBEGPI2 External input event line GPI2 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 PBEGPI1 External input event line GPI1 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 PBEGPI0 External input event line GPI0 from IOC.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDPBE:EVTMSK0

Address Offset 0x0000 001C
Physical Address 0x4008 101C Instance 0x4008 101C
Description PBE Event Mask Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 MDMFAEMPTY Enable mask for event EVT0.MDMFAEMPTY
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
14 S2RSTOP Enable mask for event EVT0.S2RSTOP
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
13 FIFOERR Enable mask for event EVT0.FIFOERR
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
12 MDMFAFULL Enable mask for event EVT0.MDMFAFULL
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
11 SYSTCMP2 Enable mask for event EVT0.SYSTCMP2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
10 SYSTCMP1 Enable mask for event EVT0.SYSTCMP1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
9 SYSTCMP0 Enable mask for event EVT0.SYSTCMP0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
8 MDMMSGBOX Enable mask for event EVT0.MDMMSGBOX
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 RFEMSGBOX Enable mask for event EVT0.RFEMSGBOX
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 RFEDAT Enable mask for event EVT0.RFEDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 RFECMD Enable mask for event EVT0.RFECMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 MDMDAT Enable mask for event EVT0.MDMDAT
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 MDMCMD Enable mask for event EVT0.MDMCMD
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 TIMER1 Enable mask for event EVT0.TIMER1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 TIMER0 Enable mask for event EVT0.TIMER0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 PBEAPI Enable mask for event EVT0.PBEAPI
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDPBE:EVTMSK1

Address Offset 0x0000 0020
Physical Address 0x4008 1020 Instance 0x4008 1020
Description PBE Event Mask Register 1
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 TXRDBTHR Enable mask for event EVT0.TXRDBTHR
Value ENUM Name Description
0x0 DIS The TX FIFO contains less than the threshold TXFRBTHRS readable bytes.
0x1 EN The TX FIFO contains TXFRBTHRS or more readable bytes.
RW 0
11 TXWRBTHR Enable mask for event EVT0.TXWRBTHR
Value ENUM Name Description
0x0 DIS The TX FIFO contains less than the threshold TXFWBTHRS writable bytes.
0x1 EN The TX FIFO contains TXFWBTHRS or more writable bytes.
RW 0
10 RXRDBTHR Enable mask for event EVT0.RXRDBTHR
Value ENUM Name Description
0x0 DIS The TX FIFO contains less than the threshold TXFWBTHRS writable bytes.
0x1 EN The TX FIFO contains TXFWBTHRS or more writable bytes.
RW 0
9 RXWRBTHR Enable mask for event EVT0.RXWRBTHR
Value ENUM Name Description
0x0 DIS The TX FIFO contains less than the threshold TXFWBTHRS writable bytes.
0x1 EN The TX FIFO contains TXFWBTHRS or more writable bytes.
RW 0
8 MDMPROG Enable mask for event EVT0.MDMPROG
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
7 PBEGPI7 Enable mask for event EVT0.PBEGPI7
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
6 PBEGPI6 Enable mask for event EVT0.PBEGPI6
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
5 PBEGPI5 Enable mask for event EVT0.PBEGPI5
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
4 PBEGPI4 Enable mask for event EVT0.PBEGPI4
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
3 PBEGPI3 Enable mask for event EVT0.PBEGPI3
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
2 PBEGPI2 Enable mask for event EVT0.PBEGPI2
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
1 PBEGPI1 Enable mask for event EVT0.PBEGPI1
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0
0 PBEGPI0 Enable mask for event EVT0.PBEGPI0
Value ENUM Name Description
0x0 DIS The bit is 0
0x1 EN The bit is 1
RW 0

TOP:LRFDPBE:EVTCLR0

Address Offset 0x0000 0024
Physical Address 0x4008 1024 Instance 0x4008 1024
Description PBE Event Clear Register 0
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 MDMFAEMPTY Clear event EVT0.MDMFAEMPTY
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
14 S2RSTOP Clear event EVT0.S2RSTOP
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
13 FIFOERR Clear event EVT0.FIFOERR
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
12 MDMFAFULL Clear event EVT0.MDMFAFULL
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
11 SYSTCMP2 Clear event EVT0.SYSTCMP2
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
10 SYSTCMP1 Clear event EVT0.SYSTCMP1
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
9 SYSTCMP0 Clear event EVT0.SYSTCMP0
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
8 MDMMSGBOX Clear event EVT0.MDMMSGBOX
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
7 RFEMSGBOX Clear event EVT0.RFEMSGBOX
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
6 RFEDAT Clear event EVT0.RFEDAT
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
5 RFECMD Clear event EVT0.RFECMD
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
4 MDMDAT Clear event EVT0.MDMDAT
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
3 MDMCMD Clear event EVT0.MDMCMD
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
2 TIMER1 Clear event EVT0.TIMER1
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
1 TIMER0 Clear event EVT0.TIMER0
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
0 PBEAPI Clear event EVT0.PBEAPI
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0

TOP:LRFDPBE:EVTCLR1

Address Offset 0x0000 0028
Physical Address 0x4008 1028 Instance 0x4008 1028
Description PBE Event Clear Register 1
Type WO
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 TXRDBTHR Clear event EVT0.TXRDBTHR
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
11 TXWRBTHR Clear event EVT0.TXWRBTHR
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
10 RXRDBTHR Clear event EVT0.RXRDBTHR
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
9 RXWRBTHR Clear event EVT0.RXWRBTHR
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
8 MDMPROG Clear event EVT0.MDMPROG
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
7 PBEGPI7 Clear event EVT0.PBEGPI7
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
6 PBEGPI6 Clear event EVT0.PBEGPI6
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
5 PBEGPI5 Clear event EVT0.PBEGPI5
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
4 PBEGPI4 Clear event EVT0.PBEGPI4
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
3 PBEGPI3 Clear event EVT0.PBEGPI3
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
2 PBEGPI2 Clear event EVT0.PBEGPI2
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
1 PBEGPI1 Clear event EVT0.PBEGPI1
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0
0 PBEGPI0 Clear event EVT0.PBEGPI0
Value ENUM Name Description
0x0 RETAIN The bit is 0
0x1 CLEAR The bit is 1
WO 0

TOP:LRFDPBE:PDREQ

Address Offset 0x0000 002C
Physical Address 0x4008 102C Instance 0x4008 102C
Description Packet Building Engine Power-down Register
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 TOPSMPDREQ Requests power down for TOPsm core. If the TOPsm has an ongoing memory access, the hardware will safely gate the clock after the transaction has completed.
Value ENUM Name Description
0x0 OFF The bit is 0
0x1 ON The bit is 1
RW 0

TOP:LRFDPBE:API

Address Offset 0x0000 0030
Physical Address 0x4008 1030 Instance 0x4008 1030
Description PBE API Command Register
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:0 PBECMD PBE Command
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000

TOP:LRFDPBE:MCEDATOUT0

Address Offset 0x0000 0034
Physical Address 0x4008 1034 Instance 0x4008 1034
Description PBE-to-MCE Send Data Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data to send to the MCE. Writing to this register will trigger an event in the MCE, and the data value written here will be readable in LRFDMDM:PBEDATIN0 register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MCEDATIN0

Address Offset 0x0000 0038
Physical Address 0x4008 1038 Instance 0x4008 1038
Description MCE-to-PBE Receive Data Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data received from MCE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:MCECMDOUT

Address Offset 0x0000 003C
Physical Address 0x4008 103C Instance 0x4008 103C
Description PBE-to-MCE Send Command Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command to send to the MCE. Writing to this register will trigger an event in the MCE, and the command value written here will be readable in LRFDMDM:PBECMDIN register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDPBE:MCECMDIN

Address Offset 0x0000 0040
Physical Address 0x4008 1040 Instance 0x4008 1040
Description MCE-to-PBE Receive Command Register
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command received from MCE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDPBE:MDMAPI

Address Offset 0x0000 0044
Physical Address 0x4008 1044 Instance 0x4008 1044
Description Modem API Command Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 PROTOCOLID Protocol ID
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
3:0 MDMCMD Modem command
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDPBE:MDMMSGBOX

Address Offset 0x0000 0048
Physical Address 0x4008 1048 Instance 0x4008 1048
Description Modem Command Status Register
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VALUE Diverse status, error, report bits from MCE. Controlled by software.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:FREQ

Address Offset 0x0000 004C
Physical Address 0x4008 104C Instance 0x4008 104C
Description Modem Frequency Offset
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 OFFSET Frequency Offset from MCE. Controlled by software.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:MDMLQI

Address Offset 0x0000 0050
Physical Address 0x4008 1050 Instance 0x4008 1050
Description Modem Link Quality Indicator estimate
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL LQI status from MCE. Controlled by software.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:RFEDATOUT0

Address Offset 0x0000 0054
Physical Address 0x4008 1054 Instance 0x4008 1054
Description PBE-to-RFE Send Data Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data to send to the RFE. Writing to this register will trigger an event in the RFE, and the data value written here will be readable in LRFDRFE:PBEDATIN0 register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:RFEDATIN0

Address Offset 0x0000 0058
Physical Address 0x4008 1058 Instance 0x4008 1058
Description RFE-to-PBE Receive Data Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Data received from RFE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:RFECMDOUT

Address Offset 0x0000 005C
Physical Address 0x4008 105C Instance 0x4008 105C
Description PBE-to-RFE Send Command Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command to send to the RFE. Writing to this register will trigger an event in the RFE, and the command value written here will be readable in LRFDRFE:PBECMDIN register.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDPBE:RFECMDIN

Address Offset 0x0000 0060
Physical Address 0x4008 1060 Instance 0x4008 1060
Description RFE-to-PBE Receive Command Register
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Command received from RFE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RO 0x0

TOP:LRFDPBE:RFEAPI

Address Offset 0x0000 0064
Physical Address 0x4008 1064 Instance 0x4008 1064
Description RFE API Command Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 PROTOCOLID Protocol ID
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0
3:0 RFECMD RFE Command
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDPBE:RFECMDPAR0

Address Offset 0x0000 0068
Physical Address 0x4008 1068 Instance 0x4008 1068
Description RFE Command Parameter 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:RFECMDPAR1

Address Offset 0x0000 006C
Physical Address 0x4008 106C Instance 0x4008 106C
Description RFE Command Parameter 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:RFEMSGBOX

Address Offset 0x0000 0070
Physical Address 0x4008 1070 Instance 0x4008 1070
Description RFE Command Status and Message Box Register
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Diverse status, error, report bits from RFE
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:RFERSSI

Address Offset 0x0000 0074
Physical Address 0x4008 1074 Instance 0x4008 1074
Description RFERSSI Value Register
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Current RSSI value (signed). If this register reads as -128 (0x80) it means that the value is not yet valid.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:RFERSSIMAX

Address Offset 0x0000 0078
Physical Address 0x4008 1078 Instance 0x4008 1078
Description RSSI Maximum Value Register
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Maximum RSSI value since start of measurements cycle. If this field reads as -128 (0x80) it means that the value is not yet valid.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:RFERFGAIN

Address Offset 0x0000 007C
Physical Address 0x4008 107C Instance 0x4008 107C
Description RF front-end gain value
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DBGAIN Current RF front-end gain, in dB
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:MDMSYNCAL

Address Offset 0x0000 0080
Physical Address 0x4008 1080 Instance 0x4008 1080
Description Modem Sync Word Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWALSB Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as most signicant bits of sync word A. The sync word is expected to be transmitted/received in lsb to msb order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMSYNCAH

Address Offset 0x0000 0084
Physical Address 0x4008 1084 Instance 0x4008 1084
Description Modem Sync Word Register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWAMSB Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as most significant bits of sync word A. The sync word is expected to be transmitted/received in lsb to msb order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMSYNCBL

Address Offset 0x0000 0088
Physical Address 0x4008 1088 Instance 0x4008 1088
Description Modem Sync Word Register 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWBLSB Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as most significant bits of sync word B. The sync word is expected to be transmitted/received in lsb to msb order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMSYNCBH

Address Offset 0x0000 008C
Physical Address 0x4008 108C Instance 0x4008 108C
Description Modem Sync Word Register 3
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SWBMSB Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as most significant bits of sync word B. The sync word is expected to be transmitted/received in lsb to msb order.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMCMDPAR0

Address Offset 0x0000 0090
Physical Address 0x4008 1090 Instance 0x4008 1090
Description Modem API Command Parameter 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0. Software defined function.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMCMDPAR1

Address Offset 0x0000 0094
Physical Address 0x4008 1094 Instance 0x4008 1094
Description Modem API Command Parameter 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1. Software defined function.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMCMDPAR2

Address Offset 0x0000 0098
Physical Address 0x4008 1098 Instance 0x4008 1098
Description Modem API Command Parameter 2
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 2. Software defined function.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:POLY0L

Address Offset 0x0000 00A0
Physical Address 0x4008 10A0 Instance 0x4008 10A0
Description LFSR 0 Polynomial Definition
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB LFSR 0 polynomial taps, lower half
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:POLY0H

Address Offset 0x0000 00A4
Physical Address 0x4008 10A4 Instance 0x4008 10A4
Description LFSR 0 Polynomial Definition
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB LFSR 0 polynomial taps, upper half
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:POLY1L

Address Offset 0x0000 00A8
Physical Address 0x4008 10A8 Instance 0x4008 10A8
Description LFSR 1 Polynomial Definition
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB LFSR 1 polynomial taps, low part
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:POLY1H

Address Offset 0x0000 00AC
Physical Address 0x4008 10AC Instance 0x4008 10AC
Description LFSR 1 Polynomial Definition
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB LFSR 1 polynomial taps, high part
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:PHACFG

Address Offset 0x0000 00B0
Physical Address 0x4008 10B0 Instance 0x4008 10B0
Description Packet Handler Accelerator Config Register
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:1 MODE1 Dual LFSR operating mode
Value ENUM Name Description
0x0 INDEP LFSR0 and LFSR1 are operated independently
0x1 CASC LFSR0 whitener is followed by LFSR1 CRC
0x2 PARAL LFSR0 and LFSR1 are operated in parallel
RW 0b00
0 MODE0 LFSR 0 operating mode
Value ENUM Name Description
0x0 CRC LFSR 0 is in CRC mode
0x1 WHITE LFSR 0 is in whitening mode
RW 0

TOP:LRFDPBE:FCFG0

Address Offset 0x0000 00B4
Physical Address 0x4008 10B4 Instance 0x4008 10B4
Description FIFO configuration register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 TXIRQMET Select source for pbe_irq(17)
Value ENUM Name Description
0x0 TXWRBTHR The TX FIFO contains TXFWBTHRS or more writable bytes.
0x1 TXRDBTHR The TX FIFO contains TXFRBTHRS or more readable bytes.
RW 0
6 RXIRQMET Select source for pbe_irq(16)
Value ENUM Name Description
0x0 RXRDBTHR The RX FIFO contains RXFRBTHRS or more readable bytes.
0x1 RXWRBTHR The RX FIFO contains RXFWBTHRS or more writable bytes.
RW 0
5 TXACOM Automatic FIFO commit configuration
Value ENUM Name Description
0x0 DIS commit TXFIFO only on command 0x95
0x1 EN Always set TXSWP := TXWP
RW 1
4 TXADEAL Automatic deallocation setting
Value ENUM Name Description
0x0 DIS Deallocate TXFIFO only on command 0x92
0x1 EN Always set TXFSRP := TXFRP.
RW 0
3:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
1 RXACOM Automatic FIFO commit configuration
Value ENUM Name Description
0x0 DIS commit rxfifo only on command 0x85
0x1 EN Always set RXFSWP := RXFWP
RW 0
0 RXADEAL Automatic deallocation setting
Value ENUM Name Description
0x0 DIS Deallocate RXFIFO only on command 0x82
0x1 EN Always set RXFSRP := RXFRP.
RW 1

TOP:LRFDPBE:FCFG1

Address Offset 0x0000 00B8
Physical Address 0x4008 10B8 Instance 0x4008 10B8
Description FIFO configuration register
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8:0 TXSTRT FIFO start address, offset from start of BUFRAM. Address is 32-bit word address (not byte address)
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x1FF ONES All bits are 1s
RW 0b0 0000 0000

TOP:LRFDPBE:FCFG2

Address Offset 0x0000 00BC
Physical Address 0x4008 10BC Instance 0x4008 10BC
Description FIFO configuration register
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 TXHSIZE Select transfer size to calculate DMA_SREQ_TRIGGER MD(more data) and FREE, for both RX FIFO and TX FIFO.
Value ENUM Name Description
0x0 BYTE MCU receives IRQ when the TX FIFO contains less amount of data than the configured threshold.
0x1 HALFW MCU receives IRQ when the TX FIFO contains less amount of data than the configured threshold.
0x2 WORD MCU receives IRQ when the TX FIFO contains more or equal amount of data than the configured threshold.
RW 0b000
7:0 TXSIZE TXFIFO size in number of 32-bit words
Value ENUM Name Description
0x0 ZEROS All bits are zero
0xFF ONES All bits are 1s
RW 0x00

TOP:LRFDPBE:FCFG3

Address Offset 0x0000 00C0
Physical Address 0x4008 10C0 Instance 0x4008 10C0
Description FIFO configuration register
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8:0 RXSTRT FIFO start address, offset from start of BUFRAM. Address is 32-bit word adress (not byte address)
Value ENUM Name Description
0x0 ZEROS All bits are zero
0x1FF ONES All bits are 1s
RW 0b0 0000 0000

TOP:LRFDPBE:FCFG4

Address Offset 0x0000 00C4
Physical Address 0x4008 10C4 Instance 0x4008 10C4
Description FIFO configuration register
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 RXHSIZE Select transfer size to calculate DMA_SREQ_TRIGGER MD(more data) and FREE, for both RX FIFO and TX FIFO.
Value ENUM Name Description
0x0 BYTE MCU receives IRQ when the TX FIFO contains less amount of data than the configured threshold.
0x1 HALFW MCU receives IRQ when the TX FIFO contains less amount of data than the configured threshold.
0x2 WORD MCU receives IRQ when the TX FIFO contains more or equal amount of data than the configured threshold.
RW 0b000
7:0 RXSIZE RXFIFO size in number of 32-bit words
Value ENUM Name Description
0x0 ZEROS commit rxfifo only on command 0x85
0xFF ONES Always set RXFSWP := RXFWP
RW 0x00

TOP:LRFDPBE:FCFG5

Address Offset 0x0000 00C8
Physical Address 0x4008 10C8 Instance 0x4008 10C8
Description Configures DMA trigger from radio FIFOs
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8:6 DMASREQ DMA trigger select. Triggers DMA when selected trigger occurs. Note that it is a mix of pulse type and level type triggers
Value ENUM Name Description
0x0 NONE No triggers generated
0x1 RXFIFOMD The RX FIFO contains FCFG4_RXHSIZE or more readable bytes.
0x2 RXFIFOFREE The RX FIFO contains FCFG4_RXHSIZE or more writable bytes.
0x3 TXFIFOMD The TX FIFO contains FCFG2_TXHSIZE or more readable bytes.
0x4 TXFIFOFREE The TX FIFO contains FCFG2_TXHSIZE or more writable bytes.
RW 0b000
5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
4:0 DMAREQ DMA trigger select. Triggers DMA when selected trigger occurs. Note that it is a mix of pulse type and level type triggers
Value ENUM Name Description
0x0 NONE No triggers generated
0x1 RXRDBTHR_MET The RX FIFO contains RXFRBTHRS or more readable bytes.
0x2 RXWRBTHR_MET The RX FIFO contains RXFWBTHRS or more writable bytes.
0x3 RXFIFO_RESET RXFIFO is reset
0x4 RXFIFO_DEALLOC RXFIFO is deallocated
0x5 RXFIFO_RETRY RXFIFO is retried
0x6 RXFIFO_DISCARD RXFIFO is discarded
0x7 RXFIFO_COMMIT RXFIFO is committed
0x9 TXRDBTHR_MET The TX FIFO contains TXFRBTHRS or more readable bytes.
0xA TXWRBTHR_MET The TX FIFO contains TXFWBTHRS or more writable bytes.
0xB TXFIFO_RESET TXFIFO is reset
0xC TXFIFO_DEALLOC TXFIFO is deallocated
0xD TXFIFO_RETRY TXFIFO is retried
0xE TXFIFO_DISCARD TXFIFO is discarded
0xF TXFIFO_COMMIT TXFIFO is committed
RW 0b0 0000

TOP:LRFDPBE:RXFWBTHRS

Address Offset 0x0000 00CC
Physical Address 0x4008 10CC Instance 0x4008 10CC
Description Threshold value for the RX FIFO writable bytes
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:RXFRBTHRS

Address Offset 0x0000 00D0
Physical Address 0x4008 10D0 Instance 0x4008 10D0
Description Threshold value for the RX FIFO readable bytes
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TXFWBTHRS

Address Offset 0x0000 00D4
Physical Address 0x4008 10D4 Instance 0x4008 10D4
Description Threshold value for the TX FIFO writable bytes
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TXFRBTHRS

Address Offset 0x0000 00D8
Physical Address 0x4008 10D8 Instance 0x4008 10D8
Description Threshold value for the TX FIFO readable bytes
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TIMCTL

Address Offset 0x0000 00DC
Physical Address 0x4008 10DC Instance 0x4008 10DC
Description PBE Timer Control Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:11 CPTSRC1 Selects bit number from event bus to use for a counter capture. Event number in range 0 to 31
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
10 ENCPT1 Enable timer capture on event. Upon a capture event, the timer value will be captured in TIMCAPT register. The timer value can always be captured using the STROBES0.TIMCAPT1
Value ENUM Name Description
0x0 OFF Disable capture mode for counter
0x1 ON Enable capture mode for counter
RW 0
9 SRC1 Select timer tick source for timer
Value ENUM Name Description
0x0 CLK Use clock
0x1 PRE1 Use magnitude estimator 0 data enable
RW 0
8 EN1 Enable 16-bit timer1. It will generate a timer interrupt after TIMPER1 timer ticks.
Value ENUM Name Description
0x0 OFF Will disable timer and clear internal timer value
0x1 ON Will enable timer
RW 0
7:3 CPTSRC0 Selects bit number from event bus to use for a counter capture. Event number in range 0 to 31
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x1F ALLONES All the bits are 1
RW 0b0 0000
2 ENCPT0 Enable timer capture on event. Upon a capture event, the timer value will be captured in TIMCAPT register. The timer value can always be captured using the STROBES0.TIMCAPT0
Value ENUM Name Description
0x0 OFF Disable capture mode for counter
0x1 ON Enable capture mode for counter
RW 0
1 SRC0 Select timer tick source for timer
Value ENUM Name Description
0x0 CLK Use clock
0x1 PRE0 Use magnitude estimator 0 data enable
RW 0
0 EN0 Enable 16-bit timer0. It will generate a timer interrupt after TIMPER0 timer ticks. Note that the internal timer value is not readable from the PBE.
Value ENUM Name Description
0x0 OFF Will disable timer and clear internal timer value
0x1 ON Will enable timer
RW 0

TOP:LRFDPBE:TIMPRE

Address Offset 0x0000 00E0
Physical Address 0x4008 10E0 Instance 0x4008 10E0
Description Prescaler setting for timer 0 and timer 1
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:8 PRE1 Prescaler setting for timer 1, timer speed will be reduced to clk/(PRE1+1)
Value ENUM Name Description
0x0 NO_DIV No prescaling
0x3F DIV64 DIV64 mode
RW 0b00 0000
7:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
5:0 PRE0 Prescaler setting for timer 0, timer speed will be reduced to clk/(PRE0+1)
Value ENUM Name Description
0x0 NO_DIV No prescaling
0x3F DIV64 DIV64 mode
RW 0b00 0000

TOP:LRFDPBE:TIMPER0

Address Offset 0x0000 00E4
Physical Address 0x4008 10E4 Instance 0x4008 10E4
Description PBE Timer0 Period Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Configurable 16 bit period that can be used for either the timer or the counter. In timer context, when timer value reach the timer period (i.e. it expires) a TIMER_IRQ event will occur, and the timer will restart from zero (until the timer is manually disabled). In counter context, a COUNTER_IRQ event will occur when the counter is equal to or higher than the period value.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:TIMPER1

Address Offset 0x0000 00E8
Physical Address 0x4008 10E8 Instance 0x4008 10E8
Description PBE Timer1 Period Configuration
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Configurable 16 bit period that can be used for either the timer or the counter. In timer context, when timer value reach the timer period (i.e. it expires) a TIMER_IRQ event will occur, and the timer will restart from zero (until the timer is manually disabled). In counter context, a COUNTER_IRQ event will occur when the counter is equal to or higher than the period value.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:TIMCAPT0

Address Offset 0x0000 00EC
Physical Address 0x4008 10EC Instance 0x4008 10EC
Description PBE Timer0 Capture Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Captured value of counter
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:TIMCAPT1

Address Offset 0x0000 00F0
Physical Address 0x4008 10F0 Instance 0x4008 10F0
Description PBE Timer1 Capture Value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALUE Captured value of counter
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:TRCCTL

Address Offset 0x0000 0100
Physical Address 0x4008 1100 Instance 0x4008 1100
Description PBE Tracer Send Trigger Register
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 SEND Sends a command to the tracer
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0

TOP:LRFDPBE:TRCSTAT

Address Offset 0x0000 0104
Physical Address 0x4008 1104 Instance 0x4008 1104
Description PBE Tracer Status Register
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 BUSY Checks if the tracer is busy
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDPBE:TRCCMD

Address Offset 0x0000 0108
Physical Address 0x4008 1108 Instance 0x4008 1108
Description PBE Tracer Commmand Register
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:8 PARCNT Number of parameters
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
RW 0b00
7:0 PKTHDR Packet header
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDPBE:TRCPAR0

Address Offset 0x0000 010C
Physical Address 0x4008 110C Instance 0x4008 110C
Description PBE Tracer Command Parameter Register 0
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:TRCPAR1

Address Offset 0x0000 0110
Physical Address 0x4008 1110 Instance 0x4008 1110
Description PBE Tracer Command Parameter Register 1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Parameter 1
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:GPOCTRL

Address Offset 0x0000 0114
Physical Address 0x4008 1114 Instance 0x4008 1114
Description PBE Direct GPO control register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 GPO7 Control GPO7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
6 GPO6 Control GPO6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
5 GPO5 Control GPO5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
4 GPO4 Control GPO4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
3 GPO3 Control GPO3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
2 GPO2 Control GPO2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
1 GPO1 Control GPO1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0
0 GPO0 Control GPO0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RW 0

TOP:LRFDPBE:MDMFWR

Address Offset 0x0000 0118
Physical Address 0x4008 1118 Instance 0x4008 1118
Description Modem FIFO Write Register
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 PAYLOADIN FIFO write port. The actual port size is configurable in LRFDMDM:FIFOWRCTRL.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:MDMFRD

Address Offset 0x0000 011C
Physical Address 0x4008 111C Instance 0x4008 111C
Description Modem FIFO Read Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 PAYLOADOUT FIFO read port. The actual port size is configurable in LRFDMDM:FIFORDCTRL.
A new value is read by writing LRFDMDM:FIFOWR.PAYLOADIN.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:MDMFWRCTL

Address Offset 0x0000 0120
Physical Address 0x4008 1120 Instance 0x4008 1120
Description Modem FIFO Write Configuration
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 WORDSZWR Actual bits in every word write access
Value ENUM Name Description
0x0 BITS1 1 bit
0x1 BITS2 2 bits
0x2 BITS3 3 bits
0x3 BITS4 4 bits
0x4 BITS5 5 bits
0x5 BITS6 6 bits
0x6 BITS7 7 bits
0x7 BITS8 8 bits
0x8 BITS9 9 bits
0x9 BITS10 10 bits
0xA BITS11 11 bits
0xB BITS12 12 bits
0xC BITS13 13 bits
0xD BITS14 14 bits
0xE BITS15 15 bits
0xF BITS16 16 bits
RW 0x0

TOP:LRFDPBE:MDMFRDCTL

Address Offset 0x0000 0124
Physical Address 0x4008 1124 Instance 0x4008 1124
Description Modem FIFO Read Configuration
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 WORDSZRD Actual bits in every word read access
Value ENUM Name Description
0x0 BITS1 1 bit
0x1 BITS2 2 bits
0x2 BITS3 3 bits
0x3 BITS4 4 bits
0x4 BITS5 5 bits
0x5 BITS6 6 bits
0x6 BITS7 7 bits
0x7 BITS8 8 bits
0x8 BITS9 9 bits
0x9 BITS10 10 bits
0xA BITS11 11 bits
0xB BITS12 12 bits
0xC BITS13 13 bits
0xD BITS14 14 bits
0xE BITS15 15 bits
0xF BITS16 16 bits
RW 0x0

TOP:LRFDPBE:MDMFCFG

Address Offset 0x0000 0128
Physical Address 0x4008 1128 Instance 0x4008 1128
Description Modem FIFO Configuration for watermark thresholds
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 AFULLTHR Almost full threshold value in bits. This threshold affects the LRFDMDM:FIFOSTA.ALMOSTFULL and LRFDMDM:FIFOSTA.TXREADY status bits. The FIFO can hold up to 64 bits.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00
7:0 AEMPTYTHR Almost empty threshold in bits. This threshold affects the LRFDMDM:FIFOSTA.ALMOSTEMPTY and LRFDMDM:FIFOSTA.RXVALID status bits. The FIFO can hold up to 64 bits.
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RW 0x00

TOP:LRFDPBE:MDMFSTA

Address Offset 0x0000 012C
Physical Address 0x4008 112C Instance 0x4008 112C
Description Modem FIFO Status Flags
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 OVFL FIFO overflow error. If this flag is asserted the modem FIFO must be re-initialized with LRFDMDM:INIT.TXRXFIFO to clear it. Note that re-initializing will flush the FIFO.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 ALMOSTFULL FIFO is almost full. Asserts when the FIFO fill level is above the almost full threshold.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 ALMOSTEMPTY FIFO is almost empty. Asserts when the FIFO fill level is below the almost empty threshold.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 UNFL FIFO underflow error. If this flag is asserted the modem FIFO must be re-initialized with LRFDMDM:INIT.TXRXFIFO to clear it.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 RXVALID A full data word is valid and can be read in LRFDMDM:FIFORD register read port.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 TXREADY The LRFDMDM:FIFOWR register write port is ready to receive a data word.
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDPBE:PHASTA

Address Offset 0x0000 0134
Physical Address 0x4008 1134 Instance 0x4008 1134
Description Packet Handler Accelerator Status
Type RO
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 BUSY Status busy flags.
Value ENUM Name Description
0x0 IDLE LFSR n sub-engine idle
0x1 BUSY LFSR n sub-engine busy
RO 0b00

TOP:LRFDPBE:LFSR0L

Address Offset 0x0000 0138
Physical Address 0x4008 1138 Instance 0x4008 1138
Description LFSR 0 Current Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB LFSR 0 low part value, bits 15:0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR0H

Address Offset 0x0000 013C
Physical Address 0x4008 113C Instance 0x4008 113C
Description LFSR 0 Current Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB LFSR 0 high part value, bits 31:16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR0BRL

Address Offset 0x0000 0140
Physical Address 0x4008 1140 Instance 0x4008 1140
Description LFSR 0 Current Value, Bit-reversed
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB LFSR 0 value, bit reversed order bits 15:0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR0BRH

Address Offset 0x0000 0144
Physical Address 0x4008 1144 Instance 0x4008 1144
Description LFSR 0 Current Value, Bit-reversed
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB LFSR 0 value, bit reversed order bits 31:16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR1L

Address Offset 0x0000 0148
Physical Address 0x4008 1148 Instance 0x4008 1148
Description LFSR 1 Current Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB LFSR 1 low part value, bits 15:0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR1H

Address Offset 0x0000 014C
Physical Address 0x4008 114C Instance 0x4008 114C
Description LFSR 1 Current Value
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB LFSR 1 high part value, bits 31:16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR1BRL

Address Offset 0x0000 0150
Physical Address 0x4008 1150 Instance 0x4008 1150
Description LFSR 1 Current Value, Bit-reversed
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB LFSR 1 value, bit reversed order bits 15:0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR1BRH

Address Offset 0x0000 0154
Physical Address 0x4008 1154 Instance 0x4008 1154
Description LFSR 1 Current Value, Bit-reversed
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB LFSR 1 value, bit reversed order bits 31:16
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RW 0xFFFF

TOP:LRFDPBE:LFSR0INL

Address Offset 0x0000 0158
Physical Address 0x4008 1158 Instance 0x4008 1158
Description LFSR 0 Input, LSB First. The number of bits actually clocked into the LFSR is determined by LFSR0N
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL LFSR 0 input value LSB first
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
WO 0x0000

TOP:LRFDPBE:LFSR0N

Address Offset 0x0000 015C
Physical Address 0x4008 115C Instance 0x4008 115C
Description Control input size of LSFR 0
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 SIZE Number of bits to clock into LSFR0 upon next write to LFSR0INL or LFSR0INM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDPBE:LFSR0INM

Address Offset 0x0000 0160
Physical Address 0x4008 1160 Instance 0x4008 1160
Description LFSR 0 Input, MSB First. The number of bits actually clocked into the LFSR is determined by LFSR0N
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL LFSR 0 input value MSB first
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0x0000

TOP:LRFDPBE:PHAOUT0

Address Offset 0x0000 0164
Physical Address 0x4008 1164 Instance 0x4008 1164
Description LFSR 0 Output
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Output value of LFSR0
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xDCD7 ALLONES All the bits are 1
RW 0x0000

TOP:LRFDPBE:LFSR1INL

Address Offset 0x0000 0168
Physical Address 0x4008 1168 Instance 0x4008 1168
Description LFSR 1 Input, LSB First. The number of bits actually clocked into the LFSR is determined by LFSR1N
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL LFSR 1 input value LSB first
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3 ALLONES All the bits are 1
WO 0x0000

TOP:LRFDPBE:LFSR1N

Address Offset 0x0000 016C
Physical Address 0x4008 116C Instance 0x4008 116C
Description Controls input size of LFSR 1
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 SIZE Number of bits to clock into LSFR1 upon next write to LFSR1INL or LFSR1INM
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xF ALLONES All the bits are 1
RW 0x0

TOP:LRFDPBE:LFSR1INM

Address Offset 0x0000 0170
Physical Address 0x4008 1170 Instance 0x4008 1170
Description LFSR 1 Input, MSB First. The number of bits actually clocked into the LFSR is determined by LFSR1N
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL LFSR 1 input value MSB first
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
WO 0x0000

TOP:LRFDPBE:PHAOUT0BR

Address Offset 0x0000 0174
Physical Address 0x4008 1174 Instance 0x4008 1174
Description LFSR 0 Output, Bit-reversed
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Output value of LFSR0 in bit reversed order
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:SYSTIM0L

Address Offset 0x0000 0180
Physical Address 0x4008 1180 Instance 0x4008 1180
Description Systimer capture value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB SYSTIM0 capture low part value, bits 15:0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0x0000

TOP:LRFDPBE:SYSTIM0H

Address Offset 0x0000 0184
Physical Address 0x4008 1184 Instance 0x4008 1184
Description Systimer capture value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB SYSTIM0 capture high part value, bits 31:16
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0x0000

TOP:LRFDPBE:SYSTIM1L

Address Offset 0x0000 0188
Physical Address 0x4008 1188 Instance 0x4008 1188
Description Systimer capture value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB SYSTIM1 capture low part value, bits 15:0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0x0000

TOP:LRFDPBE:SYSTIM1H

Address Offset 0x0000 018C
Physical Address 0x4008 118C Instance 0x4008 118C
Description Systimer capture value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB SYSTIM1 capture high part value, bits 31:16
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0x0000

TOP:LRFDPBE:SYSTIM2L

Address Offset 0x0000 0190
Physical Address 0x4008 1190 Instance 0x4008 1190
Description Systimer capture value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALLSB SYSTIM2 capture low part value, bits 15:0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0x0000

TOP:LRFDPBE:SYSTIM2H

Address Offset 0x0000 0194
Physical Address 0x4008 1194 Instance 0x4008 1194
Description Systimer capture value
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VALMSB SYSTIM2 capture high part value, bits 31:16
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0x0000

TOP:LRFDPBE:GPI

Address Offset 0x0000 0198
Physical Address 0x4008 1198 Instance 0x4008 1198
Description PBE Direct GPI Status
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 GPI7 Control GPI7
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
6 GPI6 Control GPI6
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
5 GPI5 Control GPI5
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
4 GPI4 Control GPI4
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
3 GPI3 Control GPI3
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
2 GPI2 Control GPI2
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
1 GPI1 Control GPI1
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0
0 GPI0 Control GPI0
Value ENUM Name Description
0x0 ZERO The bit is 0
0x1 ONE The bit is 1
RO 0

TOP:LRFDPBE:FCMD

Address Offset 0x0000 01A0
Physical Address 0x4008 11A0 Instance 0x4008 11A0
Description The FIFO command register
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA Command either RX or TX FIFO or both. Strobe signals which clear after write.
Value ENUM Name Description
0x1 RXFIFO_RESET Reset (empty) rxfifo. Set RXF* := 0
0x2 RXFIFO_DEALLOC Deallocate rxfifo. This sets RXFSRP := RXFRP.
0x3 TXFIFO_COMMIT Commit txfifo. This sets TXFSWP := TXFWP
0x4 TXFIFO_DISCARD Discard txfifo. This sets TXFWP := TXFSWP
0x5 TXFIFO_RETRY Retry txfifo. This sets TXFRP := TXFSRP
0x6 TXFIFO_DEALLOC Deallocate txfifo. This sets TXFSRP := TXFRP.
0x7 TXFIFO_RESET Reset (empty) txfifo. Set TXF* := 0
0x8 RXFIFO_COMMIT Commit rxfifo. This sets RXFSWP := RXFWP
0x9 RXFIFO_DISCARD Discard rxfifo. This sets RXFWP := RXFSWP
0xA RXFIFO_RETRY Retry rxfifo. This sets RXFRP := RXFSRP
0xB FIFO_RESET Reset (empty) both FIFOs
0xC FIFO_DEALLOC Deallocate both FIFOS
0xD FIFO_RETRY Retry both FIFOs
0xE FIFO_DISCARD Discard both FIFOs
0xF FIFO_COMMIT Commit both FIFOs
WO 0x00

TOP:LRFDPBE:FSTAT

Address Offset 0x0000 01A4
Physical Address 0x4008 11A4 Instance 0x4008 11A4
Description FIFO status register
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 TXUNFL Underflow occurred in the TX FIFO.
Value ENUM Name Description
0x0 FALSE Normal operation ensues
0x1 TRUE Underflow has occurred
RO 0
10 TXOVFL Overflow occurred in the TX FIFO.
Value ENUM Name Description
0x0 FALSE Normal operation ensues
0x1 TRUE Overflow has occurred
RO 0
9 TXEMPTY TXFIFO empty flag
Value ENUM Name Description
0x0 FALSE TXFIFO is not empty
0x1 TRUE TXFIFO is empty
RO 0
8 TXFULL TXFIFO full flag
Value ENUM Name Description
0x0 FALSE TXFIFO is not full
0x1 TRUE TXFIFO is full
RO 0
7:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
3 RXUNFL Underflow occurred in the RX FIFO.
Value ENUM Name Description
0x0 FALSE Normal operation ensues
0x1 TRUE Underflow has occurred
RO 0
2 RXOVFL Overflow occurred in the RX FIFO.
Value ENUM Name Description
0x0 FALSE Normal operation ensues
0x1 TRUE Overflow has occurred
RO 0
1 RXEMPTY RXFIFO empty flag
Value ENUM Name Description
0x0 FALSE RXFIFO is not empty
0x1 TRUE RXFIFO is empty
RO 0
0 RXFULL RXFIFO full flag
Value ENUM Name Description
0x0 FALSE RXFIFO is not full
0x1 TRUE RXFIFO is full
RO 0

TOP:LRFDPBE:RXFWP

Address Offset 0x0000 01A8
Physical Address 0x4008 11A8 Instance 0x4008 11A8
Description

Rxfifo write pointer. This is the offset into rxfifo the next write operation will write to. If RFFCFG.RXFAUTOCOMMIT is set writing this register will also write the same value to RXFSWP
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Write pointer
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:RXFRP

Address Offset 0x0000 01AC
Physical Address 0x4008 11AC Instance 0x4008 11AC
Description Rxfifo read pointer. This is the offset into rxfifo the next read operation will read from. If RFFCFG.RXAUTODEALLOC is set writing this register will also write the same value to RXFSRP
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Read pointer
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:RXFSWP

Address Offset 0x0000 01B0
Physical Address 0x4008 11B0 Instance 0x4008 11B0
Description Rx FIFO start of written package. This is where the write pointer can be reset to if a discard command is issued.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Pointer to start of written package
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:RXFSRP

Address Offset 0x0000 01B4
Physical Address 0x4008 11B4 Instance 0x4008 11B4
Description Rxfifo start of read package. This is the start of the allocated part of the rxfifo.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Pointer to start of read package
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TXFWP

Address Offset 0x0000 01B8
Physical Address 0x4008 11B8 Instance 0x4008 11B8
Description TXFIFO write pointer. This is the offset into TXFIFO the next write operation will write to. If RFFCFG.TXFAUTOCOMMIT is set writing this register will also write the same value to TXFSWP
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Write pointer
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TXFRP

Address Offset 0x0000 01BC
Physical Address 0x4008 11BC Instance 0x4008 11BC
Description TXFIFO read pointer. This is the offset into TXFIFO the next read operation will read from. If RFFCFG.TXAUTODEALLOC is set writing this register will also write the same value to TXFSRP
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Read pointer
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TXFSWP

Address Offset 0x0000 01C0
Physical Address 0x4008 11C0 Instance 0x4008 11C0
Description TXFIFO start of written package. This is where the write pointer can be reset to if a discard command is issued.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Pointer to start of written package
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:TXFSRP

Address Offset 0x0000 01C4
Physical Address 0x4008 11C4 Instance 0x4008 11C4
Description TXFIFO start of read package. This is the start of the allocated part of the TXFIFO
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 PTR Pointer to start of read package
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES_2 All the bits are 1
RW 0b00 0000 0000

TOP:LRFDPBE:RXFWRITABLE

Address Offset 0x0000 01C8
Physical Address 0x4008 11C8 Instance 0x4008 11C8
Description The amount of bytes which are deallocated and not yet written. srp - wp when srp >= wp else fifo_size - wp + srp
Type RO
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES The amount of writable bytes for the RX FIFO may be directly read here
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RO 0b00 0000 0000

TOP:LRFDPBE:RXFREADABLE

Address Offset 0x0000 01CC
Physical Address 0x4008 11CC Instance 0x4008 11CC
Description The amount of bytes which are comitted and not yet read. swp - rp when swp >= rp else fifo_size - rp + swp
Type RO
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES The amount of readable bytes for the RX FIFO may be directly read here
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RO 0b00 0000 0000

TOP:LRFDPBE:TXFWRITABLE

Address Offset 0x0000 01D0
Physical Address 0x4008 11D0 Instance 0x4008 11D0
Description The amount of bytes which are deallocated and not yet written. srp - wp when srp >= wp else fifo_size - wp + srp
Type RO
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES The amount of writable bytes for the TX FIFO may be directly read here
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RO 0b00 0000 0000

TOP:LRFDPBE:TXFREADABLE

Address Offset 0x0000 01D4
Physical Address 0x4008 11D4 Instance 0x4008 11D4
Description The amount of bytes which are comitted and not yet read. swp - rp when swp >= rp else fifo_size - rp + swp
Type RO
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 BYTES The amount of readable bytes for the TX FIFO may be directly read here
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0x3FF ALLONES All the bits are 1
RO 0b00 0000 0000

TOP:LRFDPBE:RXFBRD

Address Offset 0x0000 01D8
Physical Address 0x4008 11D8 Instance 0x4008 11D8
Description Read 1 byte from the RX FIFO.
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA Data to be read
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:RXFBWR

Address Offset 0x0000 01DC
Physical Address 0x4008 11DC Instance 0x4008 11DC
Description Write 1 byte to the RX FIFO.
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA Data to be written
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
WO 0x00

TOP:LRFDPBE:TXFBRD

Address Offset 0x0000 01E0
Physical Address 0x4008 11E0 Instance 0x4008 11E0
Description Read 1 byte from the TX FIFO.
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA Data to be read
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
RO 0x00

TOP:LRFDPBE:TXFBWR

Address Offset 0x0000 01E4
Physical Address 0x4008 11E4 Instance 0x4008 11E4
Description Write 1 byte to the TX FIFO.
Type WO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA Data to be written
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFF ALLONES All the bits are 1
WO 0x00

TOP:LRFDPBE:RXFHRD

Address Offset 0x0000 01E8
Physical Address 0x4008 11E8 Instance 0x4008 11E8
Description Read 2 bytes from the RX FIFO.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Data to be read
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:RXFHWR

Address Offset 0x0000 01EC
Physical Address 0x4008 11EC Instance 0x4008 11EC
Description Write 2 bytes to the RX FIFO.
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Data to be written
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
WO 0x0000

TOP:LRFDPBE:TXFHRD

Address Offset 0x0000 01F0
Physical Address 0x4008 11F0 Instance 0x4008 11F0
Description Read 2 bytes from the TX FIFO.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Data to be read
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
RO 0x0000

TOP:LRFDPBE:TXFHWR

Address Offset 0x0000 01F4
Physical Address 0x4008 11F4 Instance 0x4008 11F4
Description Write 2 bytes to the TX FIFO.
Type WO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Data to be written
Value ENUM Name Description
0x0 ALLZEROS All the bits are 0
0xFFFF ALLONES All the bits are 1
WO 0x0000


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