Instance: EVTSVT
Component: EVTSVT
Base address: 0x40025000
This is top module of SVT Event Fabric
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x3045 1010 |
0x0000 0000 |
0x4002 5000 |
|
RO |
32 |
0x0218 2D31 |
0x0000 0004 |
0x4002 5004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0064 |
0x4002 5064 |
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
0x4002 5400 |
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
0x4002 5404 |
|
RW |
32 |
0x0000 0000 |
0x0000 0408 |
0x4002 5408 |
|
RW |
32 |
0x0000 0000 |
0x0000 040C |
0x4002 540C |
|
RW |
32 |
0x0000 0000 |
0x0000 0410 |
0x4002 5410 |
|
RW |
32 |
0x0000 0000 |
0x0000 0414 |
0x4002 5414 |
|
RO |
32 |
0x0000 0009 |
0x0000 0418 |
0x4002 5418 |
|
RO |
32 |
0x0000 000C |
0x0000 041C |
0x4002 541C |
|
RO |
32 |
0x0000 000D |
0x0000 0420 |
0x4002 5420 |
|
RO |
32 |
0x0000 0014 |
0x0000 0424 |
0x4002 5424 |
|
RO |
32 |
0x0000 0016 |
0x0000 0428 |
0x4002 5428 |
|
RO |
32 |
0x0000 000F |
0x0000 042C |
0x4002 542C |
|
RO |
32 |
0x0000 0017 |
0x0000 0430 |
0x4002 5430 |
|
RO |
32 |
0x0000 0018 |
0x0000 0434 |
0x4002 5434 |
|
RO |
32 |
0x0000 0012 |
0x0000 0438 |
0x4002 5438 |
|
RO |
32 |
0x0000 0013 |
0x0000 043C |
0x4002 543C |
|
RO |
32 |
0x0000 0010 |
0x0000 0440 |
0x4002 5440 |
|
RW |
32 |
0x0000 0000 |
0x0000 0444 |
0x4002 5444 |
|
RO |
32 |
0x0000 0031 |
0x0000 0448 |
0x4002 5448 |
|
RO |
32 |
0x0000 0037 |
0x0000 044C |
0x4002 544C |
|
RO |
32 |
0x0000 0004 |
0x0000 0450 |
0x4002 5450 |
|
RW |
32 |
0x0000 0000 |
0x0000 0454 |
0x4002 5454 |
|
RO |
32 |
0x0000 002A |
0x0000 0458 |
0x4002 5458 |
|
RO |
32 |
0x0000 002B |
0x0000 045C |
0x4002 545C |
|
RO |
32 |
0x0000 002C |
0x0000 0460 |
0x4002 5460 |
|
RW |
32 |
0x0000 0000 |
0x0000 0464 |
0x4002 5464 |
|
RW |
32 |
0x0000 0000 |
0x0000 0468 |
0x4002 5468 |
|
RW |
32 |
0x0000 0000 |
0x0000 046C |
0x4002 546C |
|
RW |
32 |
0x0000 0000 |
0x0000 0470 |
0x4002 5470 |
|
RW |
32 |
0x0000 0000 |
0x0000 0474 |
0x4002 5474 |
|
RW |
32 |
0x0000 0000 |
0x0000 0478 |
0x4002 5478 |
|
RW |
32 |
0x0000 0000 |
0x0000 047C |
0x4002 547C |
|
RW |
32 |
0x0000 0000 |
0x0000 0480 |
0x4002 5480 |
|
RW |
32 |
0x0000 0000 |
0x0000 0484 |
0x4002 5484 |
|
RW |
32 |
0x0000 0000 |
0x0000 0488 |
0x4002 5488 |
|
RW |
32 |
0x0000 0000 |
0x0000 048C |
0x4002 548C |
|
RW |
32 |
0x0000 0000 |
0x0000 0490 |
0x4002 5490 |
|
RW |
32 |
0x0000 0000 |
0x0000 0494 |
0x4002 5494 |
|
RW |
32 |
0x0000 0000 |
0x0000 0498 |
0x4002 5498 |
|
RW |
32 |
0x0000 0000 |
0x0000 049C |
0x4002 549C |
|
RW |
32 |
0x0000 0000 |
0x0000 04A0 |
0x4002 54A0 |
|
RW |
32 |
0x0000 0000 |
0x0000 04A4 |
0x4002 54A4 |
|
RW |
32 |
0x0000 0000 |
0x0000 04A8 |
0x4002 54A8 |
|
RO |
32 |
0x0000 001D |
0x0000 04AC |
0x4002 54AC |
|
RO |
32 |
0x0000 001E |
0x0000 04B0 |
0x4002 54B0 |
|
RO |
32 |
0x0000 001F |
0x0000 04B4 |
0x4002 54B4 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C00 |
0x4002 5C00 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C04 |
0x4002 5C04 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C08 |
0x4002 5C08 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C0C |
0x4002 5C0C |
|
RW |
32 |
0x0000 0000 |
0x0000 0C10 |
0x4002 5C10 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C14 |
0x4002 5C14 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C18 |
0x4002 5C18 |
|
RW |
32 |
0x0000 0000 |
0x0000 0C1C |
0x4002 5C1C |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4002 5000 | Instance | 0x4002 5000 |
Description | Description This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0x3045 | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x1 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP (0-15). | RO | 0x1 | ||
3:0 | MINREV | Minor revision of IP (0-15). | RO | 0x0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4002 5004 | Instance | 0x4002 5004 |
Description | Extended Description This register provides configuration details of the IP to software drivers and end users. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:22 | IDMA | Number of DMA input channels | RO | 0b00 0000 1000 | ||
21:17 | NDMA | Number of DMA output channels | RO | 0b0 1100 | ||
16 | PD | Power Domain. 0 : SVT 1 : ULL |
RO | 0 | ||
15:8 | NSUB | Number of Subscribers | RO | 0x2D | ||
7:0 | NPUB | Number of Publishers | RO | 0x31 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4002 5064 | Instance | 0x4002 5064 |
Description | Digital test bus control This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||||||||
1:0 | SEL | Digital test bus selection mux control. Non-zero select values output a 16 bit selected group of signals per value.
|
RW | 0b00 |
Address Offset | 0x0000 0400 | ||
Physical Address | 0x4002 5400 | Instance | 0x4002 5400 |
Description | Output Selection for CPU NMI Exception | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0404 | ||
Physical Address | 0x4002 5404 | Instance | 0x4002 5404 |
Description | Output Selection for CPU Interrupt CPUIRQ0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0408 | ||
Physical Address | 0x4002 5408 | Instance | 0x4002 5408 |
Description | Output Selection for CPU Interrupt CPUIRQ1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 040C | ||
Physical Address | 0x4002 540C | Instance | 0x4002 540C |
Description | Output Selection for CPU Interrupt CPUIRQ2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0410 | ||
Physical Address | 0x4002 5410 | Instance | 0x4002 5410 |
Description | Output Selection for CPU Interrupt CPUIRQ3 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0414 | ||
Physical Address | 0x4002 5414 | Instance | 0x4002 5414 |
Description | Output Selection for CPU Interrupt CPUIRQ4 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0418 | ||
Physical Address | 0x4002 5418 | Instance | 0x4002 5418 |
Description | Output Selection for CPU Interrupt CPUIRQ5 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b00 1001 |
Address Offset | 0x0000 041C | ||
Physical Address | 0x4002 541C | Instance | 0x4002 541C |
Description | Output Selection for CPU Interrupt CPUIRQ6 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b00 1100 |
Address Offset | 0x0000 0420 | ||
Physical Address | 0x4002 5420 | Instance | 0x4002 5420 |
Description | Output Selection for CPU Interrupt CPUIRQ7 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b00 1101 |
Address Offset | 0x0000 0424 | ||
Physical Address | 0x4002 5424 | Instance | 0x4002 5424 |
Description | Output Selection for CPU Interrupt CPUIRQ8 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 0100 |
Address Offset | 0x0000 0428 | ||
Physical Address | 0x4002 5428 | Instance | 0x4002 5428 |
Description | Output Selection for CPU Interrupt CPUIRQ9 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 0110 |
Address Offset | 0x0000 042C | ||
Physical Address | 0x4002 542C | Instance | 0x4002 542C |
Description | Output Selection for CPU Interrupt CPUIRQ10 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b00 1111 |
Address Offset | 0x0000 0430 | ||
Physical Address | 0x4002 5430 | Instance | 0x4002 5430 |
Description | Output Selection for CPU Interrupt CPUIRQ11 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 0111 |
Address Offset | 0x0000 0434 | ||
Physical Address | 0x4002 5434 | Instance | 0x4002 5434 |
Description | Output Selection for CPU Interrupt CPUIRQ12 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 1000 |
Address Offset | 0x0000 0438 | ||
Physical Address | 0x4002 5438 | Instance | 0x4002 5438 |
Description | Output Selection for CPU Interrupt CPUIRQ13 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 0010 |
Address Offset | 0x0000 043C | ||
Physical Address | 0x4002 543C | Instance | 0x4002 543C |
Description | Output Selection for CPU Interrupt CPUIRQ14 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 0011 |
Address Offset | 0x0000 0440 | ||
Physical Address | 0x4002 5440 | Instance | 0x4002 5440 |
Description | Output Selection for CPU Interrupt CPUIRQ15 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 0000 |
Address Offset | 0x0000 0444 | ||
Physical Address | 0x4002 5444 | Instance | 0x4002 5444 |
Description | Output Selection for CPU Interrupt CPUIRQ16 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0448 | ||
Physical Address | 0x4002 5448 | Instance | 0x4002 5448 |
Description | Output Selection for CPU Interrupt CPUIRQ17 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b11 0001 |
Address Offset | 0x0000 044C | ||
Physical Address | 0x4002 544C | Instance | 0x4002 544C |
Description | Output Selection for CPU Interrupt CPUIRQ18 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b11 0111 |
Address Offset | 0x0000 0450 | ||
Physical Address | 0x4002 5450 | Instance | 0x4002 5450 |
Description | Output Selection for SYSTIMC0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b00 0100 |
Address Offset | 0x0000 0454 | ||
Physical Address | 0x4002 5454 | Instance | 0x4002 5454 |
Description | Output Selection for SYSTIMC1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0458 | ||
Physical Address | 0x4002 5458 | Instance | 0x4002 5458 |
Description | Output Selection for SYSTIMC2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b10 1010 |
Address Offset | 0x0000 045C | ||
Physical Address | 0x4002 545C | Instance | 0x4002 545C |
Description | Output Selection for SYSTIMC3 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b10 1011 |
Address Offset | 0x0000 0460 | ||
Physical Address | 0x4002 5460 | Instance | 0x4002 5460 |
Description | Output Selection for SYSTIMC4 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b10 1100 |
Address Offset | 0x0000 0464 | ||
Physical Address | 0x4002 5464 | Instance | 0x4002 5464 |
Description | Output Selection for ADCTRG | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0468 | ||
Physical Address | 0x4002 5468 | Instance | 0x4002 5468 |
Description | Output Selection for LGPTSYNC | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 046C | ||
Physical Address | 0x4002 546C | Instance | 0x4002 546C |
Description | Output Selection for LGPT0IN0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0470 | ||
Physical Address | 0x4002 5470 | Instance | 0x4002 5470 |
Description | Output Selection for LGPT0IN1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0474 | ||
Physical Address | 0x4002 5474 | Instance | 0x4002 5474 |
Description | Output Selection for LGPT0IN2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0478 | ||
Physical Address | 0x4002 5478 | Instance | 0x4002 5478 |
Description | Output Selection for LGPT0TEN | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 047C | ||
Physical Address | 0x4002 547C | Instance | 0x4002 547C |
Description | Output Selection for LGPT1IN0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0480 | ||
Physical Address | 0x4002 5480 | Instance | 0x4002 5480 |
Description | Output Selection for LGPT1IN1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0484 | ||
Physical Address | 0x4002 5484 | Instance | 0x4002 5484 |
Description | Output Selection for LGPT1IN2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0488 | ||
Physical Address | 0x4002 5488 | Instance | 0x4002 5488 |
Description | Output Selection for LGPT1TEN | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 048C | ||
Physical Address | 0x4002 548C | Instance | 0x4002 548C |
Description | Output Selection for LGPT2IN0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0490 | ||
Physical Address | 0x4002 5490 | Instance | 0x4002 5490 |
Description | Output Selection for LGPT2IN1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0494 | ||
Physical Address | 0x4002 5494 | Instance | 0x4002 5494 |
Description | Output Selection for LGPT2IN2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0498 | ||
Physical Address | 0x4002 5498 | Instance | 0x4002 5498 |
Description | Output Selection for LGPT2TEN | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 049C | ||
Physical Address | 0x4002 549C | Instance | 0x4002 549C |
Description | Output Selection for LGPT3IN0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 04A0 | ||
Physical Address | 0x4002 54A0 | Instance | 0x4002 54A0 |
Description | Output Selection for LGPT3IN1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 04A4 | ||
Physical Address | 0x4002 54A4 | Instance | 0x4002 54A4 |
Description | Output Selection for LGPT3IN2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 04A8 | ||
Physical Address | 0x4002 54A8 | Instance | 0x4002 54A8 |
Description | Output Selection for LGPT3TEN | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 04AC | ||
Physical Address | 0x4002 54AC | Instance | 0x4002 54AC |
Description | Output Selection for LRFDIN0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 1101 |
Address Offset | 0x0000 04B0 | ||
Physical Address | 0x4002 54B0 | Instance | 0x4002 54B0 |
Description | Output Selection for LRFDIN1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 1110 |
Address Offset | 0x0000 04B4 | ||
Physical Address | 0x4002 54B4 | Instance | 0x4002 54B4 |
Description | Output Selection for LRFDIN2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||
5:0 | PUBID | Read only selection value
|
RO | 0b01 1111 |
Address Offset | 0x0000 0C00 | ||
Physical Address | 0x4002 5C00 | Instance | 0x4002 5C00 |
Description | Output Selection for DMA CH0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
28:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | IPID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b000 |
Address Offset | 0x0000 0C04 | ||
Physical Address | 0x4002 5C04 | Instance | 0x4002 5C04 |
Description | Output Selection for DMA CH1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
28:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | IPID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b000 |
Address Offset | 0x0000 0C08 | ||
Physical Address | 0x4002 5C08 | Instance | 0x4002 5C08 |
Description | Output Selection for DMA CH2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
28:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | IPID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b000 |
Address Offset | 0x0000 0C0C | ||
Physical Address | 0x4002 5C0C | Instance | 0x4002 5C0C |
Description | Output Selection for DMA CH3 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
28:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | IPID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b000 |
Address Offset | 0x0000 0C10 | ||
Physical Address | 0x4002 5C10 | Instance | 0x4002 5C10 |
Description | Output Selection for DMA CH4 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
28:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | IPID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b000 |
Address Offset | 0x0000 0C14 | ||
Physical Address | 0x4002 5C14 | Instance | 0x4002 5C14 |
Description | Output Selection for DMA CH5 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
28:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
2:0 | IPID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b000 |
Address Offset | 0x0000 0C18 | ||
Physical Address | 0x4002 5C18 | Instance | 0x4002 5C18 |
Description | Output Selection for DMA CH6 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | EDGDETDIS | Edge detect disable. 0: Enabled. 1: Disabled |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0C1C | ||
Physical Address | 0x4002 5C1C | Instance | 0x4002 5C1C |
Description | Output Selection for DMA CH7 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | EDGDETDIS | Edge detect disable. 0: Enabled. 1: Disabled |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
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