Instance: I2C0
Component: I2C
Base address: 0x40038000
I2C IP module with peripheral and controller capabilities
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4003 8000 |
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4003 8004 |
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4003 8004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4003 8008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4003 800C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4003 8010 |
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4003 8014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4003 8018 |
|
RW |
32 |
0x0000 0000 |
0x0000 0800 |
0x4003 8800 |
|
RO |
32 |
0x0000 0020 |
0x0000 0804 |
0x4003 8804 |
|
WO |
32 |
0x0000 0000 |
0x0000 0804 |
0x4003 8804 |
|
RW |
32 |
0x0000 0000 |
0x0000 0808 |
0x4003 8808 |
|
RW |
32 |
0x0000 0001 |
0x0000 080C |
0x4003 880C |
|
RW |
32 |
0x0000 0000 |
0x0000 0810 |
0x4003 8810 |
|
RO |
32 |
0x0000 0000 |
0x0000 0814 |
0x4003 8814 |
|
RO |
32 |
0x0000 0000 |
0x0000 0818 |
0x4003 8818 |
|
RW |
32 |
0x0000 0000 |
0x0000 081C |
0x4003 881C |
|
RW |
32 |
0x0000 0000 |
0x0000 0820 |
0x4003 8820 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4003 8000 | Instance | 0x4003 8000 |
Description | Target Own Address This register consists of seven address bits that identify this I2C device on the I2C bus. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||
6:0 | OAR | Target own address. This field specifies bits a6 through a0 of the target address. | RW | 0b000 0000 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4003 8004 | Instance | 0x4003 8004 |
Description | Target status This register functions as a status register of the target. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | FBR | First byte received. This bit is only applicable when the TSTA.RREQ bit is set and is automatically cleared when data has been read from the TDR register. Note: This bit is not used for target transmit operations.
|
RO | 0 | |||||||||||
1 | TREQ | This field reflects the transmit request status
|
RO | 0 | |||||||||||
0 | RREQ | This field reflects the receive request status.
|
RO | 0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4003 8004 | Instance | 0x4003 8004 |
Description | Target control This registers functions as a target control register |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DA | This field sets the device active control
|
WO | 0 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4003 8008 | Instance | 0x4003 8008 |
Description | Target data register This register contains the data to be transmitted when in the target transmit state, and the data received when in the target receive state. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | DATA | Data for transfer. This field contains the data for transfer during a target receive or a transmit operation. When written, the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write to the controller for transmit or by an external controller to the target for receive. | RW | 0x00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4003 800C | Instance | 0x4003 800C |
Description | Target interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | STOPIM | Stop condition interrupt mask
|
RW | 0 | |||||||||||
1 | STARTIM | Start condition interrupt mask
|
RW | 0 | |||||||||||
0 | DATAIM | Data interrupt mask
|
RW | 0 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4003 8010 | Instance | 0x4003 8010 |
Description | Target raw interrupt status This register shows the unmasked interrupt status. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | STOPRIS | Stop condition raw interrupt status This bit is cleared by writing a 1 to TICR.STOPIC.
|
RO | 0 | |||||||||||
1 | STARTRIS | Start condition raw interrupt status This bit is cleared by writing a 1 to TICR.STARTIC.
|
RO | 0 | |||||||||||
0 | DATARIS | Data raw interrupt status This bit is cleared by writing a 1 to TICR.DATAIC.
|
RO | 0 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4003 8014 | Instance | 0x4003 8014 |
Description | Target Masked Interrupt Status This register shows which interrupt is active (based on result from TRIS and TIMR registers). |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | STOPMIS | Stop condition masked interrupt status This bit is cleared by writing a 1 to TICR.STOPIC.
|
RO | 0 | |||||||||||
1 | STARTMIS | Start condition masked interrupt status This bit is cleared by writing a 1 to TICR.STARTIC.
|
RO | 0 | |||||||||||
0 | DATAMIS | Start condition masked interrupt status This bit is cleared by writing a 1 to TICR.DATAIC.
|
RO | 0 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4003 8018 | Instance | 0x4003 8018 |
Description | Target Interrupt Clear This register clears the raw interrupt TRIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | STOPIC | Stop condition interrupt clear
|
WO | 0 | |||||||||||
1 | STARTIC | Start condition interrupt clear
|
WO | 0 | |||||||||||
0 | DATAIC | Data interrupt clear
|
WO | 0 |
Address Offset | 0x0000 0800 | ||
Physical Address | 0x4003 8800 | Instance | 0x4003 8800 |
Description | Controller target address This register contains seven address bits of the target to be accessed by the controller (a6-a0), and an CTA.RS bit determining if the next operation is a receive or transmit |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7:1 | SA | Controller target address Defines which target is addressed for the transaction in controller mode |
RW | 0b000 0000 | |||||||||||
0 | RS | Receive or Send This bit-field specifies the next operation with addressed target CTA.SA.
|
RW | 0 |
Address Offset | 0x0000 0804 | ||
Physical Address | 0x4003 8804 | Instance | 0x4003 8804 |
Description | Controller status This register functions as a controller status register |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6 | BUSBSY | Bus busy Note:The bit changes based on the CCTRL.START and CCTRL.STOP conditions.
|
RO | 0 | |||||||||||
5 | IDLE | This field specifies whether I2C is idle or not
|
RO | 1 | |||||||||||
4 | ARBLST | The filed specifies the arbitration status
|
RO | 0 | |||||||||||
3 | DATACKN | This field contains Data acknowledge status
|
RO | 0 | |||||||||||
2 | ADRACKN | This field reflects the address acknowledge status
|
RO | 0 | |||||||||||
1 | ERR | This field reflects the error status
|
RO | 0 | |||||||||||
0 | BUSY | This field reflects the I2C busy status Note: The I2C controller requires four CLKSVT clock cycles to assert the BUSY status after I2C controller operation has been initiated through a write into CCTL register. Hence after programming CCTL register, application is requested to wait for four CLKSVT clock cycles before issuing a controller status inquiry through a read from CSTA register. Any prior inquiry would result in wrong status being reported.
|
RO | 0 |
Address Offset | 0x0000 0804 | ||
Physical Address | 0x4003 8804 | Instance | 0x4003 8804 |
Description | Controller control This register functions as a controller control register |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | ACK | This field is to enable the data acknowledge. Note:This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the target transmitter.
|
WO | 0 | |||||||||||
2 | STOP | This field is to set stop condition . Note: This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition.
|
WO | 0 | |||||||||||
1 | START | This field is to set start or repeated start condition.
|
WO | 0 | |||||||||||
0 | RUN | This field is to set the controller enable.
|
WO | 0 |
Address Offset | 0x0000 0808 | ||
Physical Address | 0x4003 8808 | Instance | 0x4003 8808 |
Description | Controller data This register contains the data to be transmitted when in the controller transmit state and the data received when in the controller receive state. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | DATA | When Read: Last RX Data is returned When Written: Data is transferred during TX transaction |
RW | 0x00 |
Address Offset | 0x0000 080C | ||
Physical Address | 0x4003 880C | Instance | 0x4003 880C |
Description | Controller timer period This register specifies the period of the SCL clock. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7 | TPR_7 | Must be set to 0 to set CTPR.TPR. If set to 1, a write to CTPR.TPR will be ignored. | RW | 0 | ||
6:0 | TPR | SCL clock period This field specifies the period of the SCL clock. SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD, where: SCL_PRD is the SCL line period (I2C clock). TPR is the timer period register value (range of 1 to 127) SCL_LP is the SCL low period (fixed at 6). SCL_HP is the SCL high period (fixed at 4). CLK_PRD is the CLKSVT period in ns. |
RW | 0b000 0001 |
Address Offset | 0x0000 0810 | ||
Physical Address | 0x4003 8810 | Instance | 0x4003 8810 |
Description | Controller interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | IM | Interrupt mask
|
RW | 0 |
Address Offset | 0x0000 0814 | ||
Physical Address | 0x4003 8814 | Instance | 0x4003 8814 |
Description | Controller raw interrupt status This register shows the unmasked interrupt status. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | RIS | Raw interrupt status This bit is cleared by writing 1 to CICR.IC bit.
|
RO | 0 |
Address Offset | 0x0000 0818 | ||
Physical Address | 0x4003 8818 | Instance | 0x4003 8818 |
Description | Controller masked interrupt status This register shows which interrupt is active (based on result from CRIS and CIMR registers). |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | MIS | Masked interrupt status This bit is cleared by writing 1 to CICR.IC bit.
|
RO | 0 |
Address Offset | 0x0000 081C | ||
Physical Address | 0x4003 881C | Instance | 0x4003 881C |
Description | Controller interrupt clear This register clears the raw and masked interrupt. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | IC | Interrupt clear
|
WO | 0 |
Address Offset | 0x0000 0820 | ||
Physical Address | 0x4003 8820 | Instance | 0x4003 8820 |
Description | Controller Configuration This register configures the mode (Controller or Target) and sets the interface for test mode loopback. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | TFE | I2C target function enable
|
RW | 0 | |||||||||||
4 | CFE | I2C controller function enable
|
RW | 0 | |||||||||||
3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
0 | LPBK | I2C loopback
|
RW | 0 |
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