Instance: CKMD
Component: CKMD
Base address: 0x40001000
Clock Controller
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x9B4B 1000 |
0x0000 0000 |
0x4000 1000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4000 1044 |
|
RO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4000 1048 |
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0x4000 104C |
|
WO |
32 |
0x0000 0000 |
0x0000 0050 |
0x4000 1050 |
|
WO |
32 |
0x0000 0000 |
0x0000 0054 |
0x4000 1054 |
|
WO |
32 |
0x0000 0000 |
0x0000 0058 |
0x4000 1058 |
|
WO |
32 |
0x0000 0000 |
0x0000 005C |
0x4000 105C |
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0x4000 1080 |
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x4000 1084 |
|
RW |
32 |
0x0000 0000 |
0x0000 008C |
0x4000 108C |
|
RW |
32 |
0x0000 0000 |
0x0000 0090 |
0x4000 1090 |
|
RW |
32 |
0x0000 2064 |
0x0000 0094 |
0x4000 1094 |
|
RW |
32 |
0x9E84 8014 |
0x0000 0098 |
0x4000 1098 |
|
RW |
32 |
0x0000 0000 |
0x0000 009C |
0x4000 109C |
|
RW |
32 |
0x0000 0000 |
0x0000 00A0 |
0x4000 10A0 |
|
RW |
32 |
0x0040 0000 |
0x0000 00A4 |
0x4000 10A4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00A8 |
0x4000 10A8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00AC |
0x4000 10AC |
|
RW |
32 |
0x0000 0000 |
0x0000 00B0 |
0x4000 10B0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C0 |
0x4000 10C0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C4 |
0x4000 10C4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C8 |
0x4000 10C8 |
|
RO |
32 |
0x0000 0000 |
0x0000 00E0 |
0x4000 10E0 |
|
RO |
32 |
0x0000 0000 |
0x0000 00E4 |
0x4000 10E4 |
|
RO |
32 |
0x0000 0000 |
0x0000 00E8 |
0x4000 10E8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00EC |
0x4000 10EC |
|
RO |
32 |
0x0000 0000 |
0x0000 00F0 |
0x4000 10F0 |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4000 1100 |
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0x4000 1104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4000 1108 |
|
RW |
32 |
0x0000 0000 |
0x0000 0110 |
0x4000 1110 |
|
RW |
32 |
0x006F 94D6 |
0x0000 0114 |
0x4000 1114 |
|
RW |
32 |
0x147F 8000 |
0x0000 0118 |
0x4000 1118 |
|
RW |
32 |
0x5446 4B6D |
0x0000 011C |
0x4000 111C |
|
RW |
32 |
0x1446 4B6D |
0x0000 0120 |
0x4000 1120 |
|
RW |
32 |
0x0034 8882 |
0x0000 0124 |
0x4000 1124 |
|
RW |
32 |
0x260F F0FF |
0x0000 0128 |
0x4000 1128 |
|
RW |
32 |
0x605E 33B3 |
0x0000 012C |
0x4000 112C |
|
RW |
32 |
0x0000 0000 |
0x0000 0200 |
0x4000 1200 |
|
RO |
32 |
0x0000 0006 |
0x0000 0204 |
0x4000 1204 |
|
RO |
32 |
0x0000 0002 |
0x0000 0208 |
0x4000 1208 |
|
RW |
32 |
0x0000 0000 |
0x0000 020C |
0x4000 120C |
|
RW |
32 |
0x0000 0000 |
0x0000 0210 |
0x4000 1210 |
|
RW |
32 |
0x0000 0000 |
0x0000 0214 |
0x4000 1214 |
|
RW |
32 |
0x0000 0000 |
0x0000 0218 |
0x4000 1218 |
|
RW |
32 |
0x0000 0000 |
0x0000 021C |
0x4000 121C |
|
RW |
32 |
0x0000 0000 |
0x0000 0220 |
0x4000 1220 |
|
RW |
32 |
0x0000 0000 |
0x0000 0224 |
0x4000 1224 |
|
RW |
32 |
0x0000 0000 |
0x0000 0300 |
0x4000 1300 |
|
RW |
32 |
0x0000 0000 |
0x0000 0304 |
0x4000 1304 |
|
RW |
32 |
0x0000 0001 |
0x0000 0308 |
0x4000 1308 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4000 1000 | Instance | 0x4000 1000 |
Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0x9B4B | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) NOTE: This IP does not have DTB as part of the Standard IP MMRs. It uses DTBCTL instead. |
RO | 0x1 | ||
11:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP (0-15). | RO | 0x0 | ||
3:0 | MINREV | Minor revision of IP (0-15). | RO | 0x0 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4000 1044 | Instance | 0x4000 1044 |
Description | Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
RW | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
RW | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
RW | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG or HFXTDYN are reached. Applies to Q1CAP, Q2CAP and IREF. |
RW | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
RW | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
RW | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
RW | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
RW | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
RW | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
RW | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
RW | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
RW | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
RW | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
RW | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
RW | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | RW | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
RW | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
RW | 0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4000 1048 | Instance | 0x4000 1048 |
Description | Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
RO | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
RO | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
RO | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG or HFXTDYN are reached. Applies to Q1CAP, Q2CAP and IREF. |
RO | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
RO | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
RO | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
RO | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
RO | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
RO | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
RO | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
RO | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
RO | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
RO | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
RO | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
RO | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | RO | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
RO | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
RO | 0 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4000 104C | Instance | 0x4000 104C |
Description | Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
RO | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
RO | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
RO | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG or HFXTDYN are reached. Applies to Q1CAP, Q2CAP and IREF. |
RO | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
RO | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
RO | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
RO | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
RO | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
RO | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
RO | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
RO | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
RO | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
RO | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
RO | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
RO | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | RO | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
RO | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
RO | 0 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4000 1050 | Instance | 0x4000 1050 |
Description | Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
WO | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
WO | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
WO | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG.Q1CAP, HFXTTARG.Q2CAP and HFXTTARG.IREF or HFXTDYN.Q1CAP, HFXTDYN.Q2CAP and HFXTDYN.IREF are reached. |
WO | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
WO | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
WO | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
WO | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
WO | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
WO | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
WO | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
WO | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
WO | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
WO | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
WO | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
WO | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | WO | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
WO | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
WO | 0 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4000 1054 | Instance | 0x4000 1054 |
Description | Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
WO | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
WO | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
WO | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG or HFXTDYN are reached. Applies to Q1CAP, Q2CAP and IREF. |
WO | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
WO | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
WO | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
WO | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
WO | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
WO | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
WO | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
WO | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
WO | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
WO | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
WO | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
WO | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | WO | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
WO | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
WO | 0 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4000 1058 | Instance | 0x4000 1058 |
Description | Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
WO | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
WO | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
WO | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG or HFXTDYN are reached. Applies to Q1CAP, Q2CAP and IREF. |
WO | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
WO | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
WO | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
WO | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
WO | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
WO | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
WO | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
WO | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
WO | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
WO | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
WO | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
WO | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | WO | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
WO | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
WO | 0 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4000 105C | Instance | 0x4000 105C |
Description | Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
17 | LFTICK | 32kHz TICK to RTC and WDT. Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK. |
WO | 0 | ||
16 | LFGEARRSTRT | LFINC filter gearing restart. Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation. |
WO | 0 | ||
15 | AMPSETTLED | HFXT Amplitude compensation - settled Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state, and the controls configured in HFXTTARG or HFXTDYN are reached. |
WO | 0 | ||
14 | AMPCTRLATTARG | HFXT Amplitude compensation - controls at target Indicates that the control values configured in HFXTTARG or HFXTDYN are reached. Applies to Q1CAP, Q2CAP and IREF. |
WO | 0 | ||
13 | PRELFEDGE | Pre-LF clock edge detect. Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE. Can be used by software to confirm that a LF clock source is running and within the expected frequency, before selecting it as the main LF clock source. |
WO | 0 | ||
12 | LFCLKLOSS | LF clock is lost. Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period). The system will automatically fall-back to generating LFTICK based on CLKULL, to avoid timing corruption. Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY. |
WO | 0 | ||
11 | LFCLKOOR | LF clock period out-of-range. Indicates that a LF clock period was measured to be out-of-range, according to LFQUALCTL.MAXERR. |
WO | 0 | ||
10 | LFCLKGOOD | LF clock good. Indicates that the LF clock is good, according to the configuration in LFQUALCTL. |
WO | 0 | ||
9 | LFINCUPD | LFINC updated. Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC. |
WO | 0 | ||
8 | TDCDONE | TDC done event. Indicates that the TDC measurement is done. |
WO | 0 | ||
7 | ADCPEAKUPD | HFXT-ADC PEAK measurement update event. Indicates that the HFXT-ADC PEAK measurement is done. |
WO | 0 | ||
6 | ADCBIASUPD | HFXT-ADC BIAS measurement update event. Indicates that the HFXT-ADC BIAS measurement is done. |
WO | 0 | ||
5 | ADCCOMPUPD | HFXT-ADC comparison update event. Indicates that the HFXT-ADC comparison is done. |
WO | 0 | ||
4 | TRACKREFOOR | Out-of-range indication from the tracking loop. Indicates that the selected reference clock frequency of the tracking loop is out-of-range. |
WO | 0 | ||
3 | TRACKREFLOSS | Clock loss indication from the tracking loop. Indicates that the selected reference clock of the tracking loop is lost. |
WO | 0 | ||
2 | HFXTAMPGOOD | HFXT amplitude good indication. | WO | 0 | ||
1 | HFXTFAULT | HFXT fault indication. Indicates that HFXT did not start correctly, or its frequency is too low. HFXT will not recover from this fault and has to be restarted. This is only a one-time check at HFXT startup. |
WO | 0 | ||
0 | HFXTGOOD | HFXT good indication. Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation. This is only a one-time check at HFXT startup. |
WO | 0 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4000 1080 | Instance | 0x4000 1080 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | PW | Internal. Only to be used through TI provided API. | WO | 0x00 | |||||||||||
23:9 | RESERVED9 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 0000 0000 | |||||||||||
8 | CLKSVTOVR | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
7:2 | RESERVED2 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 | |||||||||||
1 | FORCEOFF | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
0 | QUALBYP | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4000 1084 | Instance | 0x4000 1084 |
Description | High frequency crystal control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | AMPOVR | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
30:27 | RESERVED27 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | |||||||||||
26 | BIASEN | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
25 | LPBUFEN | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
24 | INJECT | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
23 | QUALBYP | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
22:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
19:8 | QUALDLY | Skip potentially unstable clock cycles after enabling HFXT. Number of cycles skipped is 8*QUALDLY. |
RW | 0x000 | |||||||||||
7 | TCXOMODE | Temperature compensated crystal oscillator mode. Set this bit if a TXCO is connected. |
RW | 0 | |||||||||||
6 | TCXOTYPE | Type of temperature compensated crystal used. Only has effect if TCXOMODE is set.
|
RW | 0 | |||||||||||
5:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
2 | AUTOEN | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
1 | HPBUFEN | High performance clock buffer enable. This bit controls the clock output for the RF PLL. It is required for radio operation. |
RW | 0 | |||||||||||
0 | EN | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4000 108C | Instance | 0x4000 108C |
Description | Low frequency oscillator control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | LFOSC enable | RW | 0 |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4000 1090 | Instance | 0x4000 1090 |
Description | Low frequency crystal control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||||||||||||||
14:13 | LEAKCOMP | Leakage compensation control
|
RW | 0b00 | ||||||||||||||
12 | BUFBIAS | Control the BIAS current of the input amp in LP buffer
|
RW | 0 | ||||||||||||||
11:8 | AMPBIAS | Adjust current mirror ratio into oscillator core. This value is depending on crystal and is set by FW. This field uses a 2's complement encoding. | RW | 0x0 | ||||||||||||||
7:6 | BIASBOOST | Boost oscillator amplitude This value depends on the crystal and needs to be configured by Firmware. |
RW | 0b00 | ||||||||||||||
5:4 | REGBIAS | Regulation loop bias resistor value This value depends on the crystal and needs to be configured by Firmware. |
RW | 0b00 | ||||||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||
2 | HPBUFEN | Control the buffer used. In normal operation, low-power buffer is used in all device modes. The high-performance buffer is only used for test purposes. | RW | 0 | ||||||||||||||
1 | AMPREGMODE | Amplitude regulation mode
|
RW | 0 | ||||||||||||||
0 | EN | LFXT enable | RW | 0 |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4000 1094 | Instance | 0x4000 1094 |
Description | Low frequency clock qualification control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | ||
13:8 | MAXERR | Maximum LFCLK period error. Value given in microseconds, 3 integer bits + 3 fractional bits. |
RW | 0b10 0000 | ||
7:0 | CONSEC | Number of consecutive times the LFCLK period error has to be smaller than MAXERR to be considered "good". Setting this value to 0 will bypass clock qualification, and the "good" indicator will always be 1. |
RW | 0x64 |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4000 1098 | Instance | 0x4000 1098 |
Description | Low frequency time increment control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31 | PREVENTSTBY | Controls if the LFINC filter prevents STANBY entry until settled.
|
RW | 1 | |||||||||||||||||
30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||
29:8 | INT | Integral part of the LFINC filter. This value is updated by Hardware to reflect the current state of the filter. It can also be written to change the current state. |
RW | 0b01 1110 1000 0100 1000 0000 | |||||||||||||||||
7 | STOPGEAR | Controls the final gear of the LFINC filter.
|
RW | 0 | |||||||||||||||||
6:5 | ERRTHR | Controls the threshold for gearing restart of the LFINC filter. Only effective if GEARRSTRT is not ONETHR or TWOTHR.
|
RW | 0b00 | |||||||||||||||||
4:3 | GEARRSTRT | Controls gearing restart of the LFINC filter.
|
RW | 0b10 | |||||||||||||||||
2 | SOFTRSTRT | Use a higher gear after re-enabling / wakeup. The filter will require 16-24 LFCLK periods to settle (depending on STOPGEAR), but may respond faster to frequency changes during STANDBY.
|
RW | 1 | |||||||||||||||||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 |
Address Offset | 0x0000 009C | ||
Physical Address | 0x4000 109C | Instance | 0x4000 109C |
Description | Low frequency time increment override control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31 | OVERRIDE | Override LF increment Use the value provided in LFINC instead of the value calculated by Hardware. |
RW | 0 | ||
30:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
21:0 | LFINC | LF increment value This value is used when OVERRIDE is set to 1. Otherwise the value is calculated automatically. |
RW | 0b00 0000 0000 0000 0000 0000 |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4000 10A0 | Instance | 0x4000 10A0 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | SWOVR | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
30:18 | RESERVED18 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 | |||||||||||
17 | PEAKDETEN | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
16 | ADCEN | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
15 | RESERVED15 | Internal. Only to be used through TI provided API. | RO | 0 | |||||||||||
14:8 | COMPVAL | Internal. Only to be used through TI provided API. | RW | 0b000 0000 | |||||||||||
7:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RO | 0b000 | |||||||||||
4 | SRCSEL | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||
3:2 | RESERVED2 | Internal. Only to be used through TI provided API. | RO | 0b00 | |||||||||||
1 | COMPSTRT | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
0 | SARSTRT | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x4000 10A4 | Instance | 0x4000 10A4 |
Description | High frequency tracking loop control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31 | EN | Enable tracking loop. | RW | 0 | ||||||||||||||
30 | DSMBYP | Bypass Delta-Sigma-Modulation of fine trim. | RW | 0 | ||||||||||||||
29:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||||||||||||||
27:26 | REFCLK | Select the reference clock for the tracking loop. Change only while the tracking loop is disabled.
|
RW | 0b00 | ||||||||||||||
25:0 | RATIO | Reference clock ratio. RATIO = 24MHz / (2*reference-frequency) * 2^24 Commonly used reference clock frequencies are provided as enumerations.
|
RW | 0b00 0100 0000 0000 0000 0000 0000 |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4000 10A8 | Instance | 0x4000 10A8 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31 | SWOVR | Internal. Only to be used through TI provided API. | RW | 0 | ||
30:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
4 | HFXTLVLEN | Internal. Only to be used through TI provided API. | RW | 0 | ||
3 | STARTCTL | Internal. Only to be used through TI provided API. | RW | 0 | ||
2 | START | Internal. Only to be used through TI provided API. | RW | 0 | ||
1 | BYPASS | Internal. Only to be used through TI provided API. | RW | 0 | ||
0 | EN | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4000 10AC | Instance | 0x4000 10AC |
Description | Nanoamp-bias control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Enable nanoamp-bias | RW | 0 |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x4000 10B0 | Instance | 0x4000 10B0 |
Description | Low-frequency clock-monitor control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Enable LFMONITOR. Enable only after a LF clock source has been selected, enabled and is stable. If LFMONITOR detects a clock loss, the system will be reset. |
RW | 0 |
Address Offset | 0x0000 00C0 | ||
Physical Address | 0x4000 10C0 | Instance | 0x4000 10C0 |
Description | Low frequency clock selection | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||
3:2 | PRE | Select low frequency clock source for the PRELFCLK interrupt. Can be used by Software to confirm that the clock is running and it's frequency is good, before selecting it in MAIN.
|
RW | 0b00 | |||||||||||||||||
1:0 | MAIN | Select the main low frequency clock source. If running, this clock will be used to generate LFTICK and as CLKULL during STANDBY. If not running, LFTICK will be generated from HFOSC and STANDBY entry will be prevented.
|
RW | 0b00 |
Address Offset | 0x0000 00C4 | ||
Physical Address | 0x4000 10C4 | Instance | 0x4000 10C4 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:2 | RESERVED2 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
1:0 | REFCLK | Internal. Only to be used through TI provided API.
|
RW | 0b00 |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x4000 10C8 | Instance | 0x4000 10C8 |
Description | ADC clock selection | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1:0 | SRC | Select ADC clock source Change only while ADC is disabled.
|
RW | 0b00 |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x4000 10E0 | Instance | 0x4000 10E0 |
Description | Low-frequency clock status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31 | GOOD | Low frequency clock good Note: This is only a coarse frequency check based on LFQUALCTL. The clock may not be accurate enough for timing purposes. |
RO | 0 | |||||||||||||||||
30:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||||||||
25 | FLTSETTLED | LFINC filter is running and settled. | RO | 0 | |||||||||||||||||
24 | LFTICKSRC | Source of LFTICK.
|
RO | 0 | |||||||||||||||||
23:22 | LFINCSRC | Source of LFINC used by the RTC. This value depends on LFINCOVR.OVERRIDE, LF clock availability, HF tracking loop status and the device state (ACTIVE/STANDBY).
|
RO | 0b00 | |||||||||||||||||
21:0 | LFINC | Measured value of LFINC. Given in microseconds with 16 fractional bits. This value is calculated by Hardware. It is the LFCLK period according to CLKULL cycles. |
RO | 0b00 0000 0000 0000 0000 0000 |
Address Offset | 0x0000 00E4 | ||
Physical Address | 0x4000 10E4 | Instance | 0x4000 10E4 |
Description | HFXT status information | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
30:16 | STARTUPTIME | HFXT startup time Can be used by software to plan starting HFXT ahead in time. Measured whenever HFXT is enabled in CLKULL periods (24MHz), from HFXTCTL.EN until the clock is good for radio operation (amplitude compensation is settled). |
RO | 0b000 0000 0000 0000 | ||
15:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
1 | FAULT | HFXT clock fault Indicates a lower than expected HFXT frequency. HFXT will not recover from this fault, disabling and re-enabling HFXT is required. |
RO | 0 | ||
0 | GOOD | HFXT clock available. The frequency is not necessarily good enough for radio operation. |
RO | 0 |
Address Offset | 0x0000 00E8 | ||
Physical Address | 0x4000 10E8 | Instance | 0x4000 10E8 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:25 | RESERVED25 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 | ||
24 | COMPOUT | Internal. Only to be used through TI provided API. | RO | 0 | ||
23 | RESERVED23 | Internal. Only to be used through TI provided API. | RO | 0 | ||
22:16 | PEAKRAW | Internal. Only to be used through TI provided API. | RO | 0b000 0000 | ||
15:8 | PEAK | Internal. Only to be used through TI provided API. | RO | 0x00 | ||
7 | RESERVED7 | Internal. Only to be used through TI provided API. | RO | 0 | ||
6:0 | BIAS | Internal. Only to be used through TI provided API. | RO | 0b000 0000 |
Address Offset | 0x0000 00EC | ||
Physical Address | 0x4000 10EC | Instance | 0x4000 10EC |
Description | HFOSC tracking loop status information | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31 | LOOPERRVLD | Current HFOSC tracking error valid This bit is one if the tracking loop is running and the error value is valid. |
RO | 0 | ||
30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
29:16 | LOOPERR | Current HFOSC tracking error | RO | 0b00 0000 0000 0000 | ||
15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
12:0 | FINETRIM | Current HFOSC Fine-trim value This field uses the internal fractional representation (sign, 4 integer bits, 8 fractional bits). The actual trim value applied to the oscillator is delta-sigma modulated 5 bits non-signed (inverted sign bit + integer bits). |
RO | 0b0 0000 0000 0000 |
Address Offset | 0x0000 00F0 | ||
Physical Address | 0x4000 10F0 | Instance | 0x4000 10F0 |
Description | HFXT Amplitude Compensation Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||
28:25 | STATE | Current AMPCOMP FSM state.
|
RO | 0x0 | |||||||||||||||||||||||||||||||||||||||||
24:18 | IDAC | Current IDAC control value. | RO | 0b000 0000 | |||||||||||||||||||||||||||||||||||||||||
17:14 | IREF | Current IREF control value. | RO | 0x0 | |||||||||||||||||||||||||||||||||||||||||
13:8 | Q2CAP | Current Q2CAP control value. | RO | 0b00 0000 | |||||||||||||||||||||||||||||||||||||||||
7:2 | Q1CAP | Current Q1CAP control value. | RO | 0b00 0000 | |||||||||||||||||||||||||||||||||||||||||
1 | CTRLATTARGET | HFXT control values match target values. This applies to IREF, Q1CAP, Q2CAP values. |
RO | 0 | |||||||||||||||||||||||||||||||||||||||||
0 | AMPGOOD | HFXT amplitude good | RO | 0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4000 1100 | Instance | 0x4000 1100 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:19 | RESERVED19 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
18:0 | SEL | Internal. Only to be used through TI provided API.
|
RW | 0b000 0000 0000 0000 0000 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4000 1104 | Instance | 0x4000 1104 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:15 | RESERVED15 | Internal. Only to be used through TI provided API. | RO | 0b0 0000 0000 0000 0000 | |||||||||||||||||
14:13 | LFOSC | Internal. Only to be used through TI provided API.
|
RW | 0b00 | |||||||||||||||||
12 | NABIAS | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||||||||
11 | RESERVED11 | Internal. Only to be used through TI provided API. | RO | 0 | |||||||||||||||||
10 | LFXT | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||||||||
9:8 | LFMON | Internal. Only to be used through TI provided API.
|
RW | 0b00 | |||||||||||||||||
7 | HFXT | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||||||||
6:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 | |||||||||||||||||
0 | HFOSC | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4000 1108 | Instance | 0x4000 1108 |
Description | Digital test bus mux control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | |||||||||||||||||||||||||||||||||||
22:18 | DSEL2 | Internal. Only to be used through TI provided API. | RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||
17:13 | DSEL1 | Internal. Only to be used through TI provided API. | RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||
12:8 | DSEL0 | Internal. Only to be used through TI provided API. | RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||
7:4 | CLKSEL | Select clock to output on DTB[0]
|
RW | 0x0 | |||||||||||||||||||||||||||||||||||
3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||
0 | EN | Enable DTB output | RW | 0 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4000 1110 | Instance | 0x4000 1110 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:9 | RESERVED9 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 0000 0000 0000 0000 | ||
8:5 | HFOSC_CAP | Internal. Only to be used through TI provided API. | RW | 0x0 | ||
4:0 | HFOSC_COARSE | Internal. Only to be used through TI provided API. | RW | 0b0 0000 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4000 1114 | Instance | 0x4000 1114 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:30 | HFXTSLICER | Internal. Only to be used through TI provided API. | RW | 0b00 | ||
29:28 | PEAKIBIAS | Internal. Only to be used through TI provided API. | RW | 0b00 | ||
27 | NABIAS_UDIGLDO | Internal. Only to be used through TI provided API. | RW | 0 | ||
26:24 | LDOBW | Internal. Only to be used through TI provided API. | RW | 0b000 | ||
23:20 | LDOFB | Internal. Only to be used through TI provided API. | RW | 0x6 | ||
19:16 | LFDLY | Internal. Only to be used through TI provided API. | RW | 0xF | ||
15 | NABIAS_LFOSC | Internal. Only to be used through TI provided API. | RW | 1 | ||
14:8 | NABIAS_RES | Internal. Only to be used through TI provided API. | RW | 0b001 0100 | ||
7:0 | LFOSC_CAP | Internal. Only to be used through TI provided API. | RW | 0xD6 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4000 1118 | Instance | 0x4000 1118 |
Description | Initial values for HFXT ramping | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
29:23 | AMPTHR | Amplitude threshold during HFXT ramping | RW | 0b010 1000 | ||
22:16 | IDAC | Initial HFXT IDAC current | RW | 0b111 1111 | ||
15:12 | IREF | Initial HFXT IREF current | RW | 0x8 | ||
11:6 | Q2CAP | Initial HFXT Q2 cap trim | RW | 0b00 0000 | ||
5:0 | Q1CAP | Initial HFXT Q1 cap trim | RW | 0b00 0000 |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4000 111C | Instance | 0x4000 111C |
Description | Target values for HFXT ramping | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:30 | AMPHYST | ADC hysteresis used during IDAC updates. Every AMPCFG1.INTERVAL, IDAC will be regulated - up as long as ADC < AMPTHR - down as long as ADC > AMPTHR+AMPHYST |
RW | 0b01 | ||
29:23 | AMPTHR | Minimum HFXT amplitude | RW | 0b010 1000 | ||
22:16 | IDAC | Minimum IDAC current | RW | 0b100 0110 | ||
15:12 | IREF | Target HFXT IREF current | RW | 0x4 | ||
11:6 | Q2CAP | Target HFXT Q2 cap trim | RW | 0b10 1101 | ||
5:0 | Q1CAP | Target HFXT Q1 cap trim | RW | 0b10 1101 |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4000 1120 | Instance | 0x4000 1120 |
Description | Alternative target values for HFXT configuration Software can change these values to dynamically transition the HFXT configuration while HFXT is running. Set SEL to select the alternative set of target values. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | SEL | Select the dynamic configuration. Amplitude ramping will always happen using the values in HFXTINIT, and HFXTTARG. Afterwards, this bit can be used to select between HFXTTARG and HFXTDYN. Hardware will ensure a smooth transition of analog control signals.
|
RW | 0 | |||||||||||
30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
29:23 | AMPTHR | Minimum HFXT amplitude | RW | 0b010 1000 | |||||||||||
22:16 | IDAC | Minimum IDAC current | RW | 0b100 0110 | |||||||||||
15:12 | IREF | Target HFXT IREF current | RW | 0x4 | |||||||||||
11:6 | Q2CAP | Target HFXT Q2 cap trim | RW | 0b10 1101 | |||||||||||
5:0 | Q1CAP | Target HFXT Q1 cap trim | RW | 0b10 1101 |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4000 1124 | Instance | 0x4000 1124 |
Description | Amplitude Compensation Configuration 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||
31:28 | Q2DLY | Q2CAP change delay. Number of clock cycles to wait before changing Q2CAP by one step. Clock frequency defined in FSMRATE. |
RW | 0x0 | |||||||||||||||||||||||
27:24 | Q1DLY | Q1CAP change delay. Number of clock cycles to wait before changing Q1CAP by one step. Clock frequency defined in FSMRATE. |
RW | 0x0 | |||||||||||||||||||||||
23:20 | ADCDLY | ADC and PEAKDET startup time. Number of clock cycles to wait after enabling the PEAKDET and ADC before the first measurement. Clock frequency defined in FSMRATE. |
RW | 0x3 | |||||||||||||||||||||||
19:15 | LDOSTART | LDO startup time. Number of clock cycles to bypass the LDO resistors for faster startup. Clock frequency defined in FSMRATE. |
RW | 0b0 1001 | |||||||||||||||||||||||
14:10 | INJWAIT | Inject HFOSC for faster HFXT startup. This value specifies the number of clock cycles to wait after injection is done. The clock speed is defined in FSMRATE. |
RW | 0b0 0010 | |||||||||||||||||||||||
9:5 | INJTIME | Inject HFOSC for faster HFXT startup. This value specifies the number of clock cycles the injection is enabled. The clock speed is defined in FSMRATE. Set to 0 to disable injection. |
RW | 0b0 0100 | |||||||||||||||||||||||
4:0 | FSMRATE | Update rate for the AMPCOMP update rate. Also affects the clock rate for the Amplitude ADC. The update rate is 6MHz / (FSMRATE+1).
|
RW | 0b0 0010 |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4000 1128 | Instance | 0x4000 1128 |
Description | Amplitude Compensation Configuration 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IDACDLY | IDAC change delay. Time to wait before changing IDAC by one step. This time needs to be long enough for the crystal to settle. The number of clock cycles to wait is IDACDLY<<4 + 15. Clock frequency defined in AMPCFG0.FSMRATE. |
RW | 0x2 | ||
27:24 | IREFDLY | IREF change delay. Number of clock cycles to wait before changing IREF by one step. Clock frequency defined in AMPCFG0.FSMRATE. |
RW | 0x6 | ||
23:12 | BIASLT | Lifetime of the amplitude ADC bias value. This value specifies the number of adjustment intervals, until the ADC bias value has to be measured again. Set to 0 to disable automatic bias measurements. |
RW | 0x0FF | ||
11:0 | INTERVAL | Interval for amplitude adjustments. Set to 0 to disable periodic adjustments. This value specifies the number of clock cycles between adjustments. The clock speed is defined in AMPCFG0.FSMRATE. |
RW | 0x0FF |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4000 112C | Instance | 0x4000 112C |
Description | Configuration Register for the Tracking Loop | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:26 | FINETRIM_INIT | Initial value for the resistor fine trim | RW | 0b01 1000 | ||
25:21 | BOOST_TARGET | Number of error-updates using BOOST values, before using KI/KP | RW | 0b0 0010 | ||
20:18 | KP_BOOST | Proportional loop coefficient during BOOST | RW | 0b111 | ||
17:15 | KI_BOOST | Integral loop coefficient during BOOST | RW | 0b100 | ||
14:10 | SETTLED_TARGET | Number of updates before HFOSC is considered "settled" | RW | 0b0 1100 | ||
9:6 | OOR_LIMIT | Out-of-range threshold | RW | 0xE | ||
5:3 | KP | Proportional loop coefficient | RW | 0b110 | ||
2:0 | KI | Integral loop coefficient | RW | 0b011 |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x4000 1200 | Instance | 0x4000 1200 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:2 | RESERVED2 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
1:0 | CMD | Internal. Only to be used through TI provided API.
|
WO | 0b00 |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x4000 1204 | Instance | 0x4000 1204 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:10 | RESERVED10 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||
9 | STOP_BF | Internal. Only to be used through TI provided API. | RO | 0 | ||||||||||||||||||||||||||||||||||||||
8 | START_BF | Internal. Only to be used through TI provided API. | RO | 0 | ||||||||||||||||||||||||||||||||||||||
7 | SAT | Internal. Only to be used through TI provided API. | RO | 0 | ||||||||||||||||||||||||||||||||||||||
6 | DONE | Internal. Only to be used through TI provided API. | RO | 0 | ||||||||||||||||||||||||||||||||||||||
5:0 | STATE | Internal. Only to be used through TI provided API.
|
RO | 0b00 0110 |
Address Offset | 0x0000 0208 | ||
Physical Address | 0x4000 1208 | Instance | 0x4000 1208 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VALUE | Internal. Only to be used through TI provided API. | RO | 0x0000 0002 |
Address Offset | 0x0000 020C | ||
Physical Address | 0x4000 120C | Instance | 0x4000 120C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | LIMIT | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x4000 1210 | Instance | 0x4000 1210 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | RESERVED16 | Internal. Only to be used through TI provided API. | RO | 0x0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | STOP_POL | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:13 | RESERVED13 | Internal. Only to be used through TI provided API. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12:8 | STOP_SRC | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | START_POL | Internal. Only to be used through TI provided API.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | START_SRC | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x4000 1214 | Instance | 0x4000 1214 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Internal. Only to be used through TI provided API. | RO | 0x0000 | ||
15:0 | CNT | Internal. Only to be used through TI provided API. | RW | 0x0000 |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x4000 1218 | Instance | 0x4000 1218 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Internal. Only to be used through TI provided API. | RO | 0x0000 | ||
15:0 | CNT | Internal. Only to be used through TI provided API. | RW | 0x0000 |
Address Offset | 0x0000 021C | ||
Physical Address | 0x4000 121C | Instance | 0x4000 121C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 0220 | ||
Physical Address | 0x4000 1220 | Instance | 0x4000 1220 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Internal. Only to be used through TI provided API. | RO | 0x00 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | RESET_N | Internal. Only to be used through TI provided API. | RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | RATIO | Internal. Only to be used through TI provided API.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | RESERVED5 | Internal. Only to be used through TI provided API. | RO | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | SRC | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0224 | ||
Physical Address | 0x4000 1224 | Instance | 0x4000 1224 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED17 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 0000 0000 | ||
16 | CAPT | Internal. Only to be used through TI provided API. | WO | 0 | ||
15:0 | CNT | Internal. Only to be used through TI provided API. | RO | 0x0000 |
Address Offset | 0x0000 0300 | ||
Physical Address | 0x4000 1300 | Instance | 0x4000 1300 |
Description | WDT counter value register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Counter value. A write to this field immediately starts (or restarts) the counter. It will count down from the written value. If the counter reaches 0, a reset will be generated. A write value of 0 immediately generates a reset. This field is only writable if not locked. See WDTLOCK register. Writing this field will automatically activate the lock. A read returns the current value of the counter. |
RW | 0x0000 0000 |
Address Offset | 0x0000 0304 | ||
Physical Address | 0x4000 1304 | Instance | 0x4000 1304 |
Description | WDT test mode register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | STALLEN | WDT stall enable This field is only writable if not locked. See WDTLOCK register.
|
RW | 0 |
Address Offset | 0x0000 0308 | ||
Physical Address | 0x4000 1308 | Instance | 0x4000 1308 |
Description | WDT lock register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | STAT | A write with value 0x1ACCE551 unlocks the watchdog registers for write access. A write with any other value locks the watchdog registers for write access. Writing the WDTCNT register will also lock the watchdog registers. A read of this field returns the state of the lock (0=unlocked, 1=locked). |
RW | 0x0000 0001 |
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