Instance: FCFG2
Component: FCFG2
Base address: 0x50002800
Factory configuration area (FCFG2)
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x0000 0000 |
0x0000 0000 |
0x5000 2800 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x5000 2804 |
|
|
RO |
32 |
0xF000 0000 |
0x0000 0008 |
0x5000 2808 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 000C |
0x5000 280C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x5000 2810 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x5000 2814 |
|
|
RO |
32 |
0xF000 0000 |
0x0000 0018 |
0x5000 2818 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x5000 281C |
|
|
RO |
32 |
0xFC55 9400 |
0x0000 0020 |
0x5000 2820 |
|
|
RO |
32 |
0x1920 0000 |
0x0000 0024 |
0x5000 2824 |
|
|
RO |
32 |
0xC0B4 C53A |
0x0000 0028 |
0x5000 2828 |
|
|
RO |
32 |
0xFFFF FF53 |
0x0000 002C |
0x5000 282C |
|
|
RO |
32 |
0xFFFF FF55 |
0x0000 0030 |
0x5000 2830 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x5000 2800 | Instance | 0x5000 2800 |
| Description | Configuration register for bank0 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED32 | Configuration value written to FLASH:BANK0_TRIM_CFG_3.RESERVED32 by ROM boot FW | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x5000 2804 | Instance | 0x5000 2804 |
| Description | Configuration register for bank0 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED32 | Configuration value written to FLASH:BANK0_TRIM_CFG_2.RESERVED32 by ROM boot FW | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x5000 2808 | Instance | 0x5000 2808 |
| Description | Configuration register for bank0 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
| 27:22 | REDSWSELW3 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWSELW3 by ROM boot FW | RO | 0b00 0000 | ||
| 21:16 | REDSWSELW2 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWSELW2 by ROM boot FW | RO | 0b00 0000 | ||
| 15:10 | REDSWSELW1 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWSELW1 by ROM boot FW | RO | 0b00 0000 | ||
| 9:4 | REDSWSELW0 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWSELW0 by ROM boot FW | RO | 0b00 0000 | ||
| 3 | REDSWENW3 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWENW3 by ROM boot FW | RO | 0 | ||
| 2 | REDSWENW2 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWENW2 by ROM boot FW | RO | 0 | ||
| 1 | REDSWENW1 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWENW1 by ROM boot FW | RO | 0 | ||
| 0 | REDSWENW0 | Configuration value written to FLASH:BANK0_TRIM_CFG_1.REDSWENW0 by ROM boot FW | RO | 0 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x5000 280C | Instance | 0x5000 280C |
| Description | Configuration register for bank0 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | BANK0_TRIM_CFG_0 | Configuration value written to FLASH:BANK0_TRIM_CFG_0.BANK0_TRIM_CFG_0 by ROM boot FW | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x5000 2810 | Instance | 0x5000 2810 |
| Description | Configuration register for bank1 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED32 | Configuration value written to FLASH:BANK1_TRIM_CFG_3.RESERVED32 by ROM boot FW | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x5000 2814 | Instance | 0x5000 2814 |
| Description | Configuration register for bank1 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED32 | Configuration value written to FLASH:BANK1_TRIM_CFG_2.RESERVED32 by ROM boot FW | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x5000 2818 | Instance | 0x5000 2818 |
| Description | Configuration register for bank1 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
| 27:22 | REDSWSELW3 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWSELW3 by ROM boot FW | RO | 0b00 0000 | ||
| 21:16 | REDSWSELW2 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWSELW2 by ROM boot FW | RO | 0b00 0000 | ||
| 15:10 | REDSWSELW1 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWSELW1 by ROM boot FW | RO | 0b00 0000 | ||
| 9:4 | REDSWSELW0 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWSELW0 by ROM boot FW | RO | 0b00 0000 | ||
| 3 | REDSWENW3 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWENW3 by ROM boot FW | RO | 0 | ||
| 2 | REDSWENW2 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWENW2 by ROM boot FW | RO | 0 | ||
| 1 | REDSWENW1 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWENW1 by ROM boot FW | RO | 0 | ||
| 0 | REDSWENW0 | Configuration value written to FLASH:BANK1_TRIM_CFG_1.REDSWENW0 by ROM boot FW | RO | 0 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x5000 281C | Instance | 0x5000 281C |
| Description | Configuration register for bank1 trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | BANK1_TRIM_CFG_0 | Configuration value written to FLASH:BANK1_TRIM_CFG_0.BANK1_TRIM_CFG_0 by ROM boot FW | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x5000 2820 | Instance | 0x5000 2820 |
| Description | Configuration register for flash pump trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 1111 | ||
| 25:20 | VWLCT | Configuration value written to FLASH:PUMP_TRIM_CFG_2.VWLCT by ROM boot FW | RO | 0b00 0101 | ||
| 19:14 | VSLCT | Configuration value written to FLASH:PUMP_TRIM_CFG_2.VSLCT by ROM boot FW | RO | 0b01 0110 | ||
| 13:9 | VREADCT | Configuration value written to FLASH:PUMP_TRIM_CFG_2.VREADCT by ROM boot FW | RO | 0b0 1010 | ||
| 8:4 | VINLOWCCORCT | Configuration value written to FLASH:PUMP_TRIM_CFG_2.VINLOWCCORCT by ROM boot FW | RO | 0b0 0000 | ||
| 3:0 | VINHICCORCT | Configuration value written to FLASH:PUMP_TRIM_CFG_2.VINHICCORCT by ROM boot FW | RO | 0x0 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x5000 2824 | Instance | 0x5000 2824 |
| Description | Configuration register for flash pump trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | VINHICCORCTLSB | Configuration value written to FLASH:PUMP_TRIM_CFG_1.VINHICCORCTLSB by ROM boot FW | RO | 0 | ||
| 30:25 | VINHCT | Configuration value written to FLASH:PUMP_TRIM_CFG_1.VINHCT by ROM boot FW | RO | 0b00 1100 | ||
| 24:20 | VCGCT | Configuration value written to FLASH:PUMP_TRIM_CFG_1.VCGCT by ROM boot FW | RO | 0b1 0010 | ||
| 19:15 | IREFVRDCT | Configuration value written to FLASH:PUMP_TRIM_CFG_1.IREFVRDCT by ROM boot FW | RO | 0b0 0000 | ||
| 14:10 | IREFTCCT | Configuration value written to FLASH:PUMP_TRIM_CFG_1.IREFTCCT by ROM boot FW | RO | 0b0 0000 | ||
| 9:6 | IREFCT | Configuration value written to FLASH:PUMP_TRIM_CFG_1.IREFCT by ROM boot FW | RO | 0x0 | ||
| 5:0 | FOSCCT | Configuration value written to FLASH:PUMP_TRIM_CFG_1.FOSCCT by ROM boot FW | RO | 0b00 0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0x5000 2828 | Instance | 0x5000 2828 |
| Description | Configuration register for flash pump trims | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
| 29:20 | VHVCT_PV | Configuration value written to FLASH:PUMP_TRIM_CFG_0.VHVCT_PV by ROM boot FW | RO | 0b00 0000 1011 | ||
| 19:10 | VHVCT_PGM | Configuration value written to FLASH:PUMP_TRIM_CFG_0.VHVCT_PGM by ROM boot FW | RO | 0b01 0011 0001 | ||
| 9:0 | VHVCT_ERS | Configuration value written to FLASH:PUMP_TRIM_CFG_0.VHVCT_ERS by ROM boot FW | RO | 0b01 0011 1010 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0x5000 282C | Instance | 0x5000 282C |
| Description | Configuration register for flash read wait cycles | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF FFFF | ||
| 7:4 | WAIT2T | Configuration value written to FLASH:READWAITCFG.WAIT2T by ROM boot FW | RO | 0x5 | ||
| 3:0 | WAIT1T | Configuration value written to FLASH:READWAITCFG.WAIT1T by ROM boot FW | RO | 0x3 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0x5000 2830 | Instance | 0x5000 2830 |
| Description | Configuration register for flash verify wait cycles | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF FFFF | ||
| 7:4 | WAITSTATE1T | Configuration value written to NVMNW:CFGCMD.WAITSTATE by ROM boot FW | RO | 0x5 | ||
| 3:0 | WAITSTATE2T | Configuration value written to NVMNW:CFGCMD.WAITSTATE by flash API in ROM | RO | 0x5 | ||
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