NVMNW

Instance: NVMNW
Component: NVMNW
Base address: 0x58032000


TOP:NVMNW Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IIDX

RO

32

0x0000 0000

0x0000 0020

0x5803 2020

IMASK

RW

32

0x0000 0000

0x0000 0028

0x5803 2028

RIS

RO

32

0x0000 0000

0x0000 0030

0x5803 2030

MIS

RO

32

0x0000 0000

0x0000 0038

0x5803 2038

ISET

WO

32

0x0000 0000

0x0000 0040

0x5803 2040

ICLR

WO

32

0x0000 0000

0x0000 0048

0x5803 2048

EVT_MODE

RO

32

0x0000 0001

0x0000 00E0

0x5803 20E0

DESC

RO

32

0x0B40 0010

0x0000 00FC

0x5803 20FC

CMDEXEC

RW

32

0x0000 0000

0x0000 0100

0x5803 2100

CMDTYPE

RW

32

0bXXXX XXXX XXXX XXXX XXXX XXXX X000 0000

0x0000 0104

0x5803 2104

CMDCTL

RW

32

0b0000 0000 0000 0000 1100 000X XXX0 0000

0x0000 0108

0x5803 2108

CMDADDR

RW

32

0x0000 0000

0x0000 0120

0x5803 2120

CMDBYTEN

RW

32

0x0000 FFFF

0x0000 0124

0x5803 2124

CMDDATAINDEX

RW

32

0x0000 0000

0x0000 012C

0x5803 212C

CMDDATA0

RW

32

0xFFFF FFFF

0x0000 0130

0x5803 2130

CMDDATA1

RW

32

0xFFFF FFFF

0x0000 0134

0x5803 2134

CMDDATA2

RW

32

0xFFFF FFFF

0x0000 0138

0x5803 2138

CMDDATA3

RW

32

0xFFFF FFFF

0x0000 013C

0x5803 213C

CMDDATA4

RW

32

0xFFFF FFFF

0x0000 0140

0x5803 2140

CMDDATA5

RW

32

0xFFFF FFFF

0x0000 0144

0x5803 2144

CMDDATA6

RW

32

0xFFFF FFFF

0x0000 0148

0x5803 2148

CMDDATA7

RW

32

0xFFFF FFFF

0x0000 014C

0x5803 214C

CMDDATA8

RW

32

0xFFFF FFFF

0x0000 0150

0x5803 2150

CMDDATA9

RW

32

0xFFFF FFFF

0x0000 0154

0x5803 2154

CMDDATA10

RW

32

0xFFFF FFFF

0x0000 0158

0x5803 2158

CMDDATA11

RW

32

0xFFFF FFFF

0x0000 015C

0x5803 215C

CMDDATA12

RW

32

0xFFFF FFFF

0x0000 0160

0x5803 2160

CMDDATA13

RW

32

0xFFFF FFFF

0x0000 0164

0x5803 2164

CMDDATA14

RW

32

0xFFFF FFFF

0x0000 0168

0x5803 2168

CMDDATA15

RW

32

0xFFFF FFFF

0x0000 016C

0x5803 216C

CMDWEPROTA

RW

32

0xFFFF FFFF

0x0000 01D0

0x5803 21D0

CMDWEPROTB

RW

32

0xFFFF FFFF

0x0000 01D4

0x5803 21D4

CMDWEPROTNM

RW

32

0x0000 0001

0x0000 0210

0x5803 2210

CMDWEPROTTR

RW

32

0x0000 0001

0x0000 0214

0x5803 2214

CMDWEPROTEN

RW

32

0x0000 0001

0x0000 0218

0x5803 2218

CFGCMD

RW

32

0x0000 0002

0x0000 03B0

0x5803 23B0

CFGPCNT

RW

32

0x0000 0000

0x0000 03B4

0x5803 23B4

STATCMD

RO

32

0b0000 0000 0000 0000 0000 XXX0 0000 0000

0x0000 03D0

0x5803 23D0

STATADDR

RO

32

0x0020 0000

0x0000 03D4

0x5803 23D4

STATPCNT

RO

32

0x0000 0000

0x0000 03D8

0x5803 23D8

STATMODE

RO

32

0bXXXX XXXX XXXX XX00 XXXX 0000 0000 0000

0x0000 03DC

0x5803 23DC

GBLINFO0

RO

32

0bXXXX XXXX XXXX X010 0000 1000 0000 0000

0x0000 03F0

0x5803 23F0

GBLINFO1

RO

32

0b0000 0000 0000 0100 XXX0 0000 1000 0000

0x0000 03F4

0x5803 23F4

GBLINFO2

RO

32

0x0000 0004

0x0000 03F8

0x5803 23F8

BANK0INFO0

RO

32

0x0000 0100

0x0000 0400

0x5803 2400

BANK0INFO1

RO

32

0x0001 0101

0x0000 0404

0x5803 2404

BANK1INFO0

RO

32

0x0000 0100

0x0000 0410

0x5803 2410

BANK1INFO1

RO

32

0x0001 0101

0x0000 0414

0x5803 2414

DFTEN

RW

32

0x0000 0000

0x0000 0500

0x5803 2500

DFTCMDCTL

RW

32

0b0000 0000 0000 X000 0000 0000 0000 0000

0x0000 0504

0x5803 2504

DFTTIMERCTL

RW

32

0x0000 0000

0x0000 0508

0x5803 2508

DFTEXECZCTL

RW

32

0x0000 0002

0x0000 050C

0x5803 250C

DFTPCLKTESTCTL

RW

32

0x0000 0000

0x0000 0510

0x5803 2510

DFTPCLKTESTSTAT

RO

32

0xXXXX 0000

0x0000 0514

0x5803 2514

DFTDATARED0

RW

32

0x0000 000F

0x0000 0540

0x5803 2540

DFTDATARED1

RW

32

0x0000 000F

0x0000 0544

0x5803 2544

DFTDATARED2

RW

32

0x0000 000F

0x0000 0548

0x5803 2548

DFTDATARED3

RW

32

0x0000 000F

0x0000 054C

0x5803 254C

DFTPUMPCTL

RW

32

0x0000 1000

0x0000 0560

0x5803 2560

DFTBANKCTL

RW

32

0bXXXX XXXX XXXX XXXX XXXX XXX1 0000 0000

0x0000 0564

0x5803 2564

TOP:NVMNW Register Descriptions

TOP:NVMNW:IIDX

Address Offset 0x0000 0020
Physical Address 0x5803 2020 Instance 0x5803 2020
Description Interrupt Index Register:
The IIDX register provides the highest priority enabled interrupt index.

PSD compliant register.
Note that it is not recommended to use this register if the system clock is
running at a slower clock frequency than the NoWrapper clock. If this is the
case, then reading this register may fail to update the RIS register correctly.
The MIS register should be read directly, and a write to ICLR should be used to
clear interrupts when this clock relationship is present.
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt.
Value ENUM Name Description
0x0 NO_INTR No Interrupt Pending
0x1 DONE DONE Interrupt Pending
RO 0

TOP:NVMNW:IMASK

Address Offset 0x0000 0028
Physical Address 0x5803 2028 Instance 0x5803 2028
Description Interrupt Mask Register:
The IMASK register holds the current interrupt mask settings. Masked interrupts
are read in the MIS register. PSD compliant register.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 DONE Interrupt mask for DONE:
0: Interrupt is disabled in MIS register
1: Interrupt is enabled in MIS register
Value ENUM Name Description
0x0 DISABLED Interrupt is masked out
0x1 ENABLED Interrupt will request an interrupt service routine and corresponding bit in IPSTANDARD.MIS will be set
RW 0

TOP:NVMNW:RIS

Address Offset 0x0000 0030
Physical Address 0x5803 2030 Instance 0x5803 2030
Description Raw Interrupt Status Register:
The RIS register reflects all pending interrupts, regardless of masking.
The RIS register allows the user to implement a poll scheme. A flag set in this
register can be cleared by writing a 1 to the ICLR register bit even if the
corresponding IMASK bit is not enabled. A flag can be set by software by writing
a 1 to the ISET register. Reading the IIDX register will also clear the
corresponding bit in RIS. PSD compliant register.
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 DONE NoWrapper operation completed.
This interrupt bit is set by firmware or the corresponding bit in the ISET register.
It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
RO 0

TOP:NVMNW:MIS

Address Offset 0x0000 0038
Physical Address 0x5803 2038 Instance 0x5803 2038
Description Masked Interrupt Status Register:
The MIS register is a bit-wise AND of the contents of the IMASK and RIS
registers. This is kept mainly for ARM compatibility, and has limited use since
the highest priority interrupt index is returned via the IIDX register.
PSD
compliant register.
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 DONE NoWrapper operation completed.
This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
Value ENUM Name Description
0x0 CLR Masked interrupt did not occur
0x1 SET Masked interrupt occurred
RO 0

TOP:NVMNW:ISET

Address Offset 0x0000 0040
Physical Address 0x5803 2040 Instance 0x5803 2040
Description Interrupt Set Register:
The ISET register allows software to write a 1 to set corresponding interrupt.

Safety:
This meets a safety requirement to allow software diagnostics to trigger
interrupts.
PSD compliant register.
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 DONE 0: No effect
1: Set the DONE interrupt in the RIS register
Value ENUM Name Description
0x0 NO_EFFECT Writing a 0 has no effect
0x1 SET Set IPSTANDARD.RIS bit
WO 0

TOP:NVMNW:ICLR

Address Offset 0x0000 0048
Physical Address 0x5803 2048 Instance 0x5803 2048
Description Interrupt Clear Register.
The ICLR register allows allows software to write a 1 to clear corresponding
interrupt.
PSD compliant register.
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 DONE 0: No effect
1: Clear the DONE interrupt in the RIS register
Value ENUM Name Description
0x0 NO_EFFECT Writing a 0 has no effect
0x1 CLR Clear IPSTANDARD.RIS bit
WO 0

TOP:NVMNW:EVT_MODE

Address Offset 0x0000 00E0
Physical Address 0x5803 20E0 Instance 0x5803 20E0
Description Event mode register. It is used to select whether each line is disabled, in
software mode (software clears the RIS) or in hardware mode (hardware
clears the RIS).
Type RO
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 INT0_CFG Event line mode select for peripheral event
Value ENUM Name Description
0x0 DISABLE The interrupt or event line is disabled.
0x1 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
0x2 HARDWARE The interrupt or event line is in hardware mode. Hardware should clear the RIS.
RO 0b01

TOP:NVMNW:DESC

Address Offset 0x0000 00FC
Physical Address 0x5803 20FC Instance 0x5803 20FC
Description Hardware Version Description Register:
This register identifies the NoWrapper hardware version and feature set used.
Type RO
Bits Field Name Description Type Reset
31:16 MODULEID Module ID
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFF MAXIMUM Highest possible value
RO 0x0B40
15:12 FEATUREVER Feature set
Value ENUM Name Description
0x0 MINIMUM Minimum Value
0xF MAXIMUM Maximum Value
RO 0x0
11:8 INSTNUM Instance number
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RO 0x0
7:4 MAJREV Major Revision
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RO 0x1
3:0 MINREV Minor Revision
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RO 0x0

TOP:NVMNW:CMDEXEC

Address Offset 0x0000 0100
Physical Address 0x5803 2100 Instance 0x5803 2100
Description Command Execute Register:
Initiates execution of the command specified in the CMDTYPE register.
This register is blocked for writes after being written to 1 and prior to
STATCMD.DONE being set by the NoWrapper hardware.
NoWrapper hardware clears this register after the processing of the command
has completed.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Command Execute value
Initiates execution of the command specified in the CMDTYPE register.
Value ENUM Name Description
0x0 NOEXECUTE Command will not execute or is not executing in NoWrapper
0x1 EXECUTE Command will execute or is executing in NoWrapper
RW 0

TOP:NVMNW:CMDTYPE

Address Offset 0x0000 0104
Physical Address 0x5803 2104 Instance 0x5803 2104
Description Command Type Register
This register specifies the type of command to be executed by the NoWrapper
hardware.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.
Type RW
Bits Field Name Description Type Reset
6:4 SIZE Command size
Value ENUM Name Description
0x0 ONEWORD Operate on 1 flash word
0x1 TWOWORD Operate on 2 flash words
0x2 FOURWORD Operate on 4 flash words
0x3 EIGHTWORD Operate on 8 flash words
0x4 SECTOR Operate on a flash sector
0x5 BANK Operate on an entire flash bank
RW 0b000
3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
2:0 COMMAND Command type
Value ENUM Name Description
0x0 NOOP No Operation
0x1 PROGRAM Program
0x2 ERASE Erase
0x3 READVERIFY Read Verify - Perform a standalone read verify operation.
0x4 MODECHANGE Mode Change - Perform a mode change only, no other operation.
0x5 CLEARSTATUS Clear Status - Clear status bits in FW_SMSTAT only.
0x6 BLANKVERIFY Blank Verify - Check whether a flash word is in the erased state.
This command may only be used with CMDTYPE.SIZE = ONEWORD
RW 0b000

TOP:NVMNW:CMDCTL

Address Offset 0x0000 0108
Physical Address 0x5803 2108 Instance 0x5803 2108
Description Command Control Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21 DATAVEREN Enable invalid data verify.
This checks for 0->1 transitions in the memory when
a program operation is initiated. If such a transition is found, the program will
fail with an error without doing any programming.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
20 SSERASEDIS Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used
for all erase pulses.
By default, this bit is reset, meaning that the VHV voltage will be stepped during
successive erase pulses. The step count, step voltage, begin and end voltages
are all hard-wired.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
19 ERASEMASKDIS Disable use of erase mask for erase
Bit masking will not be used during erase verify. If any sectors fail the
verify either before (prever) or after (postver) the operation, then all specified
flash sectors will receive subsequent erase pulse.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
18 PROGMASKDIS Disable use of program mask for programming.
Bit masking will not be used during program verify. If any bits fail the
verify either before (prever) or after (postver) the operation, then all specified
flash entries will receive subsequent program pulse.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
16 ADDRXLATEOVR Override hardware address translation of address in CMDADDR from a
system address to a bank address and bank ID. Use data written to
CMDADDR directly as the bank address. Use the value written to
CMDCTL.BANKSEL directly as the bank ID. Use the value written to
CMDCTL.REGIONSEL directly as the region ID.
Value ENUM Name Description
0x0 NOOVERRIDE Do not override
0x1 OVERRIDE Override
RW 0
15 POSTVEREN Enable verify after program or erase
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 1
14 PREVEREN Enable verify before program or erase. For program, bits already programmed
to the requested value will be masked. For erase, sectors already erased will be
masked.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 1
13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
12:9 REGIONSEL Bank Region
A specific region ID can be written to this field to indicate to which region an
operation should be applied if CMDCTL.ADDRXLATEOVR is set.
Value ENUM Name Description
0x1 MAIN Main Region
0x2 NONMAIN Non-Main Region
0x4 TRIM Trim Region
0x8 ENGR Engr Region
RW 0x0
4 BANKSEL Bank Select
A specific Bank ID can be written to this field to indicate to which bank an
operation should be applied if CMDCTL.ADDRXLATEOVR is set.
Value ENUM Name Description
0x1 BANK0 Bank 0
0x2 BANK1 Bank 1
0x4 BANK2 Bank 2
0x8 BANK3 Bank 3
0x10 BANK4 Bank 4
RW 0
3:0 MODESEL Mode
This field is only used for the Mode Change command type. Otherwise, bank
and pump modes are set automaticlly via the NW hardware.
Value ENUM Name Description
0x0 READ Read Mode
0x2 RDMARG0 Read Margin 0 Mode
0x4 RDMARG1 Read Margin 1 Mode
0x6 RDMARG0B Read Margin 0B Mode
0x7 RDMARG1B Read Margin 1B Mode
0x9 PGMVER Program Verify Mode
0xA PGMSW Program Single Word
0xB ERASEVER Erase Verify Mode
0xC ERASESECT Erase Sector
0xE PGMMW Program Multiple Word
0xF ERASEBNK Erase Bank
RW 0x0

TOP:NVMNW:CMDADDR

Address Offset 0x0000 0120
Physical Address 0x5803 2120 Instance 0x5803 2120
Description Command Address Register:
This register forms the target address of a command. The use cases are as
follows:
1)For single-word program, this address indicates the flash bank word to be
programmed.
2)For multi-word program, this address indicates the first flash bank address
for the program. The address will be incremented for further words.
3)For sector erase, this address indicates the sector to be erased.
4)For bank erase, the address indicates the bank to be erased.
5)For read verify, the address indications follow program/erase listed above.
Note the address written to this register will be submitted for translation to the
NoWrapper address translation interface, and the translated address
will be used to access the bank. However, if the
CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will
be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Address value
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0x0000 0000

TOP:NVMNW:CMDBYTEN

Address Offset 0x0000 0124
Physical Address 0x5803 2124 Instance 0x5803 2124
Description Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to
be programmed, a 1 must be written to the corresponding bit in this register.
Normally, all bits are written to 1, allowing program of full flash words.
However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit
or 64-bit portions of a flash word.
In addtion, the read verify command will ignore data bytes read from the flash
in its comparison if the corresponding CMDBYTEN bit is 0.
ECC data bytes are protected by the 1-2 MSB bits in this register, depending on
the presence of ECC and the flash word data width.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is written to all 0 after the completion of all NoWrapper commands.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 VAL Command Byte Enable value.
A 1-bit per flash word byte value is placed in this register.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF

TOP:NVMNW:CMDDATAINDEX

Address Offset 0x0000 012C
Physical Address 0x5803 212C Instance 0x5803 212C
Description Command Program Data Index Register:
When multiple data registers are available for multi-word program, this register
can be written with an index which points to one of the data registers. When
a write to CMDDATA* is done, the data will be written to the physical
data register indexed by the value in this register.
Up to 8 data registers can be present, so this register can be written with 0x0
to 0x7. If less than 8 data registers are present, successive MSB bits of this
register are ignored when indexing the CMDDATA* registers.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 VAL Data register index
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0x3 MAXIMUM Maximum value of VAL
RW 0b00

TOP:NVMNW:CMDDATA0

Address Offset 0x0000 0130
Physical Address 0x5803 2130 Instance 0x5803 2130
Description Command Data Register 0
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 0.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA1

Address Offset 0x0000 0134
Physical Address 0x5803 2134 Instance 0x5803 2134
Description Command Data Register 1
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 0.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to CMDSTAT.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA2

Address Offset 0x0000 0138
Physical Address 0x5803 2138 Instance 0x5803 2138
Description Command Data Register 2
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 0.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA3

Address Offset 0x0000 013C
Physical Address 0x5803 213C Instance 0x5803 213C
Description Command Data Register 3
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 0.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA4

Address Offset 0x0000 0140
Physical Address 0x5803 2140 Instance 0x5803 2140
Description Command Data Register 4
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 1.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
T
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA5

Address Offset 0x0000 0144
Physical Address 0x5803 2144 Instance 0x5803 2144
Description Command Data Register 5

This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 1.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA6

Address Offset 0x0000 0148
Physical Address 0x5803 2148 Instance 0x5803 2148
Description Command Data Register 6
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 1.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA7

Address Offset 0x0000 014C
Physical Address 0x5803 214C Instance 0x5803 214C
Description Command Data Register 7
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 1.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA8

Address Offset 0x0000 0150
Physical Address 0x5803 2150 Instance 0x5803 2150
Description Command Data Register 8
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 2.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA9

Address Offset 0x0000 0154
Physical Address 0x5803 2154 Instance 0x5803 2154
Description Command Data Register 9

This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 2.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA10

Address Offset 0x0000 0158
Physical Address 0x5803 2158 Instance 0x5803 2158
Description Command Data Register 10
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 2.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA11

Address Offset 0x0000 015C
Physical Address 0x5803 215C Instance 0x5803 215C
Description Command Data Register 11
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 2.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA12

Address Offset 0x0000 0160
Physical Address 0x5803 2160 Instance 0x5803 2160
Description Command Data Register 12
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 3.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA13

Address Offset 0x0000 0164
Physical Address 0x5803 2164 Instance 0x5803 2164
Description Command Data Register 13

This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 3.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA14

Address Offset 0x0000 0168
Physical Address 0x5803 2168 Instance 0x5803 2168
Description Command Data Register 14
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 3.
For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDDATA15

Address Offset 0x0000 016C
Physical Address 0x5803 216C Instance 0x5803 216C
Description Command Data Register 15
This register forms the data for a command.
For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 3.
For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all NoWrapper commands.

Use cases for the CMDDATA* registers are as follows:
1)Program - These registers contain the data to be programmed.
2)Erase - These registers are not used.
3)Read Verify - These registers contain data to be verified.
Type RW
Bits Field Name Description Type Reset
31:0 VAL A 32-bit data value is placed in this field.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDWEPROTA

Address Offset 0x0000 01D0
Physical Address 0x5803 21D0 Instance 0x5803 21D0
Description Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from
program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32
sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all NoWrapper commands.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Each bit protects 1 sector.

bit [0]:When 1, sector 0 of the flash memory will be protected from program
and erase.
bit [1]:When 1, sector 1 of the flash memory will be protected from program
and erase.
:
:
bit [31]:When 1, sector 31 of the flash memory will be protected from program
and erase.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDWEPROTB

Address Offset 0x0000 01D4
Physical Address 0x5803 21D4 Instance 0x5803 21D4
Description Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and
erase. Each bit corresponds to a group of 8 sectors.
There are 3 cases for how these protect bits are applied:
1. Single-bank system:
In the case where only a single flash bank is present,
the first 32 sectors are protected via the CMDWEPROTA register. Thus, the
protection give by the bits in CMDWEPROTB begin with sector 32.
2. Multi-bank system, Bank 0:
When multiple flash banks are present, the first
32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only
bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of
bit 4 and above would begin at sector 32. Bits 3:0
of WEPROTB are ignored for bank 0.
3. Multi-bank system, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has
no effect, so the bits in CMDWEPROTB will protect these banks starting
from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all NoWrapper commands.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors
in the flash will be protected from program and erase. A maximum of 256
sectors can be protected with this register.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0xFFFFFFFF MAXIMUM Maximum value of VAL
RW 0xFFFF FFFF

TOP:NVMNW:CMDWEPROTNM

Address Offset 0x0000 0210
Physical Address 0x5803 2210 Instance 0x5803 2210
Description Command WriteErase Protect Non-Main
Register
This register allows non-main region region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all NoWrapper commands.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Each bit protects 1 sector.

bit [0]:When 1, sector 0 of the non-main region will be protected from program
and erase.
bit [1]:When 1, sector 1 of the non-main region will be protected from program
and erase.
:
:
bit [31]:When 1, sector 31 of the non-main will be protected from program
and erase.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0x1 MAXIMUM Maximum value of VAL
RW 1

TOP:NVMNW:CMDWEPROTTR

Address Offset 0x0000 0214
Physical Address 0x5803 2214 Instance 0x5803 2214
Description Command WriteErase Protect Trim
Register
This register allows trim region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all NoWrapper commands.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Each bit protects 1 sector.

bit [0]:When 1, sector 0 of the engr region will be protected from program
and erase.
bit [1]:When 1, sector 1 of the engr region will be protected from program
and erase.
:
:
bit [31]:When 1, sector 31 of the engr region will be protected from program
and erase.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0x1 MAXIMUM Maximum value of VAL
RW 1

TOP:NVMNW:CMDWEPROTEN

Address Offset 0x0000 0218
Physical Address 0x5803 2218 Instance 0x5803 2218
Description Command WriteErase Protect Engr
Register
This register allows engr region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all NoWrapper commands.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Each bit protects 1 sector.

bit [0]:When 1, sector 0 of the engr region will be protected from program
and erase.
bit [1]:When 1, sector 1 of the engr region will be protected from program
and erase.
:
:
bit [31]:When 1, sector 31 of the engr region will be protected from program
and erase.
Value ENUM Name Description
0x0 MINIMUM Minimum value of VAL
0x1 MAXIMUM Maximum value of VAL
RW 1

TOP:NVMNW:CFGCMD

Address Offset 0x0000 03B0
Physical Address 0x5803 23B0 Instance 0x5803 23B0
Description Command Configuration Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.
Type RW
Bits Field Name Description Type Reset
32:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
3:0 WAITSTATE Wait State setting for program verify, erase verify and read verify
Value ENUM Name Description
0x0 MINIMUM Minimum value
0xF MAXIMUM Maximum value
RW 0x2

TOP:NVMNW:CFGPCNT

Address Offset 0x0000 03B4
Physical Address 0x5803 23B4 Instance 0x5803 23B4
Description Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for
program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
32:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
11:4 MAXPCNTVAL Override maximum pulse counter with this value.
If MAXPCNTOVR = 0, then this field is ignored.
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used
to override the max pulse count for both program and erase. Full max value
will be {4'h0, MAXPCNTVAL} .
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used
to override the max pulse count for program only. Full max value will be
{4'h0, MAXPCNTVAL}.
Value ENUM Name Description
0x0 MINIMUM Minimum value
0xFF MAXIMUM Maximum value
RW 0x00
3:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
0 MAXPCNTOVR Override hard-wired maximum pulse count. If MAXERSPCNTOVR
is not set, then setting this value alone will override the max pulse count for
both program and erase. If MAXERSPCNTOVR is set, then this bit will only
control the max pulse count setting for program.
By default, this bit is 0, and a hard-wired max pulse count is used.
Value ENUM Name Description
0x0 DEFAULT Use hard-wired (default) value for maximum pulse count
0x1 OVERRIDE Use value from MAXPCNTVAL field as maximum puse count
RW 0

TOP:NVMNW:STATCMD

Address Offset 0x0000 03D0
Physical Address 0x5803 23D0 Instance 0x5803 23D0
Description Command Status Register
This register contains status regarding completion and errors of command
execution.
Type RO
Bits Field Name Description Type Reset
31:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000
12 FAILMISC Command failed due to error other than write/erase protect violation or verify
error. This is an extra bit in case a new failure mechanism is added which
requires a status bit.
Value ENUM Name Description
0x0 STATNOFAIL No Fail
0x1 STATFAIL Fail
RO 0
8 FAILINVDATA Program command failed because an attempt was made to program a stored
0 value to a 1.
Value ENUM Name Description
0x0 STATNOFAIL No Fail
0x1 STATFAIL Fail
RO 0
7 FAILMODE Command failed because a bank has been set to a mode other than READ.
Program and Erase commands cannot be initiated unless all banks are in READ
mode.
Value ENUM Name Description
0x0 STATNOFAIL No Fail
0x1 STATFAIL Fail
RO 0
6 FAILILLADDR Command failed due to the use of an illegal address
Value ENUM Name Description
0x0 STATNOFAIL No Fail
0x1 STATFAIL Fail
RO 0
5 FAILVERIFY Command failed due to verify error
Value ENUM Name Description
0x0 STATNOFAIL No Fail
0x1 STATFAIL Fail
RO 0
4 FAILWEPROT Command failed due to Write/Erase Protect Sector Violation
Value ENUM Name Description
0x0 STATNOFAIL No Fail
0x1 STATFAIL Fail
RO 0
3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
2 CMDINPROGRESS Command In Progress
Value ENUM Name Description
0x0 STATCOMPLETE Complete
0x1 STATINPROGRESS In Progress
RO 0
1 CMDPASS Command Pass - valid when CMD_DONE field is 1
Value ENUM Name Description
0x0 STATFAIL Fail
0x1 STATPASS Pass
RO 0
0 CMDDONE Command Done
Value ENUM Name Description
0x0 STATNOTDONE Not Done
0x1 STATDONE Done
RO 0

TOP:NVMNW:STATADDR

Address Offset 0x0000 03D4
Physical Address 0x5803 23D4 Instance 0x5803 23D4
Description Current Address Counter Value
Read only register giving read access to the state machine current address.
A bank id, region id and address are stored in this register and are incremented as
necessary during execution of a command.
Type RO
Bits Field Name Description Type Reset
31:26 RESERVED26 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
25:21 BANKID Current Bank ID
A bank indicator is stored in this register which represents the current bank on
which the state machine is operating. There is 1 bit per bank.
Value ENUM Name Description
0x1 BANK0 Bank 0
0x2 BANK1 Bank 1
0x4 BANK2 Bank 2
0x8 BANK3 Bank 3
0x10 BANK4 Bank 4
RO 0b0 0001
20:16 REGIONID Current Region ID
A region indicator is stored in this register which represents the current flash
region on which the state machine is operating.
Value ENUM Name Description
0x1 MAIN Main Region
0x2 NONMAIN Non-Main Region
0x4 TRIM Trim Region
0x8 ENGR Engr Region
RO 0b0 0000
15:0 BANKADDR Current Bank Address
A bank offset address is stored in this register.
Value ENUM Name Description
0x0 MINIMUM Minimum value
0xFFFF MAXIMUM Maximum value
RO 0x0000

TOP:NVMNW:STATPCNT

Address Offset 0x0000 03D8
Physical Address 0x5803 23D8 Instance 0x5803 23D8
Description Current Pulse Count Register:
Read only register giving read access to the state machine current pulse count
value for program/erase operations.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:0 PULSECNT Current Pulse Counter Value
Value ENUM Name Description
0x0 MINIMUM Minimum value
0xFFF MAXIMUM Maximum value
RO 0x000

TOP:NVMNW:STATMODE

Address Offset 0x0000 03DC
Physical Address 0x5803 23DC Instance 0x5803 23DC
Description Mode Status Register
Indicates any banks which not in READ mode, and it indicates the mode
which the bank(s) are in.
Type RO
Bits Field Name Description Type Reset
17 BANK1TRDY Bank 1T Ready.
Bank(s) are ready for 1T access. This is accomplished when the bank and pump
have been trimmed.
Value ENUM Name Description
0x0 FALSE Not ready
0x1 TRUE Ready
RO 0
16 BANK2TRDY Bank 2T Ready.
Bank(s) are ready for 2T access. This is accomplished when the pump has
fully driven power rails to the bank(s).
Value ENUM Name Description
0x0 FALSE Not ready
0x1 TRUE Ready
RO 0
11:8 BANKMODE Indicates mode of bank(s) that are not in READ mode
Value ENUM Name Description
0x0 READ Read Mode
0x2 RDMARG0 Read Margin 0 Mode
0x4 RDMARG1 Read Margin 1 Mode
0x6 RDMARG0B Read Margin 0B Mode
0x7 RDMARG1B Read Margin 1B Mode
0x9 PGMVER Program Verify Mode
0xA PGMSW Program Single Word
0xB ERASEVER Erase Verify Mode
0xC ERASESECT Erase Sector
0xE PGMMW Program Multiple Word
0xF ERASEBNK Erase Bank
RO 0x0
7:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 BANKNOTINRD Bank not in read mode.
Indicates which banks are not in READ mode. There is 1 bit per bank.
Value ENUM Name Description
0x1 BANK0 Bank 0
0x2 BANK1 Bank 1
0x4 BANK2 Bank 2
0x8 BANK3 Bank 3
0x10 BANK4 Bank 4
RO 0

TOP:NVMNW:GBLINFO0

Address Offset 0x0000 03F0
Physical Address 0x5803 23F0 Instance 0x5803 23F0
Description Global Info 0 Register
Read only register detailing information about sector size and number of banks
present.
Type RO
Bits Field Name Description Type Reset
18:16 NUMBANKS Number of banks instantiated
Minimum:1
Maximum:5
Value ENUM Name Description
0x1 MINIMUM Minimum value
0x5 MAXIMUM Maximum value
RO 0b010
15:0 SECTORSIZE Sector size in bytes
Value ENUM Name Description
0x400 ONEKB Sector size is ONEKB
0x800 TWOKB Sector size is TWOKB
RO 0x0800

TOP:NVMNW:GBLINFO1

Address Offset 0x0000 03F4
Physical Address 0x5803 23F4 Instance 0x5803 23F4
Description Global Info 1 Register
Read only register detailing information about data, ecc and redundant data
widths in bits.
Type RO
Bits Field Name Description Type Reset
31:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
18:16 REDWIDTH Redundant data width in bits
Value ENUM Name Description
0x0 W0BIT Redundant data width is 0. Redundancy/Repair not present.
0x2 W2BIT Redundant data width is 2 bits
0x4 W4BIT Redundant data width is 4 bits
RO 0b100
12:8 ECCWIDTH ECC data width in bits
Value ENUM Name Description
0x0 W0BIT ECC data width is 0. ECC not used.
0x8 W8BIT ECC data width is 8 bits
0x10 W16BIT ECC data width is 16 bits
RO 0b0 0000
7:0 DATAWIDTH Data width in bits
Value ENUM Name Description
0x40 W64BIT Data width is 64 bits
0x80 W128BIT Data width is 128 bits
RO 0x80

TOP:NVMNW:GBLINFO2

Address Offset 0x0000 03F8
Physical Address 0x5803 23F8 Instance 0x5803 23F8
Description Global Info 2 Register
Read only register detailing information about the number of data registers
present.
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 DATAREGISTERS Number of data registers present.
Value ENUM Name Description
0x1 MINIMUM Minimum value of DATAREGISTERS
0x8 MAXIMUM Maximum value of DATAREGISTERS
RO 0x4

TOP:NVMNW:BANK0INFO0

Address Offset 0x0000 0400
Physical Address 0x5803 2400 Instance 0x5803 2400
Description Bank Info 0 Register for bank 0.
Read only register detailing information about Main region size in the bank.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:0 MAINSIZE Main region size in sectors
Minimum:0x8 (8)
Maximum:0x200 (512)
Value ENUM Name Description
0x8 MINSECTORS Minimum value of MAINSIZE
0x200 MAXSECTORS Maximum value of MAINSIZE
RO 0x100

TOP:NVMNW:BANK0INFO1

Address Offset 0x0000 0404
Physical Address 0x5803 2404 Instance 0x5803 2404
Description Bank Info1 Register for bank 0.
Read only register detailing information about Non-Main, Trim, and Engr
region sizes in the bank.
Type RO
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 ENGRSIZE Engr region size in sectors
Minimum:0x0 (0)
Maximum:0x10 (16)
Value ENUM Name Description
0x0 MINSECTORS Minimum value of ENGRSIZE
0x20 MAXSECTORS Maximum value of ENGRSIZE
RO 0x01
15:8 TRIMSIZE Trim region size in sectors
Minimum:0x0 (0)
Maximum:0x10 (16)
Value ENUM Name Description
0x0 MINSECTORS Minimum value of TRIMSIZE
0x20 MAXSECTORS Maximum value of TRIMSIZE
RO 0x01
7:0 NONMAINSIZE Non-main region size in sectors
Minimum:0x0 (0)
Maximum:0x10 (16)
Value ENUM Name Description
0x0 MINSECTORS Minimum value of NONMAINSIZE
0x20 MAXSECTORS Maximum value of NONMAINSIZE
RO 0x01

TOP:NVMNW:BANK1INFO0

Address Offset 0x0000 0410
Physical Address 0x5803 2410 Instance 0x5803 2410
Description Bank Info 0 Register for bank 1.
Read only register detailing information about Main region size in the bank.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:0 MAINSIZE Main region size in sectors
Minimum:0x8 (8)
Maximum:0x200 (512)
Value ENUM Name Description
0x8 MINSECTORS Minimum value of MAINSIZE
0x200 MAXSECTORS Maximum value of MAINSIZE
RO 0x100

TOP:NVMNW:BANK1INFO1

Address Offset 0x0000 0414
Physical Address 0x5803 2414 Instance 0x5803 2414
Description Bank Info1 Register for bank 1.
Read only register detailing information about Non-Main, Trim, and Engr
region sizes in the bank.
Type RO
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:16 ENGRSIZE Engr region size in sectors
Minimum:0x0 (0)
Maximum:0x10 (16)
Value ENUM Name Description
0x0 MINSECTORS Minimum value of ENGRSIZE
0x20 MAXSECTORS Maximum value of ENGRSIZE
RO 0x01
15:8 TRIMSIZE Trim region size in sectors
Value ENUM Name Description
0x0 MINSECTORS Minimum value of TRIMSIZE
0x20 MAXSECTORS Maximum value of TRIMSIZE
RO 0x01
7:0 NONMAINSIZE Non-main region size in sectors
Value ENUM Name Description
0x0 MINSECTORS Minimum value of NONMAINSIZE
0x20 MAXSECTORS Maximum value of NONMAINSIZE
RO 0x01

TOP:NVMNW:DFTEN

Address Offset 0x0000 0500
Physical Address 0x5803 2500 Instance 0x5803 2500
Description DFT Enable Register
Allows control of NoWrapper test features. When set, DFT* registers in this
aperture open for write access. When cleared, DFT* registers are read-only.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ENABLE Enable Test Features
Value ENUM Name Description
0x0 DISABLED Command
0x1 ENABLED Command
RW 0

TOP:NVMNW:DFTCMDCTL

Address Offset 0x0000 0504
Physical Address 0x5803 2504 Instance 0x5803 2504
Description DFT Command Control Register
This register configures specific capabilities for test.
This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:28 DTBMUXSEL DTB Mux Select
This field will form the select for the primary DTB mux. This mux selects up to
16 sets of 32-bit fields of internal signals to be present to the 32-bit DTB output.
Value ENUM Name Description
0x0 MINIMUM Minimum value
0xF MAXIMUM Maximum value
RW 0x0
27:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
20 STOPVERONFAIL Stop read verify on fail. If this bit is set, read verify will halt when the first verify
fail is detected. If command is program or erase, another program or erase
pulse will be executed. If command is read verify, comand will terminate.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
18 ODDROWINVDATA Invert data at odd row addresses for program or verify. The LSB of the row
address is bit [4] of the bank address. This bit only applies when pattern data
is used; i.e. the DATAPATEN bit is set. It will have no effect if CMDDATA is used.
Value ENUM Name Description
0x0 TRUE Use true data
0x1 INVERT Use inverted data
RW 0
17 ODDWORDINVDATA Invert data at odd bank addresses for program or verify. This bit only applies
when pattern data is used; i.e. the DATAPATEN bit is set. It will have no effect
if CMDDATA is used.
Value ENUM Name Description
0x0 TRUE Use true data
0x1 INVERT Use inverted data
RW 0
16 ALWAYSINVDATA Invert data always for program or verify. This bit only applies when pattern data
is used; i.e. the DATAPATEN bit is set. It will have no effect if CMDDATA is used.
Value ENUM Name Description
0x0 TRUE Use true data
0x1 INVERT Use inverted data
RW 0
15:13 DATAPATSEL Select data pattern. Valid when DATAPATEN bit is set to 1. Overrides CMDDATA
registers for program or verify.
Value ENUM Name Description
0x0 ALL0 Set to all 0
0x1 ALL1 Set to all 1
0x2 LOGCHKBRD Set to logical checkerboard (0x01010101...)
RW 0b000
12 DATAPATEN Enable data pattern. Data pattern select in DATAPATSEL field will override data
from CMDDATA registers for use as program or verify data.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9 PULSECNTLDDIS Override pulse counter enable.
When set, the state machine pulse counter will not be loaded when a
command is initiated.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
8 ADDRCNTLDDIS Override address counter enable.
When set, the state machine address counter will not be loaded when a
command is initiated.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
7:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
5 REDMATCHFORCE Force redundancy match. If set to 1, repair configuration encoded in the flash
bank trim will be forced for every access.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
4 REDMATCHDIS Disable redundancy matching. Any repair configuration encoded into the
bank trim bits is disabled.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
2 AMX2TDIS 2T address mux disable control. When set to 1 2T address shifting is
disabled. This bit should only be enabled for reads. Indeterminate behavior
will result if this bit is set during program/erase. Furthermore, only reads done
via a READVERIFY command will be guaranteed to work properly. Reads via
the FBAP port are not guaranteed to operate.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
1 FORCE2TEN Force 2T Enable - Force 2T access to regions that are designated as 1T. Regions
designated as 2T will still be accessed as 2T.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
0 FORCE1TEN Force 1T Enable - Force 1T access to regions that are designated as 2T. Regions
designated as 1T will still be accessed as 1T.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0

TOP:NVMNW:DFTTIMERCTL

Address Offset 0x0000 0508
Physical Address 0x5803 2508 Instance 0x5803 2508
Description DFT Timer Control Register
This allows some configuration of timing values for various phases of flash
operations for test. These time values are hard-coded for functional execution.
This register is only writable when DFT.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30:28 TIMERCLOCKOVR Override Timer clock frequency using an ICG-based clock divide mechanism.
To divide the timer clock, pulses can be skipped based on settings in this field.
By default, this field is 0, which corresponds to no division on the timer clock.
Value ENUM Name Description
0x0 NODIVIDE No divide on timer clock.
0x1 DIVIDEBY2 Divide timer clock by 2
0x2 DIVIDEBY3 Divide timer clock by 3
0x3 DIVIDEBY4 Divide timer clock by 4
0x4 DIVIDEBY5 Divide timer clock by 5
0x5 DIVIDEBY6 Divide timer clock by 6
0x6 DIVIDEBY7 Divide timer clock by 7
0x7 DIVIDEBY8 Divide timer clock by 8
RW 0b000
27:12 PEPULSETIMEVAL Program/Erase Pulse Time Value
If operation is a program, this value gets loaded into bits [15:0] of the timer
when the PEPULSETIMEVALOVR field is set to 1.
If operation is an erase, this value gets loaded into bits [19:4] of the timer
when the PEPULSETIMEVALOVR field is set to 1.
Value ENUM Name Description
0x1 MINIMUM Minimum value
0xFFFF MAXIMUM Maximum value
RW 0x0000
11:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
8 PEPULSETIMEOVR Override Program/Erase Pulse Time
If set, this will force the program or erase pulse time to be overridden with the
value in the PEPULSETIMEVAL field. If not set, then a hard-coded value will be
used for this pulse time.
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 OVERRIDE Use value from the PE_PULSE_TIME field for time value
RW 0
7 READMODETIME Read Mode Change Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
6 PEVHOLDTIME Program/Erase Verify Hold Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
5 PEVSETUPTIME Program/Erase Verify Setup Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
4 PEVMODETIME Program/Erase Verify Mode Change Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
3 PEHOLDTIME Program/Erase Hold Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
2 PPVWORDLINETIME Program and Program Verify Wordline Switching Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
1 PVHVSETUPTIME Program VHV Setup Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0
0 PESETUPTIME Program/Erase Setup Time
Value ENUM Name Description
0x0 FUNCTIONAL Use hard-wired (Functional) timer value
0x1 TWOXFUNCTIONAL Use 2x the hard-wired (functional) time value
RW 0

TOP:NVMNW:DFTEXECZCTL

Address Offset 0x0000 050C
Physical Address 0x5803 250C Instance 0x5803 250C
Description DFT EXECUTEZ control register. This register allows direct control of the
EXECUTEZ to bank and pump for test.
This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 EXEZ_OVR Override value to be applied to EXECUTEZ
Value ENUM Name Description
0x0 ZERO Set EXECUTEZ to 0
0x1 ONE Set EXECUTEZ to 1
RW 1
0 EXEZOVREN Enable override of EXECUTEZ
Note that when this bit is set, NoWrapper has control of the bank pins.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0

TOP:NVMNW:DFTPCLKTESTCTL

Address Offset 0x0000 0510
Physical Address 0x5803 2510 Instance 0x5803 2510
Description DFT Pump Clock Test Control Register. This register controls hardware features
that allow the pump clock to be characterized for trim development.
This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 ENABLE Enable the state machine which sequences measurement of pump clock
frequency.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0

TOP:NVMNW:DFTPCLKTESTSTAT

Address Offset 0x0000 0514
Physical Address 0x5803 2514 Instance 0x5803 2514
Description DFT Pump Clock Test Status Register. This register shows status reported by the
hardware features that allow the pump clock to be characterized for trim
development.
This register is only writable when DFTEN.ENABLE is set.
Type RO
Bits Field Name Description Type Reset
15:4 CLOCKCNT Indicates the core clock count captured during the pump clock measurement.
Value ENUM Name Description
0x0 MINIMUM Minimum count value
0xFFF MAXIMUM Maximum count value
RO 0x000
3:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
0 BUSY Indicates that a pump clock measurement is in progress.
Value ENUM Name Description
0x0 COMPLETE Indicates test complete
0x1 INPROGRESS Indicates test in progress
RO 0

TOP:NVMNW:DFTDATARED0

Address Offset 0x0000 0540
Physical Address 0x5803 2540 Instance 0x5803 2540
Description DFT Redundancy Data Register 0
This register is used when testing the redundant columns in the flash. It acts
as an extension of the CMDDATA* registers. The bits in this register correspond
to flash data word register 0.
In addition, this register is used to aggregate masking for bits that do not
require additional program pulses during program operations. The original
data written to this register will be lost during program command execution.

Use cases for this register are as follows:
1)Program - Contains the data to be programmed.
2)Erase - Not used.
3)Read Verify - Contains data to be verified.

This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Data for redundant bits RW 0xF

TOP:NVMNW:DFTDATARED1

Address Offset 0x0000 0544
Physical Address 0x5803 2544 Instance 0x5803 2544
Description DFT Redundancy Data Register 1
This register is used when testing the redundant columns in the flash. It acts
as an extension of the CMDDATA* registers. The bits in this register correspond
to flash data word register 1.
In addition, this register is used to aggregate masking for bits that do not
require additional program pulses during program operations. The original
data written to this register will be lost during program command execution.

Use cases for this register are as follows:
1)Program - Contains the data to be programmed.
2)Erase - Not used.
3)Read Verify - Contains data to be verified.

This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Data for redundant bits RW 0xF

TOP:NVMNW:DFTDATARED2

Address Offset 0x0000 0548
Physical Address 0x5803 2548 Instance 0x5803 2548
Description DFT Redundancy Data Register 2
This register is used when testing the redundant columns in the flash. It acts
as an extension of the CMDDATA* registers. The bits in this register correspond
to flash data word register 2.
In addition, this register is used to aggregate masking for bits that do not
require additional program pulses during program operations. The original
data written to this register will be lost during program command execution.

Use cases for this register are as follows:
1)Program - Contains the data to be programmed.
2)Erase - Not used.
3)Read Verify - Contains data to be verified.

This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Data for redundant bits RW 0xF

TOP:NVMNW:DFTDATARED3

Address Offset 0x0000 054C
Physical Address 0x5803 254C Instance 0x5803 254C
Description DFT Redundancy Data Register 3
This register is used when testing the redundant columns in the flash. It acts
as an extension of the CMDDATA* registers. The bits in this register correspond
to flash data word register 3.
In addition, this register is used to aggregate masking for bits that do not
require additional program pulses during program operations. The original
data written to this register will be lost during program command execution.

Use cases for this register are as follows:
1)Program - Contains the data to be programmed.
2)Erase - Not used.
3)Read Verify - Contains data to be verified.

This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 VAL Data for redundant bits RW 0xF

TOP:NVMNW:DFTPUMPCTL

Address Offset 0x0000 0560
Physical Address 0x5803 2560 Instance 0x5803 2560
Description DFT Pump Control Register
This allows some configuration of pump parameters during test.
This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
31:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
18:16 IREFEVCTL IREFEV control IREFVRD, REFTC, IREFCONST, IREFCCOR blocks in IREFEV RW 0b000
15:12 CONFIGPMP Pump configuration control. LP, HP operation RW 0x1
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9 SSEN Dither control for oscillator
Enumeration:
0: Disable Dither
1: Enable Dither
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
8 PUMPCLKEN Allows direct control of the pump oscillator which is used to generate pumpclk.
Normally, enable/disable of pumpclk is under NoWrapper state machine
control. This bit allows system to enable the clock independently.
Value ENUM Name Description
0x0 HWCTL Allow pump clock oscillator to be controlled by hardware.
0x1 ENABLE Force pump clock oscillator to be enabled.
RW 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:0 TCR TCR test mode to be applied to the pump
Value ENUM Name Description
0x0 MINIMUM Minimum value
0x7F MAXIMUM Maximum value
RW 0b000 0000

TOP:NVMNW:DFTBANKCTL

Address Offset 0x0000 0564
Physical Address 0x5803 2564 Instance 0x5803 2564
Description DFT Bank Control Register
This allows some configuration of bank parameters during test.
This register is only writable when DFTEN.ENABLE is set.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the NoWrapper
hardware.
Type RW
Bits Field Name Description Type Reset
8 TEZ When set, TEZ is asserted to the flash banks. Which banks get the asserted
signal is determined by the BANKSELECT field in CMDCTL.
0x0 Do no assert TEZ
0x1 Assert TEZ
Value ENUM Name Description
0x0 ASSERT Assert TEZ
0x1 NEGATE Do not assert TEZ
RW 1
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:0 TCR TCR test mode to be applied to the bank
Value ENUM Name Description
0x0 MINIMUM Minimum value
0x7F MAXIMUM Maximum value
RW 0b000 0000


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