soc.h File Reference

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Macros
SOC Domain ID
#define	SOC_DOMAIN_ID_TOPSS_CTRL   (0U)
#define	SOC_DOMAIN_ID_APP_RCM   (1U)
#define	SOC_DOMAIN_ID_APP_CTRL   (2U)
#define	SOC_DOMAIN_ID_TOP_IO_MUX   (3U)
#define	SOC_DOMAIN_ID_TOP_PRCM   (4U)

Enumerations
enum	SOC_SysRstReason { SOC_SYS_RESET_REASON_PORZ = 0x01U, SOC_SYS_RESET_REASON_SR = 0x02U, SOC_SYS_RESET_REASON_WDG = 0x04U }
	SOC System Reset Reason. More...
enum	SOC_RstReason {   SOC_RESET_REASON_PORZ = 0x01U, SOC_RESET_REASON_WARM, SOC_RESET_REASON_DEEPSLEEP, SOC_RESET_REASON_SOFT,   SOC_RESET_REASON_STC_WARM, SOC_RESET_REASON_STC_PORZ }
	SOC Reset Reason. More...

Functions
int32_t	SOC_moduleClockEnable (uint32_t moduleId, uint32_t enable)
	Enable clock to specified module. More...
int32_t	SOC_clocksEnable (void)
	Enables ADPLL. More...
int32_t	SOC_moduleSetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
	Set module clock to specified frequency. More...
const char *	SOC_getCoreName (uint16_t coreId)
	Convert a core ID to a user readable name. More...
void	SOC_controlModuleLockMMR (uint32_t domainId, uint32_t partition)
	Lock control module partition to prevent writes into control MMRs. More...
void	SOC_controlModuleUnlockMMR (uint32_t domainId, uint32_t partition)
	Unlock control module partition to allow writes into control MMRs. More...
void	SOC_logAllClockHz (void)
	Print's module clock info to the console. More...
uint64_t	SOC_virtToPhy (void *virtAddr)
	SOC Virtual (CPU) to Physical address translation function. More...
void	SOC_memoryInit (uint16_t flag)
	Initializes APPSS shared RAM0, RAM1 and HWASS Shared RAM. More...
void	SOC_enableMDLLClock (void)
	Enables MDLL Clock. More...
void	SOC_triggerWarmReset (void)
	Software Warm reset request. Generates warm reset for entire device. More...
void	SOC_triggerSoftReset (void)
	Soft reset request. More...
SOC_RstReason	SOC_getRstReason (void)
	Retrieves the reset reason. More...
SOC_SysRstReason	SOC_getSysRstReason (void)
	Retrieves the system reset reason from SYS_RST_CAUSE. All the reset registers will be cleared by the bootloader. The reset register values will be stored in BOOT_INFO_REG0[23:0] The TOP_PRCM:SYS_RST_CAUSE[2:0] is stored in APP_CTRL:APPSS_BOOT_INFO_REG0[7:4]. More...
void	SOC_setEpwmTbClk (uint32_t enable)
	Enable or disable ePWM time base clock from Control MMR. More...