Introduction

For more details and example usage, see SOC

Sub Modules
	APIs for SOC Reset and Clock Functions

Functions
int32_t	SOC_moduleClockEnable (uint32_t moduleId, uint32_t enable)
	Enable clock to specified module. More...

int32_t	SOC_clocksEnable (void)
	Enables ADPLL. More...

int32_t	SOC_moduleSetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
	Set module clock to specified frequency. More...

const char *	SOC_getCoreName (uint16_t coreId)
	Convert a core ID to a user readable name. More...

void	SOC_controlModuleLockMMR (uint32_t domainId, uint32_t partition)
	Lock control module partition to prevent writes into control MMRs. More...

void	SOC_controlModuleUnlockMMR (uint32_t domainId, uint32_t partition)
	Unlock control module partition to allow writes into control MMRs. More...

void	SOC_logAllClockHz (void)
	Print's module clock info to the console. More...

uint64_t	SOC_virtToPhy (void *virtAddr)
	SOC Virtual (CPU) to Physical address translation function. More...

void	SOC_memoryInit (uint16_t flag)
	Initializes APPSS shared RAM0, RAM1 and HWASS Shared RAM. More...

void	SOC_enableMDLLClock (void)
	Enables MDLL Clock. More...

void	SOC_triggerWarmReset (void)
	Software Warm reset request. Generates warm reset for entire device. More...

void	SOC_triggerSoftReset (void)
	Soft reset request. More...

SOC_RstReason	SOC_getRstReason (void)
	Retrieves the reset reason. More...

SOC_SysRstReason	SOC_getSysRstReason (void)
	Retrieves the system reset reason from SYS_RST_CAUSE. All the reset registers will be cleared by the bootloader. The reset register values will be stored in BOOT_INFO_REG0[23:0] The TOP_PRCM:SYS_RST_CAUSE[2:0] is stored in APP_CTRL:APPSS_BOOT_INFO_REG0[7:4]. More...

void	SOC_setEpwmTbClk (uint32_t enable)
	Enable or disable ePWM time base clock from Control MMR. More...

Enumerations
enum	SOC_SysRstReason { SOC_SYS_RESET_REASON_PORZ = 0x01U, SOC_SYS_RESET_REASON_SR = 0x02U, SOC_SYS_RESET_REASON_WDG = 0x04U }
	SOC System Reset Reason. More...

enum	SOC_RstReason { SOC_RESET_REASON_PORZ = 0x01U, SOC_RESET_REASON_WARM, SOC_RESET_REASON_DEEPSLEEP, SOC_RESET_REASON_SOFT, SOC_RESET_REASON_STC_WARM, SOC_RESET_REASON_STC_PORZ }
	SOC Reset Reason. More...

SOC Domain ID

#define	SOC_DOMAIN_ID_TOPSS_CTRL (0U)

#define	SOC_DOMAIN_ID_APP_RCM (1U)

#define	SOC_DOMAIN_ID_APP_CTRL (2U)

#define	SOC_DOMAIN_ID_TOP_IO_MUX (3U)

#define	SOC_DOMAIN_ID_TOP_PRCM (4U)

Macro Definition Documentation

◆ SOC_DOMAIN_ID_TOPSS_CTRL

#define SOC_DOMAIN_ID_TOPSS_CTRL (0U)

◆ SOC_DOMAIN_ID_APP_RCM

#define SOC_DOMAIN_ID_APP_RCM (1U)

◆ SOC_DOMAIN_ID_APP_CTRL

#define SOC_DOMAIN_ID_APP_CTRL (2U)

◆ SOC_DOMAIN_ID_TOP_IO_MUX

#define SOC_DOMAIN_ID_TOP_IO_MUX (3U)

◆ SOC_DOMAIN_ID_TOP_PRCM

#define SOC_DOMAIN_ID_TOP_PRCM (4U)

Enumeration Type Documentation

◆ SOC_SysRstReason

enum SOC_SysRstReason

SOC System Reset Reason.

Enumerator
SOC_SYS_RESET_REASON_PORZ	Value specifying Power ON Reset.
SOC_SYS_RESET_REASON_SR	Value specifying Warm reset due to soft register.
SOC_SYS_RESET_REASON_WDG	Value specifying Warm reset due to WDG.

◆ SOC_RstReason

enum SOC_RstReason

SOC Reset Reason.

Enumerator
SOC_RESET_REASON_PORZ	Value specifying Power ON Reset.
SOC_RESET_REASON_WARM	Value specifying Warm Reset.
SOC_RESET_REASON_DEEPSLEEP	Value specifying Deep Sleep Reset.
SOC_RESET_REASON_SOFT	Value specifying Soft Reset.
SOC_RESET_REASON_STC_WARM	Value specifying STC or Warm Reset.
SOC_RESET_REASON_STC_PORZ	Value specifying STC or Power ON Reset.

Function Documentation

◆ SOC_moduleClockEnable()

int32_t SOC_moduleClockEnable	(	uint32_t	moduleId,
		uint32_t	enable
	)

Enable clock to specified module.

Parameters

moduleId	[in] module ID's
enable	[in] 1: enable clock to the module, 0: disable clock to the module

Returns: SystemP_SUCCESS Module clock is enabled; SystemP_FAILURE Module clock could not be enabled

◆ SOC_clocksEnable()

int32_t SOC_clocksEnable ( void )

Enables ADPLL.

Returns: SystemP_SUCCESS Module clock is enabled; SystemP_FAILURE Module clock could not be enabled

◆ SOC_moduleSetClockFrequency()

int32_t SOC_moduleSetClockFrequency	(	uint32_t	moduleId,
		uint32_t	clkId,
		uint64_t	clkRate
	)

Set module clock to specified frequency.

Parameters

moduleId	[in] module ID's
clkId	[in] clocks associated with the specified module ID
clkRate	[in] Frequency to set in Hz

Returns: SystemP_SUCCESS Module clock is enabled; SystemP_FAILURE Module clock could not be enabled

◆ SOC_getCoreName()

const char* SOC_getCoreName ( uint16_t coreId )

Convert a core ID to a user readable name.

Parameters

coreId [in] see CSL_CoreID

Returns: name as a string

◆ SOC_controlModuleLockMMR()

void SOC_controlModuleLockMMR	(	uint32_t	domainId,
		uint32_t	partition
	)

Lock control module partition to prevent writes into control MMRs.

Parameters

domainId	[in] See SOC_DomainId_t
partition	[in] Partition number to unlock

◆ SOC_controlModuleUnlockMMR()

void SOC_controlModuleUnlockMMR	(	uint32_t	domainId,
		uint32_t	partition
	)

Unlock control module partition to allow writes into control MMRs.

Parameters

domainId	[in] See SOC_DomainId_t
partition	[in] Partition number to unlock

◆ SOC_logAllClockHz()

void SOC_logAllClockHz ( void )

Print's module clock info to the console.

◆ SOC_virtToPhy()

uint64_t SOC_virtToPhy ( void * virtAddr )

SOC Virtual (CPU) to Physical address translation function.

Parameters

virtAddr [IN] Virtual/CPU address

Returns: Corresponding SOC physical address

◆ SOC_memoryInit()

void SOC_memoryInit ( uint16_t flag )

Initializes APPSS shared RAM0, RAM1 and HWASS Shared RAM.

◆ SOC_enableMDLLClock()

void SOC_enableMDLLClock ( void )

Enables MDLL Clock.

◆ SOC_triggerWarmReset()

void SOC_triggerWarmReset ( void )

Software Warm reset request. Generates warm reset for entire device.

◆ SOC_triggerSoftReset()

void SOC_triggerSoftReset ( void )

Soft reset request.

◆ SOC_getRstReason()

SOC_RstReason SOC_getRstReason ( void )

Retrieves the reset reason.

Returns: Reset reason

◆ SOC_getSysRstReason()

SOC_SysRstReason SOC_getSysRstReason ( void )

Retrieves the system reset reason from SYS_RST_CAUSE. All the reset registers will be cleared by the bootloader. The reset register values will be stored in BOOT_INFO_REG0[23:0] The TOP_PRCM:SYS_RST_CAUSE[2:0] is stored in APP_CTRL:APPSS_BOOT_INFO_REG0[7:4].

Returns: System reset reason

◆ SOC_setEpwmTbClk()

void SOC_setEpwmTbClk ( uint32_t enable )

Enable or disable ePWM time base clock from Control MMR.

Parameters

enable [in] TRUE to enable and FALSE to disable

Introduction

Sub Modules

Functions

Enumerations

SOC Domain ID

Macro Definition Documentation

◆ SOC_DOMAIN_ID_TOPSS_CTRL

◆ SOC_DOMAIN_ID_APP_RCM

◆ SOC_DOMAIN_ID_APP_CTRL

◆ SOC_DOMAIN_ID_TOP_IO_MUX

◆ SOC_DOMAIN_ID_TOP_PRCM

Enumeration Type Documentation

◆ SOC_SysRstReason

◆ SOC_RstReason

Function Documentation

◆ SOC_moduleClockEnable()

◆ SOC_clocksEnable()

◆ SOC_moduleSetClockFrequency()

◆ SOC_getCoreName()

◆ SOC_controlModuleLockMMR()

◆ SOC_controlModuleUnlockMMR()

◆ SOC_logAllClockHz()

◆ SOC_virtToPhy()

◆ SOC_memoryInit()

◆ SOC_enableMDLLClock()

◆ SOC_triggerWarmReset()

◆ SOC_triggerSoftReset()

◆ SOC_getRstReason()

◆ SOC_getSysRstReason()

◆ SOC_setEpwmTbClk()