cslr_soc_defines.h File Reference

Go to the source code of this file.

Macros
#define	CSL_APSS_UART_PER_CNT   (2U)
	Number of UART instances. More...
#define	CSL_APPSS_MCSPI_PER_CNT   (1U)
	Number of MIBSPI instances. More...
#define	CSL_APPSS_I2C_CNT   (1U)
	Number of I2C instances. More...
#define	CSL_APPSS_LIN_CNT   (1U)
	Number of LIN instances. More...
#define	CSL_APPSS_QSPI_CNT   (1U)
	Number of QSPI instances. More...
#define	CSL_APPSS_MCAN_CNT   (1U)
	Number of MCAN instances. More...
#define	CSL_APPSS_PWM_CNT   (1U)
	Number of PWM instances. More...
#define	SOC_EDMA_NUM_DMACH   (64U)
	Number of DMA Channels. More...
#define	SOC_EDMA_NUM_QDMACH   (8U)
	Number of QDMA Channels. More...
#define	SOC_EDMA_NUM_PARAMSETS   (128U)
	Number of PaRAM Sets available. More...
#define	SOC_EDMA_NUM_EVQUE   (2U)
	Number of Event Queues available. More...
#define	SOC_EDMA_CHMAPEXIST   (1U)
	Support for Channel to PaRAM Set mapping. More...
#define	SOC_EDMA_NUM_REGIONS   (8)
	Number of EDMA Regions. More...
#define	SOC_EDMA_MEMPROTECT   (1U)
	Support for Memory Protection. More...
#define	MCAN_MSG_RAM_MAX_WORD_COUNT   (4352U)
	MCAN Maximum Message RAM words. More...
#define	MCAN_MAX_RX_DMA_BUFFERS   (3U)
	Maximum number of Rx Dma buffers. More...
#define	MCAN_MAX_TX_DMA_BUFFERS   (3U)
	Maximum number of Tx Dma buffers. More...
#define	ESM_NUM_GROUP_MAX   (3U)
#define	ESM_NUM_INTR_PER_GROUP   (128U)
#define	EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ   0
	DSP TPCC A EVENT MAP. More...
#define	EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ   1
#define	EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ   2
#define	EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ   3
#define	EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ   4
#define	EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ   5
#define	EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ   6
#define	EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ   7
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ0   8
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ1   9
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT1   10
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT2   11
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT3   12
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT4   13
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT5   14
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT6   15
#define	EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT7   16
#define	EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0   17
#define	EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1   18
#define	EDMA_APPSS_TPCC_A_GIO_INT0   19
#define	EDMA_APPSS_TPCC_A_GIO_INT1   20
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0   21
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1   22
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2   23
#define	EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3   24
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0   25
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1   26
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2   27
#define	EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3   28
#define	EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0   29
#define	EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1   30
#define	EDMA_APPSS_TPCC_A_QSPI_DMA_REQ   31
#define	EDMA_APPSS_TPCC_A_PWM_DMA_REQ0   32
#define	EDMA_APPSS_TPCC_A_PWM_DMA_REQ1   33
#define	EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ   34
#define	EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ   35
#define	EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START   36
#define	EDMA_APPSS_TPCC_A_CHIP_AVAIL_IRQ   37
#define	EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END   38
#define	EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START   39
#define	EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END   40
#define	EDMA_APPSS_TPCC_A_ADC_VALID_START   41
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0   42
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1   43
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2   44
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3   45
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4   46
#define	EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5   47
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0   48
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1   49
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2   50
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3   51
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4   52
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5   53
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6   54
#define	EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7   55
#define	EDMA_APPSS_TPCC_A_EVT_FREE_0   56
#define	EDMA_APPSS_TPCC_A_FEC_INTR0   57
#define	EDMA_APPSS_TPCC_A_FEC_INTR1   58
#define	EDMA_APPSS_TPCC_A_FEC_INTR2   59
#define	EDMA_APPSS_TPCC_A_FEC_INTR3   60
#define	EDMA_APPSS_TPCC_A_EVT_FREE_1   61
#define	EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_RX_REQ   62
#define	EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_TX_REQ   63
#define	EDMA_APPSS_TPCC_B_EVT_FRAMETIMER_FRAME_START   0
	DSP TPCC B EVENT MAP. More...
#define	EDMA_APPSS_TPCC_B_EVT_CHIRP_AVAIL_IRQ   1
#define	EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_END   2
#define	EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_START   3
#define	EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_FRAME_END   4
#define	EDMA_APPSS_TPCC_B_EVT_ADC_VALID_START   5
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ0   6
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ1   7
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ2   8
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ3   9
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ4   10
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ5   11
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ6   12
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ7   13
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ8   14
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ9   15
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ10   16
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ11   17
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ12   18
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ13   19
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ14   20
#define	EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ15   21
#define	EDMA_APPSS_TPCC_B_EVT_HWA_LOOP_INT   22
#define	EDMA_APPSS_TPCC_B_EVT_HWA_PARAMDONE_INT   23
#define	EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_RX_REQ   24
#define	EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_TX_REQ   25
#define	EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_RX_REQ   26
#define	EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_TX_REQ   27
#define	EDMA_APPSS_TPCC_B_EVT_FREE_0   28
#define	EDMA_APPSS_TPCC_B_EVT_FREE_1   29
#define	EDMA_APPSS_TPCC_B_EVT_FREE_2   30
#define	EDMA_APPSS_TPCC_B_EVT_FREE_3   31
#define	EDMA_APPSS_TPCC_B_EVT_FREE_4   32
#define	EDMA_APPSS_TPCC_B_EVT_FREE_5   33
#define	EDMA_APPSS_TPCC_B_EVT_FREE_6   34
#define	EDMA_APPSS_TPCC_B_EVT_FREE_7   35
#define	EDMA_APPSS_TPCC_B_EVT_FREE_8   36
#define	EDMA_APPSS_TPCC_B_EVT_FREE_9   37
#define	EDMA_APPSS_TPCC_B_EVT_FREE_10   38
#define	EDMA_APPSS_TPCC_B_EVT_FREE_11   39
#define	EDMA_APPSS_TPCC_B_EVT_FREE_12   40
#define	EDMA_APPSS_TPCC_B_EVT_FREE_13   41
#define	EDMA_APPSS_TPCC_B_EVT_FREE_14   42
#define	EDMA_APPSS_TPCC_B_EVT_FREE_15   43
#define	EDMA_APPSS_TPCC_B_EVT_FREE_16   44
#define	EDMA_APPSS_TPCC_B_EVT_FREE_17   45
#define	EDMA_APPSS_TPCC_B_EVT_FREE_18   46
#define	EDMA_APPSS_TPCC_B_EVT_FREE_19   47
#define	EDMA_APPSS_TPCC_B_EVT_FREE_20   48
#define	EDMA_APPSS_TPCC_B_EVT_FREE_21   49
#define	EDMA_APPSS_TPCC_B_EVT_FREE_22   50
#define	EDMA_APPSS_TPCC_B_EVT_FREE_23   51
#define	EDMA_APPSS_TPCC_B_EVT_FREE_24   52
#define	EDMA_APPSS_TPCC_B_EVT_FREE_25   53
#define	EDMA_APPSS_TPCC_B_EVT_FREE_26   54
#define	EDMA_APPSS_TPCC_B_EVT_FREE_27   55
#define	EDMA_APPSS_TPCC_B_EVT_FREE_28   56
#define	EDMA_APPSS_TPCC_B_EVT_FREE_29   57
#define	EDMA_APPSS_TPCC_B_EVT_FREE_30   58
#define	EDMA_APPSS_TPCC_B_EVT_FREE_31   59
#define	EDMA_APPSS_TPCC_B_EVT_FREE_32   60
#define	EDMA_APPSS_TPCC_B_EVT_FREE_33   61
#define	EDMA_APPSS_TPCC_B_EVT_FREE_34   62
#define	EDMA_APPSS_TPCC_B_EVT_FREE_35   63
#define	EDMA_APPSS_TPCC_A_NUM_PARAM_SETS   (128U)
#define	EDMA_APPSS_TPCC_A_NUM_DMA_CHANS   (64U)
#define	EDMA_APPSS_TPCC_A_NUM_TC   (2U)
#define	EDMA_APPSS_TPCC_B_NUM_PARAM_SETS   (128U)
#define	EDMA_APPSS_TPCC_B_NUM_DMA_CHANS   (64U)
#define	EDMA_APPSS_TPCC_B_NUM_TC   (2U)
#define	EDMA_TPCC_ERRAGG_TPCC_EERINT__POS   (0U)
#define	EDMA_TPCC_INTAGG_TPCC_INTG__POS   (0U)
#define	EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS   (2U) /* position of the lowest TC Id, others are higher */
#define	EDMA_APPSS_NUM_CC   4
#define	EDMA_APPSS_MAX_NUM_TC
#define	EDMA_MSS_NUM_CC   6
#define	EDMA_MSS_MAX_NUM_TC
#define	HWA_NUM_INSTANCES   (1U)
#define	SOC_HWA_NUM_MEM_BANKS   (4U)
	number of HWA memory banks More...
#define	SOC_HWA_NUM_PARAM_SETS   (32U)
	number of HWA parameter sets More...
#define	SOC_HWA_NUM_DMA_CHANNEL   (16U)
	number of HWA MDA channels More...
#define	SOC_HWA_MEM_SIZE   (CSL_APP_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)
	number of HWA memory size in bytes More...
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END   (0U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END   (1U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END   (2U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END   (3U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END   (4U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END   (5U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END   (6U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END   (7U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0   (8U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1   (9U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END   (10U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END   (11U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END   (12U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END   (13U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END   (14U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END   (15U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END   (16U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END   (17U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0   (18U)
#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1   (19U)
#define	APPSS_SYS_VCLK   160000000U
Core ID's of core or CPUs present on this SOC
#define	CSL_CORE_ID_M4FSS0_0   (0U)
#define	CSL_CORE_ID_MAX   (1U)

Macro Definition Documentation

CSL_CORE_ID_M4FSS0_0

#define CSL_CORE_ID_M4FSS0_0   (0U)

CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX   (1U)

CSL_APSS_UART_PER_CNT

#define CSL_APSS_UART_PER_CNT   (2U)

Number of UART instances.

CSL_APPSS_MCSPI_PER_CNT

#define CSL_APPSS_MCSPI_PER_CNT   (1U)

Number of MIBSPI instances.

CSL_APPSS_I2C_CNT

#define CSL_APPSS_I2C_CNT   (1U)

Number of I2C instances.

CSL_APPSS_LIN_CNT

#define CSL_APPSS_LIN_CNT   (1U)

Number of LIN instances.

CSL_APPSS_QSPI_CNT

#define CSL_APPSS_QSPI_CNT   (1U)

Number of QSPI instances.

CSL_APPSS_MCAN_CNT

#define CSL_APPSS_MCAN_CNT   (1U)

Number of MCAN instances.

CSL_APPSS_PWM_CNT

#define CSL_APPSS_PWM_CNT   (1U)

Number of PWM instances.

SOC_EDMA_NUM_DMACH

#define SOC_EDMA_NUM_DMACH   (64U)

Number of DMA Channels.

SOC_EDMA_NUM_QDMACH

#define SOC_EDMA_NUM_QDMACH   (8U)

Number of QDMA Channels.

SOC_EDMA_NUM_PARAMSETS

#define SOC_EDMA_NUM_PARAMSETS   (128U)

Number of PaRAM Sets available.

SOC_EDMA_NUM_EVQUE

#define SOC_EDMA_NUM_EVQUE   (2U)

Number of Event Queues available.

SOC_EDMA_CHMAPEXIST

#define SOC_EDMA_CHMAPEXIST   (1U)

Support for Channel to PaRAM Set mapping.

SOC_EDMA_NUM_REGIONS

#define SOC_EDMA_NUM_REGIONS   (8)

Number of EDMA Regions.

SOC_EDMA_MEMPROTECT

#define SOC_EDMA_MEMPROTECT   (1U)

Support for Memory Protection.

MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT   (4352U)

MCAN Maximum Message RAM words.

MCAN_MAX_RX_DMA_BUFFERS

#define MCAN_MAX_RX_DMA_BUFFERS   (3U)

Maximum number of Rx Dma buffers.

MCAN_MAX_TX_DMA_BUFFERS

#define MCAN_MAX_TX_DMA_BUFFERS   (3U)

Maximum number of Tx Dma buffers.

ESM_NUM_GROUP_MAX

#define ESM_NUM_GROUP_MAX   (3U)

ESM_NUM_INTR_PER_GROUP

#define ESM_NUM_INTR_PER_GROUP   (128U)

EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ   0

DSP TPCC A EVENT MAP.

EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ   1

EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ   2

EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ   3

EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ   4

EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ   5

EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ   6

EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ   7

EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ0

#define EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ0   8

EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ1

#define EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ1   9

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT1

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT1   10

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT2

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT2   11

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT3

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT3   12

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT4

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT4   13

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT5

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT5   14

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT6

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT6   15

EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT7

#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT7   16

EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0

#define EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0   17

EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1

#define EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1   18

EDMA_APPSS_TPCC_A_GIO_INT0

#define EDMA_APPSS_TPCC_A_GIO_INT0   19

EDMA_APPSS_TPCC_A_GIO_INT1

#define EDMA_APPSS_TPCC_A_GIO_INT1   20

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0   21

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1   22

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2   23

EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3

#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3   24

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0   25

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1   26

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2   27

EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3

#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3   28

EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0

#define EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0   29

EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1

#define EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1   30

EDMA_APPSS_TPCC_A_QSPI_DMA_REQ

#define EDMA_APPSS_TPCC_A_QSPI_DMA_REQ   31

EDMA_APPSS_TPCC_A_PWM_DMA_REQ0

#define EDMA_APPSS_TPCC_A_PWM_DMA_REQ0   32

EDMA_APPSS_TPCC_A_PWM_DMA_REQ1

#define EDMA_APPSS_TPCC_A_PWM_DMA_REQ1   33

EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ   34

EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ   35

EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START

#define EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START   36

EDMA_APPSS_TPCC_A_CHIP_AVAIL_IRQ

#define EDMA_APPSS_TPCC_A_CHIP_AVAIL_IRQ   37

EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END

#define EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END   38

EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START

#define EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START   39

EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END

#define EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END   40

EDMA_APPSS_TPCC_A_ADC_VALID_START

#define EDMA_APPSS_TPCC_A_ADC_VALID_START   41

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0   42

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1   43

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2   44

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3   45

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4   46

EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5

#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5   47

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0   48

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1   49

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2   50

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3   51

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4   52

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5   53

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6   54

EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7

#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7   55

EDMA_APPSS_TPCC_A_EVT_FREE_0

#define EDMA_APPSS_TPCC_A_EVT_FREE_0   56

EDMA_APPSS_TPCC_A_FEC_INTR0

#define EDMA_APPSS_TPCC_A_FEC_INTR0   57

EDMA_APPSS_TPCC_A_FEC_INTR1

#define EDMA_APPSS_TPCC_A_FEC_INTR1   58

EDMA_APPSS_TPCC_A_FEC_INTR2

#define EDMA_APPSS_TPCC_A_FEC_INTR2   59

EDMA_APPSS_TPCC_A_FEC_INTR3

#define EDMA_APPSS_TPCC_A_FEC_INTR3   60

EDMA_APPSS_TPCC_A_EVT_FREE_1

#define EDMA_APPSS_TPCC_A_EVT_FREE_1   61

EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_RX_REQ

#define EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_RX_REQ   62

EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_TX_REQ

#define EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_TX_REQ   63

EDMA_APPSS_TPCC_B_EVT_FRAMETIMER_FRAME_START

#define EDMA_APPSS_TPCC_B_EVT_FRAMETIMER_FRAME_START   0

DSP TPCC B EVENT MAP.

EDMA_APPSS_TPCC_B_EVT_CHIRP_AVAIL_IRQ

#define EDMA_APPSS_TPCC_B_EVT_CHIRP_AVAIL_IRQ   1

EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_END

#define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_END   2

EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_START

#define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_START   3

EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_FRAME_END

#define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_FRAME_END   4

EDMA_APPSS_TPCC_B_EVT_ADC_VALID_START

#define EDMA_APPSS_TPCC_B_EVT_ADC_VALID_START   5

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ0

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ0   6

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ1

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ1   7

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ2

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ2   8

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ3

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ3   9

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ4

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ4   10

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ5

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ5   11

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ6

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ6   12

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ7

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ7   13

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ8

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ8   14

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ9

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ9   15

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ10

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ10   16

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ11

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ11   17

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ12

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ12   18

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ13

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ13   19

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ14

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ14   20

EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ15

#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ15   21

EDMA_APPSS_TPCC_B_EVT_HWA_LOOP_INT

#define EDMA_APPSS_TPCC_B_EVT_HWA_LOOP_INT   22

EDMA_APPSS_TPCC_B_EVT_HWA_PARAMDONE_INT

#define EDMA_APPSS_TPCC_B_EVT_HWA_PARAMDONE_INT   23

EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_RX_REQ

#define EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_RX_REQ   24

EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_TX_REQ

#define EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_TX_REQ   25

EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_RX_REQ

#define EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_RX_REQ   26

EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_TX_REQ

#define EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_TX_REQ   27

EDMA_APPSS_TPCC_B_EVT_FREE_0

#define EDMA_APPSS_TPCC_B_EVT_FREE_0   28

EDMA_APPSS_TPCC_B_EVT_FREE_1

#define EDMA_APPSS_TPCC_B_EVT_FREE_1   29

EDMA_APPSS_TPCC_B_EVT_FREE_2

#define EDMA_APPSS_TPCC_B_EVT_FREE_2   30

EDMA_APPSS_TPCC_B_EVT_FREE_3

#define EDMA_APPSS_TPCC_B_EVT_FREE_3   31

EDMA_APPSS_TPCC_B_EVT_FREE_4

#define EDMA_APPSS_TPCC_B_EVT_FREE_4   32

EDMA_APPSS_TPCC_B_EVT_FREE_5

#define EDMA_APPSS_TPCC_B_EVT_FREE_5   33

EDMA_APPSS_TPCC_B_EVT_FREE_6

#define EDMA_APPSS_TPCC_B_EVT_FREE_6   34

EDMA_APPSS_TPCC_B_EVT_FREE_7

#define EDMA_APPSS_TPCC_B_EVT_FREE_7   35

EDMA_APPSS_TPCC_B_EVT_FREE_8

#define EDMA_APPSS_TPCC_B_EVT_FREE_8   36

EDMA_APPSS_TPCC_B_EVT_FREE_9

#define EDMA_APPSS_TPCC_B_EVT_FREE_9   37

EDMA_APPSS_TPCC_B_EVT_FREE_10

#define EDMA_APPSS_TPCC_B_EVT_FREE_10   38

EDMA_APPSS_TPCC_B_EVT_FREE_11

#define EDMA_APPSS_TPCC_B_EVT_FREE_11   39

EDMA_APPSS_TPCC_B_EVT_FREE_12

#define EDMA_APPSS_TPCC_B_EVT_FREE_12   40

EDMA_APPSS_TPCC_B_EVT_FREE_13

#define EDMA_APPSS_TPCC_B_EVT_FREE_13   41

EDMA_APPSS_TPCC_B_EVT_FREE_14

#define EDMA_APPSS_TPCC_B_EVT_FREE_14   42

EDMA_APPSS_TPCC_B_EVT_FREE_15

#define EDMA_APPSS_TPCC_B_EVT_FREE_15   43

EDMA_APPSS_TPCC_B_EVT_FREE_16

#define EDMA_APPSS_TPCC_B_EVT_FREE_16   44

EDMA_APPSS_TPCC_B_EVT_FREE_17

#define EDMA_APPSS_TPCC_B_EVT_FREE_17   45

EDMA_APPSS_TPCC_B_EVT_FREE_18

#define EDMA_APPSS_TPCC_B_EVT_FREE_18   46

EDMA_APPSS_TPCC_B_EVT_FREE_19

#define EDMA_APPSS_TPCC_B_EVT_FREE_19   47

EDMA_APPSS_TPCC_B_EVT_FREE_20

#define EDMA_APPSS_TPCC_B_EVT_FREE_20   48

EDMA_APPSS_TPCC_B_EVT_FREE_21

#define EDMA_APPSS_TPCC_B_EVT_FREE_21   49

EDMA_APPSS_TPCC_B_EVT_FREE_22

#define EDMA_APPSS_TPCC_B_EVT_FREE_22   50

EDMA_APPSS_TPCC_B_EVT_FREE_23

#define EDMA_APPSS_TPCC_B_EVT_FREE_23   51

EDMA_APPSS_TPCC_B_EVT_FREE_24

#define EDMA_APPSS_TPCC_B_EVT_FREE_24   52

EDMA_APPSS_TPCC_B_EVT_FREE_25

#define EDMA_APPSS_TPCC_B_EVT_FREE_25   53

EDMA_APPSS_TPCC_B_EVT_FREE_26

#define EDMA_APPSS_TPCC_B_EVT_FREE_26   54

EDMA_APPSS_TPCC_B_EVT_FREE_27

#define EDMA_APPSS_TPCC_B_EVT_FREE_27   55

EDMA_APPSS_TPCC_B_EVT_FREE_28

#define EDMA_APPSS_TPCC_B_EVT_FREE_28   56

EDMA_APPSS_TPCC_B_EVT_FREE_29

#define EDMA_APPSS_TPCC_B_EVT_FREE_29   57

EDMA_APPSS_TPCC_B_EVT_FREE_30

#define EDMA_APPSS_TPCC_B_EVT_FREE_30   58

EDMA_APPSS_TPCC_B_EVT_FREE_31

#define EDMA_APPSS_TPCC_B_EVT_FREE_31   59

EDMA_APPSS_TPCC_B_EVT_FREE_32

#define EDMA_APPSS_TPCC_B_EVT_FREE_32   60

EDMA_APPSS_TPCC_B_EVT_FREE_33

#define EDMA_APPSS_TPCC_B_EVT_FREE_33   61

EDMA_APPSS_TPCC_B_EVT_FREE_34

#define EDMA_APPSS_TPCC_B_EVT_FREE_34   62

EDMA_APPSS_TPCC_B_EVT_FREE_35

#define EDMA_APPSS_TPCC_B_EVT_FREE_35   63

EDMA_APPSS_TPCC_A_NUM_PARAM_SETS

#define EDMA_APPSS_TPCC_A_NUM_PARAM_SETS   (128U)

EDMA_APPSS_TPCC_A_NUM_DMA_CHANS

#define EDMA_APPSS_TPCC_A_NUM_DMA_CHANS   (64U)

EDMA_APPSS_TPCC_A_NUM_TC

#define EDMA_APPSS_TPCC_A_NUM_TC   (2U)

EDMA_APPSS_TPCC_B_NUM_PARAM_SETS

#define EDMA_APPSS_TPCC_B_NUM_PARAM_SETS   (128U)

EDMA_APPSS_TPCC_B_NUM_DMA_CHANS

#define EDMA_APPSS_TPCC_B_NUM_DMA_CHANS   (64U)

EDMA_APPSS_TPCC_B_NUM_TC

#define EDMA_APPSS_TPCC_B_NUM_TC   (2U)

EDMA_TPCC_ERRAGG_TPCC_EERINT__POS

#define EDMA_TPCC_ERRAGG_TPCC_EERINT__POS   (0U)

EDMA_TPCC_INTAGG_TPCC_INTG__POS

#define EDMA_TPCC_INTAGG_TPCC_INTG__POS   (0U)

EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS

#define EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS   (2U) /* position of the lowest TC Id, others are higher */

EDMA_APPSS_NUM_CC

#define EDMA_APPSS_NUM_CC   4

EDMA_APPSS_MAX_NUM_TC

#define EDMA_APPSS_MAX_NUM_TC

Value:

                                CSL_MAX(EDMA_APPSS_TPCC_A_NUM_TC, \
                                CSL_MAX(EDMA_APPSS_TPCC_B_NUM_TC, \
                                CSL_MAX(EDMA_APPSS_TPCC_C_NUM_TC, \
                                EDMA_RCSS_TPCC_A_NUM_TC)))

EDMA_MSS_NUM_CC

#define EDMA_MSS_NUM_CC   6

EDMA_MSS_MAX_NUM_TC

#define EDMA_MSS_MAX_NUM_TC

Value:

                                CSL_MAX(EDMA_MSS_TPCC_A_NUM_TC, \
                                CSL_MAX(EDMA_MSS_TPCC_B_NUM_TC, \
                                CSL_MAX(EDMA_APPSS_TPCC_A_NUM_TC, \
                                CSL_MAX(EDMA_APPSS_TPCC_B_NUM_TC, \
                                CSL_MAX(EDMA_APPSS_TPCC_C_NUM_TC, \
                                EDMA_RCSS_TPCC_A_NUM_TC)))))

HWA_NUM_INSTANCES

#define HWA_NUM_INSTANCES   (1U)

SOC_HWA_NUM_MEM_BANKS

#define SOC_HWA_NUM_MEM_BANKS   (4U)

number of HWA memory banks

SOC_HWA_NUM_PARAM_SETS

#define SOC_HWA_NUM_PARAM_SETS   (32U)

number of HWA parameter sets

SOC_HWA_NUM_DMA_CHANNEL

#define SOC_HWA_NUM_DMA_CHANNEL   (16U)

number of HWA MDA channels

SOC_HWA_MEM_SIZE

#define SOC_HWA_MEM_SIZE   (CSL_APP_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)

number of HWA memory size in bytes

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END   (0U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END   (1U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END   (2U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END   (3U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END   (4U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END   (5U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END   (6U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END   (7U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0   (8U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1   (9U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END   (10U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END   (11U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END   (12U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END   (13U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END   (14U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END   (15U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END   (16U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END   (17U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0   (18U)

HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1   (19U)

APPSS_SYS_VCLK

#define APPSS_SYS_VCLK   160000000U