Introduction

For more details and example usage, see SOC

Functions
void	SOC_rcmEnableADPLLClock ()
	Enable ADPLL. More...

int32_t	SOC_rcmSetM4Clock (uint32_t m4FreqHz)
	Set M4 frequency. More...

int32_t	SOC_rcmSetM4ClockSrc (SOC_rcmM4ClockSrc m4Src)
	Set M4 Clock Source. More...

uint32_t	SOC_rcmGetM4Clock (void)
	Get M4 frequency. More...

int32_t	SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
	Set peripheral frequency. More...

uint32_t	SOC_rcmGetPeripheralClock (SOC_RcmPeripheralId periphId)
	Get peripheral frequency. More...

SOC_RcmResetCause	SOC_rcmGetResetCause (void)
	Get SOC reset cause. More...

int32_t	SOC_rcmEnablePeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockGate enable)
	Enable/Disable peripheral Clock gating. More...

void	SOC_rcmStartInitSharedRam (uint16_t flag)
	Start memory initialization for APPSS Shared Memory RAM0, RAM1 and HWASS Shared RAM. More...

void	SOC_rcmWaitMemInitSharedRam (uint16_t flag)
	Wait memory initialization to complete APSS Shared Memory RAM0, RAM1 and HWA Shared RAM. More...

void	SOC_rcmStartMemInitTpcc (uint16_t flag)
	Start memory initialization for TPCCA and TPCCB. More...

void	SOC_rcmWaitMemInitTpcc (uint16_t flag)
	Wait memory initialization to complete TPCCA and TPCCB. More...

uint8_t	SOC_getEfuseRomVersion (void)
	Reads EFUSEROM_VER from TOP Efuse memory. More...

uint8_t	SOC_rcmReadSynthTrimValid (void)
	Reads SYNTH_TRIM_VALID field from TOP Efuse memory. More...

uint8_t	SOC_rcmReadAPLLCalibTrimValid (void)
	Reads APLL_CALIB_TRIM_VALID field from TOP Efuse memory. More...

uint8_t	SOC_getEfusePgVersion (void)
	Reads PG_VER field from TOP Efuse memory. More...

uint8_t	SOC_isDeviceAOP (void)
	Reads ANTENNA TYPE field from TOP Efuse memory. More...

Enumerations
enum	SOC_rcmM4ClockSrc { SOC_rcmM4ClockSrc_OSC_CLK = 0x000, SOC_rcmM4ClockSrc_SLOW_CLK = 0x111, SOC_rcmM4ClockSrc_MDLL_CLK = 0x222, SOC_rcmM4ClockSrc_FAST_CLK = 0x333 }

enum	SOC_RcmResetCause { SOC_RcmResetCause_POWER_CAUSE_CLEAR = 0x0U, SOC_RcmResetCause_POWER_ON_RESET = 0x1U, SOC_RcmResetCause_WARM_RESET = 0x2U, SOC_RcmResetCause_STC_RESET = 0x4U, SOC_RcmResetCause_CPU_ONLY_RESET = 0x10U, SOC_RcmResetCause_CORE_RESET = 0x20U, SOC_RcmResetCause_MAX_VALUE = 0xFFFFFFFFu }
	Reset Causes. More...

enum	SOC_RcmPeripheralId { SOC_RcmPeripheralId_APPSS_MCAN, SOC_RcmPeripheralId_APPSS_LIN, SOC_RcmPeripheralId_APPSS_QSPI, SOC_RcmPeripheralId_APPSS_RTI, SOC_RcmPeripheralId_APPSS_WDT, SOC_RcmPeripheralId_APPSS_MCSPIA, SOC_RcmPeripheralId_APPSS_MCSPIB, SOC_RcmPeripheralId_APPSS_I2C, SOC_RcmPeripheralId_APPSS_UART0, SOC_RcmPeripheralId_APPSS_UART1, SOC_RcmPeripheralId_APPSS_ESM, SOC_RcmPeripheralId_APPSS_EDMA, SOC_RcmPeripheralId_APPSS_CRC, SOC_RcmPeripheralId_APPSS_PWM, SOC_RcmPeripheralId_APPSS_GIO, SOC_RcmPeripheralId_HWASS, SOC_RcmPeripheralId_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral IDs. More...

enum	SOC_RcmPeripheralClockSource { SOC_RcmPeripheralClockSource_OSC_CLK, SOC_RcmPeripheralClockSource_SLOW_CLK, SOC_RcmPeripheralClockSource_MDLL_CLK, SOC_RcmPeripheralClockSource_FAST_CLK, SOC_RcmPeripheralClockSource_XREF_IN_CLK, SOC_RcmPeripheralClockSource_OSC_CLKX2, SOC_RcmPeripheralClockSource_RC_CLK_10M, SOC_RcmPeripheralClockSource_RCCLK32K, SOC_RcmPeripheralClockSource_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral Clock Sources. More...

enum	SOC_RcmM4ClockSource { SOC_RcmM4ClockSource_OSC_CLK, SOC_RcmM4ClockSource_SLOW_CLK, SOC_RcmM4ClockSource_MDLL_CLK, SOC_RcmM4ClockSource_FAST_CLK, SOC_RcmM4ClockSource_MAX_VALUE = 0xFFFFFFFFu }
	M4 Clock Sources. More...

enum	SOC_RcmQspiClockFreqId { SOC_RcmQspiClockFreqId_CLK_40MHZ = 0x0, SOC_RcmQspiClockFreqId_CLK_60MHZ = 0x1, SOC_RcmQspiClockFreqId_CLK_80MHZ = 0x2, SOC_RcmQspiClockFreqId_MAX_VALUE = 0xFFFFFFFFu }
	QSPI frequency values. More...

enum	SOC_RcmPeripheralClockGate { SOC_RcmPeripheralClockGateEnable, SOC_RcmPeripheralClockGateDisable }
	Peripheral Clock Gate Status. More...

Macros
#define	SOC_RCM_FREQ_HZ2MHZ(hz) ((hz)/(1000000U))

#define	SOC_RCM_FREQ_MHZ2HZ(mhz) ((mhz)*(1000000U))

#define	SOC_RCM_MEMINIT_APPSS_RAM1A_INIT (1U << 0U)

#define	SOC_RCM_MEMINIT_APPSS_RAM2A_INIT (1U << 1U)

#define	SOC_RCM_MEMINIT_APPSS_RAM3A_INIT (1U << 2U)

#define	SOC_RCM_MEMINIT_APPSS_ALL_INIT

#define	SOC_RCM_MEMINIT_APPSS_SHRAM0_INIT (0x1U)

#define	SOC_RCM_MEMINIT_APPSS_SHRAM1_INIT (0x1U << 1U)

#define	SOC_RCM_MEMINIT_HWA_SHRAM_INIT (0x1U << 2U)

#define	SOC_RCM_MEMINIT_FECSS_SHRAM_INIT (0x1U << 3U)

#define	SOC_RCM_MEMINIT_TPCCA_INIT (0x1U << 8U)

#define	SOC_RCM_MEMINIT_TPCCB_INIT (0x1U << 9U)

#define	SOC_RCM_EFUSEROM_VER_2 ((uint8_t)(0x02U))
	ROM version 2 devices. More...

Macro Definition Documentation

◆ SOC_RCM_FREQ_HZ2MHZ

#define SOC_RCM_FREQ_HZ2MHZ ( hz ) ((hz)/(1000000U))

◆ SOC_RCM_FREQ_MHZ2HZ

#define SOC_RCM_FREQ_MHZ2HZ ( mhz ) ((mhz)*(1000000U))

◆ SOC_RCM_MEMINIT_APPSS_RAM1A_INIT

#define SOC_RCM_MEMINIT_APPSS_RAM1A_INIT (1U << 0U)

◆ SOC_RCM_MEMINIT_APPSS_RAM2A_INIT

#define SOC_RCM_MEMINIT_APPSS_RAM2A_INIT (1U << 1U)

◆ SOC_RCM_MEMINIT_APPSS_RAM3A_INIT

#define SOC_RCM_MEMINIT_APPSS_RAM3A_INIT (1U << 2U)

◆ SOC_RCM_MEMINIT_APPSS_ALL_INIT

#define SOC_RCM_MEMINIT_APPSS_ALL_INIT

Value:

                                               (SOC_RCM_MEMINIT_APPSS_RAM1A_INIT | \
                                               SOC_RCM_MEMINIT_APPSS_RAM2A_INIT | \
                                               SOC_RCM_MEMINIT_APPSS_RAM3A_INIT)

◆ SOC_RCM_MEMINIT_APPSS_SHRAM0_INIT

#define SOC_RCM_MEMINIT_APPSS_SHRAM0_INIT (0x1U)

◆ SOC_RCM_MEMINIT_APPSS_SHRAM1_INIT

#define SOC_RCM_MEMINIT_APPSS_SHRAM1_INIT (0x1U << 1U)

◆ SOC_RCM_MEMINIT_HWA_SHRAM_INIT

#define SOC_RCM_MEMINIT_HWA_SHRAM_INIT (0x1U << 2U)

◆ SOC_RCM_MEMINIT_FECSS_SHRAM_INIT

#define SOC_RCM_MEMINIT_FECSS_SHRAM_INIT (0x1U << 3U)

◆ SOC_RCM_MEMINIT_TPCCA_INIT

#define SOC_RCM_MEMINIT_TPCCA_INIT (0x1U << 8U)

◆ SOC_RCM_MEMINIT_TPCCB_INIT

#define SOC_RCM_MEMINIT_TPCCB_INIT (0x1U << 9U)

◆ SOC_RCM_EFUSEROM_VER_2

#define SOC_RCM_EFUSEROM_VER_2 ((uint8_t)(0x02U))

ROM version 2 devices.

Enumeration Type Documentation

◆ SOC_rcmM4ClockSrc

enum SOC_rcmM4ClockSrc

Enumerator
SOC_rcmM4ClockSrc_OSC_CLK
SOC_rcmM4ClockSrc_SLOW_CLK
SOC_rcmM4ClockSrc_MDLL_CLK
SOC_rcmM4ClockSrc_FAST_CLK

◆ SOC_RcmResetCause

enum SOC_RcmResetCause

Reset Causes.

Enumerator
SOC_RcmResetCause_POWER_CAUSE_CLEAR	Value specifying Reset Cause Clear.
SOC_RcmResetCause_POWER_ON_RESET	Value specifying Power ON Reset.
SOC_RcmResetCause_WARM_RESET	Value specifying Warm Reset or Subsystem Reset.
SOC_RcmResetCause_STC_RESET	Value specifying STC Reset.
SOC_RcmResetCause_CPU_ONLY_RESET	Value specifying M4 CPU Reset.
SOC_RcmResetCause_CORE_RESET	Value specifying M4 Core Reset.
SOC_RcmResetCause_MAX_VALUE	max value

◆ SOC_RcmPeripheralId

enum SOC_RcmPeripheralId

Peripheral IDs.

Enumerator
SOC_RcmPeripheralId_APPSS_MCAN	Value specifying CAN.
SOC_RcmPeripheralId_APPSS_LIN	Value specifying LIN.
SOC_RcmPeripheralId_APPSS_QSPI	Value specifying QSPI (Quad SPI)
SOC_RcmPeripheralId_APPSS_RTI	Value specifying APPSS RTIA (Timer)
SOC_RcmPeripheralId_APPSS_WDT	Value specifying APPSS WatchDog.
SOC_RcmPeripheralId_APPSS_MCSPIA	Value specifying APPSS SPI-0.
SOC_RcmPeripheralId_APPSS_MCSPIB	Value specifying APPSS SPI-1.
SOC_RcmPeripheralId_APPSS_I2C	Value specifying APPSS I2C.
SOC_RcmPeripheralId_APPSS_UART0	Value specifying APPSS SCI-A (UART)
SOC_RcmPeripheralId_APPSS_UART1	Value specifying APPSS SCI-B (UART)
SOC_RcmPeripheralId_APPSS_ESM	Value specifying APPSS ESM.
SOC_RcmPeripheralId_APPSS_EDMA	Value specifying APPSS EDMA.
SOC_RcmPeripheralId_APPSS_CRC	Value specifying APPSS CRC.
SOC_RcmPeripheralId_APPSS_PWM	Value specifying APPSS PWM.
SOC_RcmPeripheralId_APPSS_GIO	Value specifying APPSS PWM.
SOC_RcmPeripheralId_HWASS	Value specifying HWASS.
SOC_RcmPeripheralId_MAX_VALUE	max value

◆ SOC_RcmPeripheralClockSource

enum SOC_RcmPeripheralClockSource

Peripheral Clock Sources.

Enumerator
SOC_RcmPeripheralClockSource_OSC_CLK	Value specifying Crystal Clock (40MHz)
SOC_RcmPeripheralClockSource_SLOW_CLK	Value specifying Slow Clock (33Khz)
SOC_RcmPeripheralClockSource_MDLL_CLK	Value specifying MDLL Clock (160Mhz)
SOC_RcmPeripheralClockSource_FAST_CLK	Value specifying Fast Clock (160Mhz)
SOC_RcmPeripheralClockSource_XREF_IN_CLK	Value specifying XREF_IN Clock (40MHz)
SOC_RcmPeripheralClockSource_OSC_CLKX2	Value specifying OSC_CLKx2 Clock (80Mhz)
SOC_RcmPeripheralClockSource_RC_CLK_10M	Value specifying RC_CLK_10M Clock (10Mhz)
SOC_RcmPeripheralClockSource_RCCLK32K	Value specifying RCCLK32K Clock (32KHz)
SOC_RcmPeripheralClockSource_MAX_VALUE	max value

◆ SOC_RcmM4ClockSource

enum SOC_RcmM4ClockSource

M4 Clock Sources.

Enumerator
SOC_RcmM4ClockSource_OSC_CLK
SOC_RcmM4ClockSource_SLOW_CLK
SOC_RcmM4ClockSource_MDLL_CLK
SOC_RcmM4ClockSource_FAST_CLK
SOC_RcmM4ClockSource_MAX_VALUE

◆ SOC_RcmQspiClockFreqId

enum SOC_RcmQspiClockFreqId

QSPI frequency values.

Enumerator
SOC_RcmQspiClockFreqId_CLK_40MHZ	Value specifying QSPI clock of 40 Mhz.
SOC_RcmQspiClockFreqId_CLK_60MHZ	Value specifying QSPI clock of 60 Mhz.
SOC_RcmQspiClockFreqId_CLK_80MHZ	Value specifying QSPI clock of 80 Mhz.
SOC_RcmQspiClockFreqId_MAX_VALUE	max value

◆ SOC_RcmPeripheralClockGate

enum SOC_RcmPeripheralClockGate

Peripheral Clock Gate Status.

Enumerator
SOC_RcmPeripheralClockGateEnable	Peripheral Clock Ungate.
SOC_RcmPeripheralClockGateDisable	Peripheral Clock Gate.

Function Documentation

◆ SOC_rcmEnableADPLLClock()

void SOC_rcmEnableADPLLClock ( )

Enable ADPLL.

◆ SOC_rcmSetM4Clock()

int32_t SOC_rcmSetM4Clock ( uint32_t m4FreqHz )

Set M4 frequency.

Parameters

m4FreqHz [in] M4 frequency, in Hz

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_rcmSetM4ClockSrc()

int32_t SOC_rcmSetM4ClockSrc ( SOC_rcmM4ClockSrc m4Src )

Set M4 Clock Source.

Parameters

m4Src [in] Clock Source Enum

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_rcmGetM4Clock()

uint32_t SOC_rcmGetM4Clock ( void )

Get M4 frequency.

Returns: M4 frequency, in Hz

◆ SOC_rcmSetPeripheralClock()

int32_t SOC_rcmSetPeripheralClock	(	SOC_RcmPeripheralId	periphId,
		SOC_RcmPeripheralClockSource	clkSource,
		uint32_t	freqHz
	)

Set peripheral frequency.

Parameters

periphId	[in] Peripheral ID
clkSource	[in] Peripheral clock source to use
freqHz	[in] Peripheral frequency, in Hz

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_rcmGetPeripheralClock()

uint32_t SOC_rcmGetPeripheralClock ( SOC_RcmPeripheralId periphId )

Get peripheral frequency.

Parameters

periphId [in] Peripheral ID

Returns: Peripheral frequency, in Hz

◆ SOC_rcmGetResetCause()

SOC_RcmResetCause SOC_rcmGetResetCause ( void )

Get SOC reset cause.

Returns: SOC reset cause

◆ SOC_rcmEnablePeripheralClock()

int32_t SOC_rcmEnablePeripheralClock	(	SOC_RcmPeripheralId	periphId,
		SOC_RcmPeripheralClockGate	enable
	)

Enable/Disable peripheral Clock gating.

This API programs the IP clock gates
for a specified peripheral Id.

Parameters

periphId	[in] Peripheral ID
enable	[in] ungate / gate clock

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_rcmStartInitSharedRam()

void SOC_rcmStartInitSharedRam ( uint16_t flag )

Start memory initialization for APPSS Shared Memory RAM0, RAM1 and HWASS Shared RAM.

◆ SOC_rcmWaitMemInitSharedRam()

void SOC_rcmWaitMemInitSharedRam ( uint16_t flag )

Wait memory initialization to complete APSS Shared Memory RAM0, RAM1 and HWA Shared RAM.

◆ SOC_rcmStartMemInitTpcc()

void SOC_rcmStartMemInitTpcc ( uint16_t flag )

Start memory initialization for TPCCA and TPCCB.

◆ SOC_rcmWaitMemInitTpcc()

void SOC_rcmWaitMemInitTpcc ( uint16_t flag )

Wait memory initialization to complete TPCCA and TPCCB.

◆ SOC_getEfuseRomVersion()

uint8_t SOC_getEfuseRomVersion ( void )

Reads EFUSEROM_VER from TOP Efuse memory.

◆ SOC_rcmReadSynthTrimValid()

uint8_t SOC_rcmReadSynthTrimValid ( void )

Reads SYNTH_TRIM_VALID field from TOP Efuse memory.

◆ SOC_rcmReadAPLLCalibTrimValid()

uint8_t SOC_rcmReadAPLLCalibTrimValid ( void )

Reads APLL_CALIB_TRIM_VALID field from TOP Efuse memory.

◆ SOC_getEfusePgVersion()

uint8_t SOC_getEfusePgVersion ( void )

Reads PG_VER field from TOP Efuse memory.

◆ SOC_isDeviceAOP()

uint8_t SOC_isDeviceAOP ( void )

Reads ANTENNA TYPE field from TOP Efuse memory.

Introduction

Functions

Enumerations

Macros

Macro Definition Documentation

◆ SOC_RCM_FREQ_HZ2MHZ

◆ SOC_RCM_FREQ_MHZ2HZ

◆ SOC_RCM_MEMINIT_APPSS_RAM1A_INIT

◆ SOC_RCM_MEMINIT_APPSS_RAM2A_INIT

◆ SOC_RCM_MEMINIT_APPSS_RAM3A_INIT

◆ SOC_RCM_MEMINIT_APPSS_ALL_INIT

◆ SOC_RCM_MEMINIT_APPSS_SHRAM0_INIT

◆ SOC_RCM_MEMINIT_APPSS_SHRAM1_INIT

◆ SOC_RCM_MEMINIT_HWA_SHRAM_INIT

◆ SOC_RCM_MEMINIT_FECSS_SHRAM_INIT

◆ SOC_RCM_MEMINIT_TPCCA_INIT

◆ SOC_RCM_MEMINIT_TPCCB_INIT

◆ SOC_RCM_EFUSEROM_VER_2

Enumeration Type Documentation

◆ SOC_rcmM4ClockSrc

◆ SOC_RcmResetCause

◆ SOC_RcmPeripheralId

◆ SOC_RcmPeripheralClockSource

◆ SOC_RcmM4ClockSource

◆ SOC_RcmQspiClockFreqId

◆ SOC_RcmPeripheralClockGate

Function Documentation

◆ SOC_rcmEnableADPLLClock()

◆ SOC_rcmSetM4Clock()

◆ SOC_rcmSetM4ClockSrc()

◆ SOC_rcmGetM4Clock()

◆ SOC_rcmSetPeripheralClock()

◆ SOC_rcmGetPeripheralClock()

◆ SOC_rcmGetResetCause()

◆ SOC_rcmEnablePeripheralClock()

◆ SOC_rcmStartInitSharedRam()

◆ SOC_rcmWaitMemInitSharedRam()

◆ SOC_rcmStartMemInitTpcc()

◆ SOC_rcmWaitMemInitTpcc()

◆ SOC_getEfuseRomVersion()

◆ SOC_rcmReadSynthTrimValid()

◆ SOC_rcmReadAPLLCalibTrimValid()

◆ SOC_getEfusePgVersion()

◆ SOC_isDeviceAOP()