bissc_drv.h File Reference

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Data Structures
struct	bissc_clk_cfg
	Structure defining EnDat clock configuration for selected frequency. More...
struct	bissc_position_info
	Structure defining BiSSC Position data results. More...
struct	bissc_control_info
	Structure defining BiSSC Channel specific control communication(ctrl) results. More...
struct	bissc_priv
	Initialize BiSS-C firmware interface address and get the pointer to struct bissc_priv instance. More...

Macros
#define	BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU   (0U)
#define	BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU   (1U)
#define	BISSC_MODE_MULTI_CHANNEL_MULTI_PRU   (2U)
#define	BISSC_MAX_CYCLE_TIMEOUT   5
#define	NUM_ED_CH_MAX   3
#define	NUM_ENCODERS_MAX   3
#define	BISSC_MAX_PROC_DELAY_1MHZ   40
#define	BISSC_MAX_PROC_DELAY_2MHZ   80
#define	BISSC_MAX_PROC_DELAY_5MHZ   200
#define	BISSC_MAX_PROC_DELAY_8MHZ   320
#define	BISSC_MAX_PROC_DELAY_10MHZ   400
#define	BISSC_CTS_BIT   1 /* CTS bit for control communication */
#define	BISSC_ENC_ID_LEN   3 /* Number of Encoder ID bits */
#define	BISSC_ENC_ID_MASK   0x7 /* Mask for encoder ID*/
#define	BISSC_REG_ADDR_LEN   7 /* Number of bits for Register address */
#define	BISSC_REG_ADDR_MASK   0x7F /* Mask for Register address */
#define	BISSC_RWS_LEN   3 /* Number of RWS bits */
#define	BISSC_RWS_MASK   0x7 /* Mask for RWS bits */
#define	BISSC_CTRL_READ_ACCESS   0x5 /* RWS = "101" for read access of register */
#define	BISSC_CTRL_WRITE_ACCESS   0x3 /* RWS = "011" for write access of register */
#define	BISSC_REG_DATA_LEN   8 /* Number of Register data bits */
#define	BISSC_REG_DATA_MASK   0xFF /* Mask for Register data */
#define	BISSC_CTRL_STOP_LEN   2 /* Number of stop bits PS, P: stop bit for one frame, S: stop bit for sequential control communication */
#define	BISSC_RX_SAMPLE_SIZE   7 /* 8x over clock */
#define	BISSC_RX_SAMPLE_SIZE_10MHZ   3 /* 4x over clock */
#define	BISSC_POS_CRC_LEN   6 /* Number of position data CRC bits */
#define	BISSC_EW_LEN   2 /* Number of Error and Warning bits */
#define	BISSC_CTRL_CMD_CRC_LEN   4 /* Number of CTRL cmd CRC bits */
#define	BISSC_CTRL_CMD_CRC_MASK   0xF /* Mask for CTRL cmd CRC bits */
#define	BISSC_POS_DATA_LEN_DEFAULT   12 /* Default data length instead of garbage*/
#define	BISSC_SAFETY_CRC_LEN   16 /* Number of Safety CRC bits */
#define	BISSC_RX_ENABLE_FRACTIONAL_DIV   (1<<15) /* Enable fractional divider 1.5 for RX */
#define	BISSC_FREQ_1MHZ   1
#define	BISSC_FREQ_2MHZ   2
#define	BISSC_FREQ_5MHZ   5
#define	BISSC_FREQ_8MHZ   8
#define	BISSC_FREQ_10MHZ   10

Macro Definition Documentation

BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU

#define BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU   (0U)

BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU

#define BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU   (1U)

BISSC_MODE_MULTI_CHANNEL_MULTI_PRU

#define BISSC_MODE_MULTI_CHANNEL_MULTI_PRU   (2U)

BISSC_MAX_CYCLE_TIMEOUT

#define BISSC_MAX_CYCLE_TIMEOUT   5

NUM_ED_CH_MAX

#define NUM_ED_CH_MAX   3

NUM_ENCODERS_MAX

#define NUM_ENCODERS_MAX   3

BISSC_MAX_PROC_DELAY_1MHZ

#define BISSC_MAX_PROC_DELAY_1MHZ   40

BISSC_MAX_PROC_DELAY_2MHZ

#define BISSC_MAX_PROC_DELAY_2MHZ   80

BISSC_MAX_PROC_DELAY_5MHZ

#define BISSC_MAX_PROC_DELAY_5MHZ   200

BISSC_MAX_PROC_DELAY_8MHZ

#define BISSC_MAX_PROC_DELAY_8MHZ   320

BISSC_MAX_PROC_DELAY_10MHZ

#define BISSC_MAX_PROC_DELAY_10MHZ   400

BISSC_CTS_BIT

#define BISSC_CTS_BIT   1 /* CTS bit for control communication */

BISSC_ENC_ID_LEN

#define BISSC_ENC_ID_LEN   3 /* Number of Encoder ID bits */

BISSC_ENC_ID_MASK

#define BISSC_ENC_ID_MASK   0x7 /* Mask for encoder ID*/

BISSC_REG_ADDR_LEN

#define BISSC_REG_ADDR_LEN   7 /* Number of bits for Register address */

BISSC_REG_ADDR_MASK

#define BISSC_REG_ADDR_MASK   0x7F /* Mask for Register address */

BISSC_RWS_LEN

#define BISSC_RWS_LEN   3 /* Number of RWS bits */

BISSC_RWS_MASK

#define BISSC_RWS_MASK   0x7 /* Mask for RWS bits */

BISSC_CTRL_READ_ACCESS

#define BISSC_CTRL_READ_ACCESS   0x5 /* RWS = "101" for read access of register */

BISSC_CTRL_WRITE_ACCESS

#define BISSC_CTRL_WRITE_ACCESS   0x3 /* RWS = "011" for write access of register */

BISSC_REG_DATA_LEN

#define BISSC_REG_DATA_LEN   8 /* Number of Register data bits */

BISSC_REG_DATA_MASK

#define BISSC_REG_DATA_MASK   0xFF /* Mask for Register data */

BISSC_CTRL_STOP_LEN

#define BISSC_CTRL_STOP_LEN   2 /* Number of stop bits PS, P: stop bit for one frame, S: stop bit for sequential control communication */

BISSC_RX_SAMPLE_SIZE

#define BISSC_RX_SAMPLE_SIZE   7 /* 8x over clock */

BISSC_RX_SAMPLE_SIZE_10MHZ

#define BISSC_RX_SAMPLE_SIZE_10MHZ   3 /* 4x over clock */

BISSC_POS_CRC_LEN

#define BISSC_POS_CRC_LEN   6 /* Number of position data CRC bits */

BISSC_EW_LEN

#define BISSC_EW_LEN   2 /* Number of Error and Warning bits */

BISSC_CTRL_CMD_CRC_LEN

#define BISSC_CTRL_CMD_CRC_LEN   4 /* Number of CTRL cmd CRC bits */

BISSC_CTRL_CMD_CRC_MASK

#define BISSC_CTRL_CMD_CRC_MASK   0xF /* Mask for CTRL cmd CRC bits */

BISSC_POS_DATA_LEN_DEFAULT

#define BISSC_POS_DATA_LEN_DEFAULT   12 /* Default data length instead of garbage*/

BISSC_SAFETY_CRC_LEN

#define BISSC_SAFETY_CRC_LEN   16 /* Number of Safety CRC bits */

BISSC_RX_ENABLE_FRACTIONAL_DIV

#define BISSC_RX_ENABLE_FRACTIONAL_DIV   (1<<15) /* Enable fractional divider 1.5 for RX */

BISSC_FREQ_1MHZ

#define BISSC_FREQ_1MHZ   1

BISSC_FREQ_2MHZ

#define BISSC_FREQ_2MHZ   2

BISSC_FREQ_5MHZ

#define BISSC_FREQ_5MHZ   5

BISSC_FREQ_8MHZ

#define BISSC_FREQ_8MHZ   8

BISSC_FREQ_10MHZ

#define BISSC_FREQ_10MHZ   10