2.5. Sitara TI ESC Exceptions

TI ESC exceptions w.r.t ET1100

2.5.1. ESC register exceptions

TI ESC (EtherCAT Slave Controller) register map is fully compatible with ET1100 ASIC register map except for the registers and register fields documented below.

Note

NOTE 1: TI ESC is a 2 port EtherCAT slave and all register fields corresponding to Port2 and Port3 are NOT implemented and not mentioned in the below table.

Note

NOTE2: TI ESC does not support E-bus interface, all register fields corresponding to this functionality is NOT implemented

No ESC register Remarks
1

Write Register Enable (0x0020)

Write Register Protection (0x0021)

ESC Write Enable (0x0030)

ESC Write Protection (0x0031)

NOT implemented
2

PDI Control (0x0140)

ESC Configuration (0x0141)

PDI side access is an exception. RW access is enabled to allow loading of 0x140 and 0x141 from EEPROM ADDR: 0x0000 during RESET. TI ESC uses EEPROM emulation mode. More details here : [[1]]
3

PDI configuration (0x0150)

Sync/Latch[1:0] PDI Configuration (0x0151)

NOT loaded from EEPROM ADDR: 0x0001 during RESET. This is read only and only bit field 3 and 7 are valid i.e. SYNC0/1 mapped to AL Event Request register 0x0220.2/0x0220.3. Beckhoff is going to make proposal to ETG to make EEPROM loading of this register [0x0150:0x0153] on RESET as well as PDI side implementation ESC vendor specific
4 On-chip bus extended configuration (0x0152:0x0153) NOT implemented
5 RX Invalid Frame Counter Port 0 & 1 (0x0300 and 0x302) Too short frames (< 64 Byte) are counted by TI ESC for Port1 if both ports are connected
6 RX Error Counter of Port 0 & 1 (0x0301 and 0x303) TI ESC does not count RX_ER in MII_CLK units (counts number of frames encountered RX_ER).RX_ERs outside frame is not counted (will fix except on AM335 and AM437)
7 ECAT Processing Unit Error Counter(0x030C) Physical layer errors are not counted by TI ESC
8 0x0300, 0x0301, 0x0302, 0x0303, 0x0304, 0x0308, 0x0309, 0x30C For long frames errors, TI ESC considers frames of length > 1522B
9 PDI Error Counter (0x030D) NOT implemented
10 Lost Link Counter (0x0310: 0x0311) TI ESC counts 2 every link loss. This will be fixed (see errata for details)
11 Watchdog Divider (0x0400:0x0401) For TI ESC max value is 327.64 us or 8189 (13-bit wide and NOT 16-bit) because of 200MHz clock tick. If one programs > 13 bits, upper 3-bits are lost as firmware shifts 3-bits (25MHz clock to 200MHz clock conversion by multiplying with 8) before programming to HW register
12

Status SyncManager 0 : 0x0805.Bits4-7

Status SyncManager 1 : 0x080D.Bits4-7

Status SyncManager 2 : 0x0815.Bits4-7

Status SyncManager 3 : 0x081D.Bits4-7

Status SyncManager 4 : 0x0825.Bits4-7

Status SyncManager 5 : 0x082D.Bits4-7

Status SyncManager 6 : 0x0835.Bits4-7

Status SyncManager 7 : 0x083D.Bits4-7

Following Bits are NOT implemented

4-5: Buffered mode: buffer status (last written buffer)

00: 1. buffer

01: 2. buffer

10: 3. buffer

11: (no buffer written)

Mailbox mode: reserved

6: Read buffer in use (opened)

7: Write buffer in use (opened)

13

Activate SyncManager 0 : 0x806.Bits6-7

Activate SyncManager 1 : 0x80E.Bits6-7

Activate SyncManager 2 : 0x816.Bits6-7

Activate SyncManager 3 : 0x81E.Bits6-7

Activate SyncManager 4 : 0x826.Bits6-7

Activate SyncManager 5 : 0x82E.Bits6-7

Activate SyncManager 6 : 0x836.Bits6-7

Activate SyncManager 7 : 0x83E.Bits6-7

Following Bits are NOT implemented

6: Latch Event ECAT

1: Generate Latch event if EtherCAT master issues a buffer exchange

7: Latch Event PDI

1: Generate Latch events if PDI issues a buffer exchange or if PDI accesses buffer start address

14 Start Time Cyclic Operation (0x0990:0x0997) System time of next pulse register (0x990:0x993) is not updated instantaneous ly, resulting in read of incorrect value if read immediately after sync pulse
15

Latch0 Status (0x09AE).Bit2

Latch1 Status (0x09AF).Bit2

Following Bit is not implemented 2: Latch0/1 pin state
16

EtherCAT Buffer Change Event Time (0x09F0:0x09F3)

PDI Buffer Start Event Time (0x09F8:0x09FB)

PDI Buffer Change Event Time (0x09FC:0x09FF)

NOT implemented
17 Digital Outputs (0x0F00:0x0F03) Digital Outputs are updated at the end of an EtherCAT frame which triggered the Process Data Watchdog in ET1100 with typical SyncManager configuration: a frame containing a write access to at least one of the registers 0x0F00:0x0F03. TI ESC firmware requires SyncManager address to be higher than or equal to 0x1000.

2.5.2. Known issues with no plans to fix

No Issue Description Description
1 SDOCM00092510: Single datagram accessing multiple FMMU mapped areas using LRD/LWR commands from a single slave Increased codememory requirements needed in firmware to implement this support. LRW command supports this which is more optimal with lower framing overhead... Minor use case impact as more optimal solutions exists. May cause interop issues with certain masters if 8 SM is supported by slave and all of them are accessed via single logical datagram
2 SDOCM00098105: PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled using EtherCAT master Whenever EtherCAT master disables WD by writing zero to respective Watchdog Time registers (0x0410:0x0411 or 0x0420:0x0421). ICSS h/w limitation, can potentially workaround in firmware by maintaining this counter in firmware but require additional instructions. This has very minor use case impact to undertake this.
3 SDOCM00098950: LRD access on unused registers results in WKC increment Firmware does not support register protection in LRD mode at this moment, it requires more firmware footprint to support, this minor spec compliance does not justify the footprint increase and there are no Write Only registers in ESC. LRD access to unused register is not a practical use case…
4 SDOCM00105048: LRW access to non-interleaved input and output process data of multiple slaves does not work

Conditions in which failures occur Single LRW datagram accessing FMMU mapped areas in multiple slaves and PD out is mapped

FMMU0(0x1000:0x1007)-> SM2#1(Write SM)

FMMU1(0x1008:0x100F)->SM 2#2(Write SM)

FMMU2(0x1010:0x1017)->SM 3#1(Read SM)

FMMU3(0x1018:0x101F)->SM 3#2(Read SM)

Single LRW access from (0x1000:101F)

Rootcause Pointer management is optimized for interleaved access as well as non-interleaved access I/O data is not a very optimal use of EtherCAT – it increases the cycle time overhead/datagram size and not effective use of LRW datagram which can perform read and write in the same cycle.

Work around Use LRD/LWR datagram to access process data Use LRW datagram to access process data Input and output overlaid on the same logical address range (TwinCAT usage)

Input and output of a given slave back to back in logical address space

FMMU0(0x1000:0x1007)->SM 2 #1(Write SM)

FMMU1(0x1008:0x100F)->SM 3#1 (Read SM)

FMMU2 (0x1010:0x1017)->SM2 #2 (Write SM)

FMMU3(0x1018:0x101F)->SM 3#2(Read SM)

2.5.3. Known functional differences

No Functional Difference Description
1 Increased ProcessPath latency

There are certain scenarios under which TI ESC require increased process path latency – TIESC_PORT0/1_TX_DELA Y is programmable via tiescbsp.h or Program 0x0E10 and 0x0E12 registers in TI ESC from master and re-connect cable to one of the ports

  1. LRW [SM2 SM3] [SM4 SM5] [SM6 SM7]

  2. LRW [SM2 SM3] [SM4 SM5]

  3. LRW[SM2 ↑SM3] when LSA SM2 != LSA SM3

    [LSA : logical start address] - Overhead per frame is much higher than case a) below as datagram length is length SM2+ length SM3 compared to Max (length SM2, length SM3) which will increase the cycle time as number of slaves grow

Following scenarios work well with latency 0x48 => 360ns

  1. LRW [SM2 SM3] LSA SM2 == LSA SM3
  2. LRD[SM3]LWR[SM2]
  3. LRW 1 [SM2 SM3] LRW 2 [SM4 SM5] LRW 3 [SM6 SM7]
2 Enhanced link detection using RX_ERR and PHY does not support fast link detection RX_ERR detection is valid only during inside frame. This may not be as reliable as ET1100 which supports RX_ERR detection outside frame.
3 APRW/FPRW/BRW for SM mapped process data memory This is not a valid use as RW access to SM mapped area does not make sense