Software Phase Locked Loop (SPLL)

Table of Contents

• Introduction
• Features Supported
• Features Not Supported
• Benchmark Results
• Provided Examples
• Additional References
• API

Introduction

SPLL_1PH_NOTCH: The Software Phase Lock Loop for Single Phase Grid with NOTCH filter (SPLL_1PH_NOTCH) API provides a set of functions that calculate the instantaneous phase of a single phase grid. It also computes the sine and cosine values of the grid that can then be used in the closed loop control.

SPLL_1PH_SOGI: The Orthogonal Signal Generator SPLL for Software Phase Grid (SPLL_1PH_SOGI) API provides a set of functions that implements a software phase lock loop based on orthogonal signal generation using second order generalized integrators. This block can be further used in P and Q style control for single phase grid connected equipment.

SPLL_1PH_SOGI_FLL: The SPLL_1PH_SOGI_FLL API provides a set of functions that implements a software phase lock loop based on orthogonal signal generation using second order generalized integrators and frequency locked loop.

SPLL_3PH_DDSRF: The Software Phase Lock Loop based on decoupled double synchronous reference frame (SPLL_3PH_DDSRF) API provides a set of functions that implements a software phase lock loop based on based on decoupled double synchronous reference frame for grid connection to three phase grid.

SPLL_3PH_SRF: The Software Phase Lock Loop based on synchronous reference frame (SPLL_3PH_SRF) API provides a set of functions that implements a software phase lock loop based on based on synchronous reference frame for grid connection to three phase grid.

Features Supported

SPLL module includes:

• Calculates instantaneous phase of a grid.
• Computes the sine and cosine values of the grid that can be used in the closed loop control.

Features Not Supported

N/A

Benchmark Results

A benchmark on R5F core has been conducted on to observe the following results when running the following functions:

SPLL Function	Cpu Cycles
SPLL_1PH_SOGI
SPLL_1PH_SOGI_reset	406
SPLL_1PH_SOGI_config	40
SPLL_1PH_SOGI_run	335
SPLL_1PH_SOGI_FLL
SPLL_1PH_SOGI_FLL_reset	408
SPLL_1PH_SOGI_FLL_config	42
SPLL_1PH_SOGI_FLL_run	449
SPLL_1PH_NOTCH
SPLL_1PH_NOTCH_reset	275
SPLL_1PH_NOTCH_config	32
SPLL_1PH_NOTCH_run	376

• Ran with TI Clang Compiler v3.2.1.LTS, with -Os flag and functions force-inlined onto the benchmarking function. Obtained the average result from 500 consecutive loops of running spll_1ph_sogi functions with DPL CycleCountP, mimicking the usage of a control loop.
• Actual result may vary depending on provided datasets and memory configuration. For R5F, it is recommended for users to map control loops to TCM for the best performance.

Provided Examples

The following examples has been provided to demonstrate SPLL_1PH_SOGI functionality of SPLL module:

• Software PLL Library Test

Additional References

N/A

API

APIs for Software Phase Locked Loop Library