4.3. CDD DMA Module
4.3.1. Acronyms and Definitions
Abbreviation/Term |
Explanation |
|---|---|
AUTOSAR |
Automotive Open System Architecture |
BSW |
Basic Software |
DET |
Default Error Tracer |
CDD |
Complex Device Driver |
DMA |
Direct Memory Access |
ISR |
Interrupt Service Routine |
INT |
Interrupt |
HW |
Hardware |
SW |
Software |
MCU |
Micro Controller Unit |
OS |
Operating System |
API |
Application Programming Interface |
4.3.2. Introduction
This document describes the functionality and configuration of the Cdd_Dma module.
Supported AUTOSAR Release |
4.3.1 |
|---|---|
Supported Configuration Variants |
Pre-Compile |
Vendor ID |
DMA_VENDOR_ID (44) |
Module ID |
DMA_MODULE_ID (255) |
Supported Platform |
AM263Px |
The Cdd_Dma module initiates memory transfer without the intervention of the CPU and used in data transfer within peripheral, based on DMA channel configured.
4.3.3. Functional Overview
Cdd_Dma Driver using HW IP “EDMA”(Enhanced DMA). EDMA performs high-performance data transfer between two target endpoints, memories and peripheral devices without microcontroller support during transfer. EDMA transfer is programmed through a logical EDMA channel which allows the transfer to be optimally tailored to the requirements of the application.
The EDMA controller is based on two major principal blocks:
• EDMA third-party channel controller (EDMA_TPCC)
• EDMA third-party transfer controller (EDMA_TPTC)
Fig. 4.24 Basic Working Principle
The TPCC is a high flexible channel controller that serves as both a user interface and an event interface for the EDMA controller. The EDMA_TPCC serves to prioritize incoming software requests or events from peripherals, and submits transfer requests (TRs) to the transfer controller.
The TPTC performs read and write transfers by EDMA ports to the target peripherals, as programmed in the Active and Pending set of the registers. The transfer controllers are responsible for data movement, and issue read/write commands to the source and destination addresses programmed for a given transfer in the EDMA_TPCC.
The Cdd_Dma module has 64 EDMA channels, which serves the purpose of driving transferring of data.
4.3.3.1. Initialization
Cdd_Dma_Init() has to be called to initialize the Cdd_Dma driver.
4.3.3.2. States
None
4.3.3.3. Assumptions
None
4.3.3.4. Limitations
Below are the IP’s that needed software workaround with EDMA because of the HW Limitations -
UART : A dummy PaRAM needs to be linked to the actual TX PaRAM. This is because UART generates TX empty event after the last character is transferred and it results in an event miss error being set in EDMA (since the TX PaRAM has already been used up for the transfer). A dummy PaRAM set is linked to the actual TX PaRAM to service the extra event generated.
McSpi : Above scenario also applies to McSPI. A dummy PaRAM set is linked to solve the issue.
NOTE: Both of these above limitations are taken care internally by UART and McSpi driver respectively.
4.3.3.5. Design overview
Will be updated in future release
4.3.4. Hardware Features
4.3.4.1. IP Supported Features
EDMA channels are supported.
Both memory transfer and transfer within peripheral is supported.
Both interrupt mode and polling mode are supported.
Linking of multiple params are supported.
Chaining of multiple channels are supported.
4.3.4.2. Not supported Features
QDMA is not supported.
4.3.4.3. Non compliance
4.3.4.3.1. Deviations to requirements (Requirement Traceability)
4.3.4.3.1.1. Deviation of requirements against AUTOSAR specification requirements
None
4.3.5. Source files
Static source C Files are defined below
📦AM263Px
┣ 📂build
┣ 📂mcal
┃ ┣ 📂Dma
┃ ┃ ┣ 📂include
┃ ┃ ┃ ┣ 📜Cdd_Dma.h : Contains the API’s of the Cdd_Dma driver to be used by upper layers.
┃ ┃ ┃ ┣ 📜Cdd_Dma_cslr_tpcc.h : Contains Internal functions definition and initialization of Cdd_Dma driver.
┃ ┃ ┃ ┣ 📜Cdd_Dma_cslr_tptc.h : Contains Internal functions definition and initialization of Cdd_Dma driver.
┃ ┃ ┃ ┣ 📜Cdd_Dma_edma.h : Contains Internal functions definition and initialization of Cdd_Dma driver.
┃ ┃ ┃ ┣ 📜Cdd_Dma_Irq.h : Contains ISR function declaration.
┃ ┃ ┃ ┗ 📜Cdd_Dma_Priv.h : Contains Internal functions definition and initialization of Cdd_Dma driver.
┃ ┃ ┣ 📂src
┃ ┃ ┃ ┣ 📜Cdd_Dma.c : Contains the implementation of the API’s for Cdd_Dma driver.
┃ ┃ ┃ ┣ 📜Cdd_Dma_Irq.c : Contains ISR function definitions.
┃ ┃ ┃ ┗ 📜Cdd_Dma_Priv.c : Contains Internal functions definition and initialization of Cdd_Dma driver.
┃ ┃ ┣ 📂V0
┃ ┃ ┃ ┗ 📜Cdd_Dma_dmaxbar.h : Contains DMA cross bar interrupt information.
┃ ┃ ┃ ┣ 📜Cdd_Dma_soc.c : Contains device specific a function definition, data types and definitions.
┃ ┃ ┃ ┗ 📜Cdd_Dma_trig_xbar.h : Contains DMA cross bar interrupt information.
┃ ┃ ┃ ┣ 📜Cdd_Dma_xbar.h : Contains DMA cross bar interrupt information.
┃ ┃ ┗ 📜Makefile
┃ 📂mcal_config
┃ 📂mcal_docs
┃ 📜README.txt
Plugin files are defined below in the table.
Plugin Files |
Description |
|---|---|
CDD_Dma_Cfg.h |
Contains the Precompile switches, Symbolic names of the handles and xbar, HW units |
CDD_Dma_Cfg.c |
contains the configuration parameters |
4.3.6. Module requirements
Please refer Software Product Specification document provided as part of CSP.
4.3.6.1. Memory Mapping
Memory Mapping Sections |
CDD_DMA_CODE |
CDD_DMA_CODE_ISR |
CDD_DMA_VAR_NO_INIT |
CDD_DMA_VAR |
CDD_DMA_CFG |
|---|---|---|---|---|---|
CDD_DMA_START_SEC_VAR_INIT_8 (.bss) |
x |
||||
CDD_DMA_STOP_SEC_VAR_INIT_8 |
x |
||||
CDD_DMA_START_SEC_CONFIG_DATA (.const) |
x |
||||
CDD_DMA_STOP_SEC_CONFIG_DATA |
x |
||||
CDD_DMA_START_SEC_CODE (.text) |
x |
||||
CDD_DMA_STOP_SEC_CODE |
x |
||||
CDD_DMA_START_SEC_VAR_INIT_32 (.bss) |
x |
||||
CDD_DMA_STOP_SEC_VAR_INIT_32 |
x |
||||
CDD_DMA_START_SEC_VAR_NO_INIT_UNSPECIFIED (.data) |
x |
||||
CDD_DMA_STOP_SEC_VAR_NO_INIT_UNSPECIFIED |
x |
||||
CDD_DMA_START_SEC_ISR_CODE |
x |
||||
CDD_DMA_STOP_SEC_ISR_CODE |
x |
4.3.6.2. Scheduling
4.3.6.2.1. SchM (Optional)
Beside the OS the BSW Scheduler provides functions that module Cdd_Dma calls at begin and end of critical sections.
4.3.6.2.2. Critical Sections
There is only one kind of critical sections in this driver. Within these sections all read /modify / write accesses to internal Cdd_Dma driver data structures must be protected. Therefore, switching to tasks that also access Cdd_Dma has to be avoided and all Cdd_Dma interrupts have to be suspended. This is handled internally by Cdd_Dma Driver.
4.3.6.3. Error handling
4.3.6.3.1. Development Error Reporting (DET)
In development mode, the Cdd_Dma module reports development error through the Det_ReportError function of module DET. The errors reported to DET are described in the following table
Type of Error |
Related Error code |
Value (Hex) |
|---|---|---|
API service called without module initialization. |
CDD_DMA_E_UNINIT |
0x01 |
API service for initialization is called when already initialized. |
CDD_DMA_E_ALREADY_INITIALIZED |
0x02 |
API parameter checking: invalid value. |
CDD_DMA_E_PARAM_VALUE |
0x03 |
API parameter checking: invalid pointer. |
CDD_DMA_E_PARAM_POINTER |
0x04 |
API service for indicating callback is already registered |
CDD_DMA_E_ALREADY_REGISTERED |
0x05 |
API service for indicating DMA handle already in use |
CDD_DMA_E_ALREADY_IN_PROGRESS |
0x06 |
4.3.6.3.2. Runtime Errors
None
4.3.7. Used resources
4.3.7.1. Interrupt Handling
Cdd_Dma driver provides ISR for transfer completion detection. The interrupt category must be configured in Cdd_Dma Driver and OS modules.
Respective ISR for each Cdd_Dma Instance in AM263Px are as follows:
Cdd_Dma Instances |
ISR Routines |
|---|---|
CDD_DMA_MSS_A |
CDD_EDMA_lld_transferCompletionMasterIsrFxn() |
CDD_DMA_MSS_A instance of Cdd_Dma has interrupt number as “72” in AM263Px.
4.3.8. Integration description
4.3.8.1. Dependent modules
4.3.8.1.1. MCU
The module MCU powers up the microcontroller’s peripherals at startup time and initializes the PLL as well as the internal clock domains which is connected to the Cdd_Dma unit.
The Cdd_Dma module will not take care of settings which configure the clock and PLL for channels in its init function. This must be done by the MCU module.
4.3.8.1.2. PORT
The Port driver configures the port pins used for the Cdd_Dma driver as input or output. Hence, the Port driver has to be initialized prior to the use of Cdd_Dma functions. Otherwise, Cdd_Dma driver functions will exhibit undefined behavior.
4.3.8.1.3. OS
An operating system can be used for task scheduling, interrupt handling, global suspend and restore of interrupts and creating of the Interrupt Vector Table.The Cdd_Dma module may use AUTOSAR OS to suspend and restore global interrupts.
4.3.8.1.4. DET
The module PWM depends on the DET (by default) in order to report development errors.
4.3.8.1.5. DEM
None
4.3.8.1.6. Callback Functions
None
4.3.8.1.7. Callback Notification
None
4.3.8.2. Multi-core and Resource allocator
Will be updated in the next release
4.3.9. Configuration
The Cdd_Dma can be configured as Pre-Compile variant, using EB tresos tool.
Variants |
Configured Files |
|---|---|
Pre-Compile |
Cdd_Dma_Cfg.c , Cdd_Dma_Cfg.h |
4.3.9.1. Parameter Description
Standard Parameters |
Description |
Default Value |
Range |
Unit/Datatype |
|---|---|---|---|---|
Config Variant |
Parameter used to configure the variant of the module. |
Pre-Compile |
Pre-Compile |
ENUMERATION |
CddDmaVersionInfoApi |
Macro to enable or disable the version info |
TRUE |
TRUE FALSE |
BOOLEAN |
CddDmaDeinitApi |
Macro to enable or disable the DeInit Api |
TRUE |
TRUE FALSE |
BOOLEAN |
CddDmaDevErrorDetect |
Macro to enable or disable the Development error detection |
TRUE |
TRUE FALSE |
BOOLEAN |
CddDmaIrqType |
Parameter specifies the category of Interrupt Request. |
CDD_DMA_ISR_VOID |
CDD_DMA_ISR_VOID CDD_DMA_ISR_CAT1 CDD_DMA_ISR_CAT2 |
ENUMERATION |
CddDmaTransferType |
Parameter denote the type of transfer either this is memory transfer or peripheral based and even in peripheral based which peripheral is using Dma is decided by this field. |
CDD_DMA_TRANSFER_TYPE_MEMORY_TRANSFER |
CDD_DMA_TRANSFER_TYPE_MEMORY_TRANSFER CDD_DMA_TRANSFER_TYPE_UART_TX CDD_DMA_TRANSFER_TYPE_UART_RX CDD_DMA_TRANSFER_TYPE_ADC CDD_DMA_TRANSFER_TYPE_MC_SPI |
ENUMERATION |
CddDmaInstance |
Parameter to select the Dma instance which we want to use. |
CDD_DMA_MSS_A |
CDD_DMA_MSS_A |
ENUMERATION |
CddDmaRegionID |
There are several dma regions and according to the region selected DMA resources(DMA channels and interrupts) that are assigned to the region can be used by EDMA programmer. |
0 |
0 to 7 |
INTEGER |
CddDmaTccNumber |
Tcc field is linked to the logical channel and whenever that channel is involved in the transmission we can see the completion status for that channel based on the Tcc number. |
0 |
0 to 63 |
INTEGER |
CddDmaQueueNumber |
Queue number correspond to the priority of the transfer.Lower the number higher the priority. |
0 |
0 to 1 |
INTEGER |
CddDmaEnableInterrupt |
Parameter to enable or disable the interrupt mode |
TRUE |
TRUE FALSE |
BOOLEAN |
CddDmaTransferModeSelect |
In Cdd_Dma we are supporting multiple transfer mode like linking (used in case linking params) chaining(used in chaining channels)and nomal mode. |
CDD_DMA_TRANSFER_MODE_NORMAL |
CDD_DMA_TRANSFER_MODE_NORMAL CDD_DMA_TRANSFER_MODE_LINKING CDD_DMA_TRANSFER_MODE_CHAINING |
ENUMERATION |
CddDmaChannel |
In a particular handle we have channel group and within this we have channel number(logical channel) we can assign channel number which will be linked to the handle.In case of chaining multiple channels can be configured. |
0 |
0 to 63 |
INTEGER |
CddDmaParamNumber |
For a particular channel group we can have multiple params so param number is assigned at channel level and each param has dedicated paramSet which contains transfer parameters. |
0 |
0 to 255 |
INTEGER |
CddDmaDmaChannelModule |
The DMA channel selected for module |
CDD_DMA_TRIG_XBAR_EDMA_MODULE_0 |
CDD_DMA_TRIG_XBAR_EDMA_MODULE_0 CDD_DMA_TRIG_XBAR_EDMA_MODULE_1 CDD_DMA_TRIG_XBAR_EDMA_MODULE_2 CDD_DMA_TRIG_XBAR_EDMA_MODULE_3 CDD_DMA_TRIG_XBAR_EDMA_MODULE_4 CDD_DMA_TRIG_XBAR_EDMA_MODULE_5 CDD_DMA_TRIG_XBAR_EDMA_MODULE_6 CDD_DMA_TRIG_XBAR_EDMA_MODULE_7 CDD_DMA_TRIG_XBAR_EDMA_MODULE_8 CDD_DMA_TRIG_XBAR_EDMA_MODULE_9 CDD_DMA_TRIG_XBAR_EDMA_MODULE_10 CDD_DMA_TRIG_XBAR_EDMA_MODULE_11 CDD_DMA_TRIG_XBAR_EDMA_MODULE_12 CDD_DMA_TRIG_XBAR_EDMA_MODULE_13 CDD_DMA_TRIG_XBAR_EDMA_MODULE_14 CDD_DMA_TRIG_XBAR_EDMA_MODULE_15 CDD_DMA_TRIG_XBAR_EDMA_MODULE_16 CDD_DMA_TRIG_XBAR_EDMA_MODULE_17 CDD_DMA_TRIG_XBAR_EDMA_MODULE_18 CDD_DMA_TRIG_XBAR_EDMA_MODULE_19 CDD_DMA_TRIG_XBAR_EDMA_MODULE_20 CDD_DMA_TRIG_XBAR_EDMA_MODULE_21 CDD_DMA_TRIG_XBAR_EDMA_MODULE_22 CDD_DMA_TRIG_XBAR_EDMA_MODULE_23 CDD_DMA_TRIG_XBAR_EDMA_MODULE_24 CDD_DMA_TRIG_XBAR_EDMA_MODULE_25 CDD_DMA_TRIG_XBAR_EDMA_MODULE_26 CDD_DMA_TRIG_XBAR_EDMA_MODULE_27 CDD_DMA_TRIG_XBAR_EDMA_MODULE_28 CDD_DMA_TRIG_XBAR_EDMA_MODULE_29 CDD_DMA_TRIG_XBAR_EDMA_MODULE_30 CDD_DMA_TRIG_XBAR_EDMA_MODULE_31 CDD_DMA_TRIG_XBAR_EDMA_MODULE_32 CDD_DMA_TRIG_XBAR_EDMA_MODULE_33 CDD_DMA_TRIG_XBAR_EDMA_MODULE_34 CDD_DMA_TRIG_XBAR_EDMA_MODULE_35 CDD_DMA_TRIG_XBAR_EDMA_MODULE_36 CDD_DMA_TRIG_XBAR_EDMA_MODULE_37 CDD_DMA_TRIG_XBAR_EDMA_MODULE_38 CDD_DMA_TRIG_XBAR_EDMA_MODULE_39 CDD_DMA_TRIG_XBAR_EDMA_MODULE_40 CDD_DMA_TRIG_XBAR_EDMA_MODULE_41 CDD_DMA_TRIG_XBAR_EDMA_MODULE_42 CDD_DMA_TRIG_XBAR_EDMA_MODULE_43 CDD_DMA_TRIG_XBAR_EDMA_MODULE_44 CDD_DMA_TRIG_XBAR_EDMA_MODULE_45 CDD_DMA_TRIG_XBAR_EDMA_MODULE_46 CDD_DMA_TRIG_XBAR_EDMA_MODULE_47 CDD_DMA_TRIG_XBAR_EDMA_MODULE_48 CDD_DMA_TRIG_XBAR_EDMA_MODULE_49 CDD_DMA_TRIG_XBAR_EDMA_MODULE_50 CDD_DMA_TRIG_XBAR_EDMA_MODULE_51 CDD_DMA_TRIG_XBAR_EDMA_MODULE_52 CDD_DMA_TRIG_XBAR_EDMA_MODULE_53 CDD_DMA_TRIG_XBAR_EDMA_MODULE_54 CDD_DMA_TRIG_XBAR_EDMA_MODULE_55 CDD_DMA_TRIG_XBAR_EDMA_MODULE_56 CDD_DMA_TRIG_XBAR_EDMA_MODULE_57 CDD_DMA_TRIG_XBAR_EDMA_MODULE_58 CDD_DMA_TRIG_XBAR_EDMA_MODULE_59 CDD_DMA_TRIG_XBAR_EDMA_MODULE_60 CDD_DMA_TRIG_XBAR_EDMA_MODULE_61 CDD_DMA_TRIG_XBAR_EDMA_MODULE_62 CDD_DMA_TRIG_XBAR_EDMA_MODULE_63 |
ENUMERATION |
CddDmaChannelTriggerSource |
Source to Trigger DMA Channel |
CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_0 |
CDD_DMA_TRIG_XBAR_LIN0_RXDMA CDD_DMA_TRIG_XBAR_LIN0_TXDMA CDD_DMA_TRIG_XBAR_LIN1_RXDMA CDD_DMA_TRIG_XBAR_LIN1_TXDMA CDD_DMA_TRIG_XBAR_LIN2_RXDMA CDD_DMA_TRIG_XBAR_LIN2_TXDMA CDD_DMA_TRIG_XBAR_LIN3_RXDMA CDD_DMA_TRIG_XBAR_LIN3_TXDMA CDD_DMA_TRIG_XBAR_LIN4_RXDMA CDD_DMA_TRIG_XBAR_LIN4_TXDMA CDD_DMA_TRIG_XBAR_I2C0_TX CDD_DMA_TRIG_XBAR_I2C0_RX CDD_DMA_TRIG_XBAR_I2C1_TX CDD_DMA_TRIG_XBAR_I2C1_RX CDD_DMA_TRIG_XBAR_I2C2_TX CDD_DMA_TRIG_XBAR_I2C2_RX CDD_DMA_TRIG_XBAR_I2C3_TX CDD_DMA_TRIG_XBAR_I2C3_RX CDD_DMA_TRIG_XBAR_SPI0_DMA_READ_REQ0 CDD_DMA_TRIG_XBAR_SPI0_DMA_READ_REQ1 CDD_DMA_TRIG_XBAR_SPI0_DMA_READ_REQ2 CDD_DMA_TRIG_XBAR_SPI0_DMA_READ_REQ3 CDD_DMA_TRIG_XBAR_SPI0_DMA_WRITE_REQ0 CDD_DMA_TRIG_XBAR_SPI0_DMA_WRITE_REQ1 CDD_DMA_TRIG_XBAR_SPI0_DMA_WRITE_REQ2 CDD_DMA_TRIG_XBAR_SPI0_DMA_WRITE_REQ3 CDD_DMA_TRIG_XBAR_SPI1_DMA_READ_REQ0 CDD_DMA_TRIG_XBAR_SPI1_DMA_READ_REQ1 CDD_DMA_TRIG_XBAR_SPI1_DMA_READ_REQ2 CDD_DMA_TRIG_XBAR_SPI1_DMA_READ_REQ3 CDD_DMA_TRIG_XBAR_SPI1_DMA_WRITE_REQ0 CDD_DMA_TRIG_XBAR_SPI1_DMA_WRITE_REQ1 CDD_DMA_TRIG_XBAR_SPI1_DMA_WRITE_REQ2 CDD_DMA_TRIG_XBAR_SPI1_DMA_WRITE_REQ3 CDD_DMA_TRIG_XBAR_SPI2_DMA_READ_REQ0 CDD_DMA_TRIG_XBAR_SPI2_DMA_READ_REQ1 CDD_DMA_TRIG_XBAR_SPI2_DMA_READ_REQ2 CDD_DMA_TRIG_XBAR_SPI2_DMA_READ_REQ3 CDD_DMA_TRIG_XBAR_SPI2_DMA_WRITE_REQ0 CDD_DMA_TRIG_XBAR_SPI2_DMA_WRITE_REQ1 CDD_DMA_TRIG_XBAR_SPI2_DMA_WRITE_REQ2 CDD_DMA_TRIG_XBAR_SPI2_DMA_WRITE_REQ3 CDD_DMA_TRIG_XBAR_SPI3_DMA_READ_REQ0 CDD_DMA_TRIG_XBAR_SPI3_DMA_READ_REQ1 CDD_DMA_TRIG_XBAR_SPI3_DMA_READ_REQ2 CDD_DMA_TRIG_XBAR_SPI3_DMA_READ_REQ3 CDD_DMA_TRIG_XBAR_SPI3_DMA_WRITE_REQ0 CDD_DMA_TRIG_XBAR_SPI3_DMA_WRITE_REQ1 CDD_DMA_TRIG_XBAR_SPI3_DMA_WRITE_REQ2 CDD_DMA_TRIG_XBAR_SPI3_DMA_WRITE_REQ3 CDD_DMA_TRIG_XBAR_SPI4_DMA_READ_REQ0 CDD_DMA_TRIG_XBAR_SPI4_DMA_READ_REQ1 CDD_DMA_TRIG_XBAR_SPI4_DMA_READ_REQ2 CDD_DMA_TRIG_XBAR_SPI4_DMA_READ_REQ3 CDD_DMA_TRIG_XBAR_SPI4_DMA_WRITE_REQ0 CDD_DMA_TRIG_XBAR_SPI4_DMA_WRITE_REQ1 CDD_DMA_TRIG_XBAR_SPI4_DMA_WRITE_REQ2 CDD_DMA_TRIG_XBAR_SPI4_DMA_WRITE_REQ3 CDD_DMA_TRIG_XBAR_RTI0_DMA_0 CDD_DMA_TRIG_XBAR_RTI0_DMA_1 CDD_DMA_TRIG_XBAR_RTI0_DMA_2 CDD_DMA_TRIG_XBAR_RTI0_DMA_3 CDD_DMA_TRIG_XBAR_RTI1_DMA_0 CDD_DMA_TRIG_XBAR_RTI1_DMA_1 CDD_DMA_TRIG_XBAR_RTI1_DMA_2 CDD_DMA_TRIG_XBAR_RTI1_DMA_3 CDD_DMA_TRIG_XBAR_RTI2_DMA_0 CDD_DMA_TRIG_XBAR_RTI2_DMA_1 CDD_DMA_TRIG_XBAR_RTI2_DMA_2 CDD_DMA_TRIG_XBAR_RTI2_DMA_3 CDD_DMA_TRIG_XBAR_RTI3_DMA_0 CDD_DMA_TRIG_XBAR_RTI3_DMA_1 CDD_DMA_TRIG_XBAR_RTI3_DMA_2 CDD_DMA_TRIG_XBAR_RTI3_DMA_3 CDD_DMA_TRIG_XBAR_MCANSS0_TX_DMA_0 CDD_DMA_TRIG_XBAR_MCANSS0_TX_DMA_1 CDD_DMA_TRIG_XBAR_MCANSS0_TX_DMA_2 CDD_DMA_TRIG_XBAR_MCANSS0_TX_DMA_3 CDD_DMA_TRIG_XBAR_MCANSS1_TX_DMA_0 CDD_DMA_TRIG_XBAR_MCANSS1_TX_DMA_1 CDD_DMA_TRIG_XBAR_MCANSS1_TX_DMA_2 CDD_DMA_TRIG_XBAR_MCANSS1_TX_DMA_3 CDD_DMA_TRIG_XBAR_MCANSS2_TX_DMA_0 CDD_DMA_TRIG_XBAR_MCANSS2_TX_DMA_1 CDD_DMA_TRIG_XBAR_MCANSS2_TX_DMA_2 CDD_DMA_TRIG_XBAR_MCANSS2_TX_DMA_3 CDD_DMA_TRIG_XBAR_MCANSS3_TX_DMA_0 CDD_DMA_TRIG_XBAR_MCANSS3_TX_DMA_1 CDD_DMA_TRIG_XBAR_MCANSS3_TX_DMA_2 CDD_DMA_TRIG_XBAR_MCANSS3_TX_DMA_3 CDD_DMA_TRIG_XBAR_USART0_DMA_0 CDD_DMA_TRIG_XBAR_USART0_DMA_1 CDD_DMA_TRIG_XBAR_USART1_DMA_0 CDD_DMA_TRIG_XBAR_USART1_DMA_1 CDD_DMA_TRIG_XBAR_USART2_DMA_0 CDD_DMA_TRIG_XBAR_USART2_DMA_1 CDD_DMA_TRIG_XBAR_USART3_DMA_0 CDD_DMA_TRIG_XBAR_USART3_DMA_1 CDD_DMA_TRIG_XBAR_USART4_DMA_0 CDD_DMA_TRIG_XBAR_USART4_DMA_1 CDD_DMA_TRIG_XBAR_USART5_DMA_0 CDD_DMA_TRIG_XBAR_USART5_DMA_1 CDD_DMA_TRIG_XBAR_MCRC_DMA_EVENT_0 CDD_DMA_TRIG_XBAR_MCRC_DMA_EVENT_1 CDD_DMA_TRIG_XBAR_MCRC_DMA_EVENT_2 CDD_DMA_TRIG_XBAR_MCRC_DMA_EVENT_3 CDD_DMA_TRIG_XBAR_QSPI_INTR CDD_DMA_TRIG_XBAR_GPIO_INT_XBAR_OUT_0 CDD_DMA_TRIG_XBAR_GPIO_INT_XBAR_OUT_1 CDD_DMA_TRIG_XBAR_GPIO_INT_XBAR_OUT_2 CDD_DMA_TRIG_XBAR_GPIO_INT_XBAR_OUT_3 CDD_DMA_TRIG_XBAR_SOC_TIMESYNC_XBAR1_OUT_0 CDD_DMA_TRIG_XBAR_SOC_TIMESYNC_XBAR1_OUT_1 CDD_DMA_TRIG_XBAR_SOC_TIMESYNC_XBAR0_OUT_0 CDD_DMA_TRIG_XBAR_SOC_TIMESYNC_XBAR0_OUT_1 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_0 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_1 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_2 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_3 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_4 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_5 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_6 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_7 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_8 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_9 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_10 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_11 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_12 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_13 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_14 CDD_DMA_TRIG_XBAR_DMA_XBAR_OUT_15 CDD_DMA_TRIG_XBAR_MMC_DMA_RD CDD_DMA_TRIG_XBAR_MMC_DMA_WR CDD_DMA_TRIG_XBAR_DTHE_SHA_DMA_REQ0 CDD_DMA_TRIG_XBAR_DTHE_SHA_DMA_REQ1 CDD_DMA_TRIG_XBAR_DTHE_SHA_DMA_REQ2 CDD_DMA_TRIG_XBAR_DTHE_SHA_DMA_REQ3 CDD_DMA_TRIG_XBAR_DTHE_SHA_DMA_REQ4 CDD_DMA_TRIG_XBAR_DTHE_SHA_DMA_REQ5 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ0 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ1 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ2 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ3 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ4 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ5 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ6 CDD_DMA_TRIG_XBAR_DTHE_AES_DMA_REQ7 CDD_DMA_TRIG_XBAR_MCANSS0_FE_0 CDD_DMA_TRIG_XBAR_MCANSS0_FE_1 CDD_DMA_TRIG_XBAR_MCANSS0_FE_2 CDD_DMA_TRIG_XBAR_MCANSS0_FE_3 CDD_DMA_TRIG_XBAR_MCANSS0_FE_4 CDD_DMA_TRIG_XBAR_MCANSS0_FE_5 CDD_DMA_TRIG_XBAR_MCANSS0_FE_6 CDD_DMA_TRIG_XBAR_MCANSS1_FE_0 CDD_DMA_TRIG_XBAR_MCANSS1_FE_1 CDD_DMA_TRIG_XBAR_MCANSS1_FE_2 CDD_DMA_TRIG_XBAR_MCANSS1_FE_3 CDD_DMA_TRIG_XBAR_MCANSS1_FE_4 CDD_DMA_TRIG_XBAR_MCANSS1_FE_5 CDD_DMA_TRIG_XBAR_MCANSS1_FE_6 CDD_DMA_TRIG_XBAR_MCANSS2_FE_0 CDD_DMA_TRIG_XBAR_MCANSS2_FE_1 CDD_DMA_TRIG_XBAR_MCANSS2_FE_2 CDD_DMA_TRIG_XBAR_MCANSS2_FE_3 CDD_DMA_TRIG_XBAR_MCANSS2_FE_4 CDD_DMA_TRIG_XBAR_MCANSS2_FE_5 CDD_DMA_TRIG_XBAR_MCANSS2_FE_6 CDD_DMA_TRIG_XBAR_MCANSS3_FE_0 CDD_DMA_TRIG_XBAR_MCANSS3_FE_1 CDD_DMA_TRIG_XBAR_MCANSS3_FE_2 CDD_DMA_TRIG_XBAR_MCANSS3_FE_3 CDD_DMA_TRIG_XBAR_MCANSS3_FE_4 CDD_DMA_TRIG_XBAR_MCANSS3_FE_5 CDD_DMA_TRIG_XBAR_MCANSS3_FE_6 CDD_DMA_TRIG_XBAR_GPMC_SDMAREQ |
ENUMERATION |
CddDmaDmaChannelXbar |
DMA Channel Cross bar source |
CDD_DMA_XBAR_DMA_TRIG_XBAR_0 |
CDD_DMA_XBAR_DMA_TRIG_XBAR_0 CDD_DMA_XBAR_DMA_TRIG_XBAR_1 CDD_DMA_XBAR_DMA_TRIG_XBAR_2 CDD_DMA_XBAR_DMA_TRIG_XBAR_3 CDD_DMA_XBAR_DMA_TRIG_XBAR_4 CDD_DMA_XBAR_DMA_TRIG_XBAR_5 CDD_DMA_XBAR_DMA_TRIG_XBAR_6 CDD_DMA_XBAR_DMA_TRIG_XBAR_7 CDD_DMA_XBAR_DMA_TRIG_XBAR_8 CDD_DMA_XBAR_DMA_TRIG_XBAR_9 CDD_DMA_XBAR_DMA_TRIG_XBAR_10 CDD_DMA_XBAR_DMA_TRIG_XBAR_11 CDD_DMA_XBAR_DMA_TRIG_XBAR_12 CDD_DMA_XBAR_DMA_TRIG_XBAR_13 CDD_DMA_XBAR_DMA_TRIG_XBAR_14 CDD_DMA_XBAR_DMA_TRIG_XBAR_15 |
ENUMERATION |
CddDmaDmaChannelXbarMap |
DMA Channel Cross bar trigger mapping to interrupt trigger source from external modules |
CDD_DMA_XBAR_ADC0_INT1 |
CDD_DMA_XBAR_EPWM0_SOCA CDD_DMA_XBAR_EPWM1_SOCA CDD_DMA_XBAR_EPWM2_SOCA CDD_DMA_XBAR_EPWM3_SOCA CDD_DMA_XBAR_EPWM4_SOCA CDD_DMA_XBAR_EPWM5_SOCA CDD_DMA_XBAR_EPWM6_SOCA CDD_DMA_XBAR_EPWM7_SOCA CDD_DMA_XBAR_EPWM8_SOCA CDD_DMA_XBAR_EPWM9_SOCA CDD_DMA_XBAR_EPWM10_SOCA CDD_DMA_XBAR_EPWM11_SOCA CDD_DMA_XBAR_EPWM12_SOCA CDD_DMA_XBAR_EPWM13_SOCA CDD_DMA_XBAR_EPWM14_SOCA CDD_DMA_XBAR_EPWM15_SOCA CDD_DMA_XBAR_EPWM16_SOCA CDD_DMA_XBAR_EPWM17_SOCA CDD_DMA_XBAR_EPWM18_SOCA CDD_DMA_XBAR_EPWM19_SOCA CDD_DMA_XBAR_EPWM20_SOCA CDD_DMA_XBAR_EPWM21_SOCA CDD_DMA_XBAR_EPWM22_SOCA CDD_DMA_XBAR_EPWM23_SOCA CDD_DMA_XBAR_EPWM24_SOCA CDD_DMA_XBAR_EPWM25_SOCA CDD_DMA_XBAR_EPWM26_SOCA CDD_DMA_XBAR_EPWM27_SOCA CDD_DMA_XBAR_EPWM28_SOCA CDD_DMA_XBAR_EPWM29_SOCA CDD_DMA_XBAR_EPWM30_SOCA CDD_DMA_XBAR_EPWM31_SOCA CDD_DMA_XBAR_EPWM0_SOCB CDD_DMA_XBAR_EPWM1_SOCB CDD_DMA_XBAR_EPWM2_SOCB CDD_DMA_XBAR_EPWM3_SOCB CDD_DMA_XBAR_EPWM4_SOCB CDD_DMA_XBAR_EPWM5_SOCB CDD_DMA_XBAR_EPWM6_SOCB CDD_DMA_XBAR_EPWM7_SOCB CDD_DMA_XBAR_EPWM8_SOCB CDD_DMA_XBAR_EPWM9_SOCB CDD_DMA_XBAR_EPWM10_SOCB CDD_DMA_XBAR_EPWM11_SOCB CDD_DMA_XBAR_EPWM12_SOCB CDD_DMA_XBAR_EPWM13_SOCB CDD_DMA_XBAR_EPWM14_SOCB CDD_DMA_XBAR_EPWM15_SOCB CDD_DMA_XBAR_EPWM16_SOCB CDD_DMA_XBAR_EPWM17_SOCB CDD_DMA_XBAR_EPWM18_SOCB CDD_DMA_XBAR_EPWM19_SOCB CDD_DMA_XBAR_EPWM20_SOCB CDD_DMA_XBAR_EPWM21_SOCB CDD_DMA_XBAR_EPWM22_SOCB CDD_DMA_XBAR_EPWM23_SOCB CDD_DMA_XBAR_EPWM24_SOCB CDD_DMA_XBAR_EPWM25_SOCB CDD_DMA_XBAR_EPWM26_SOCB CDD_DMA_XBAR_EPWM27_SOCB CDD_DMA_XBAR_EPWM28_SOCB CDD_DMA_XBAR_EPWM29_SOCB CDD_DMA_XBAR_EPWM30_SOCB CDD_DMA_XBAR_EPWM31_SOCB CDD_DMA_XBAR_ADC0_INT1 CDD_DMA_XBAR_ADC0_INT2 CDD_DMA_XBAR_ADC0_INT3 CDD_DMA_XBAR_ADC0_INT4 CDD_DMA_XBAR_ADC0_EVTINT CDD_DMA_XBAR_ADC1_INT1 CDD_DMA_XBAR_ADC1_INT2 CDD_DMA_XBAR_ADC1_INT3 CDD_DMA_XBAR_ADC1_INT4 CDD_DMA_XBAR_ADC1_EVTINT CDD_DMA_XBAR_ADC2_INT1 CDD_DMA_XBAR_ADC2_INT2 CDD_DMA_XBAR_ADC2_INT3 CDD_DMA_XBAR_ADC2_INT4 CDD_DMA_XBAR_ADC2_EVTINT CDD_DMA_XBAR_ADC3_INT1 CDD_DMA_XBAR_ADC3_INT2 CDD_DMA_XBAR_ADC3_INT3 CDD_DMA_XBAR_ADC3_INT4 CDD_DMA_XBAR_ADC3_EVTINT CDD_DMA_XBAR_ADC4_INT1 CDD_DMA_XBAR_ADC4_INT2 CDD_DMA_XBAR_ADC4_INT3 CDD_DMA_XBAR_ADC4_INT4 CDD_DMA_XBAR_ADC4_EVTINT CDD_DMA_XBAR_FSI0_RX_DMA_EVT CDD_DMA_XBAR_FSI0_DMA_TRIG1 CDD_DMA_XBAR_FSI0_DMA_TRIG2 CDD_DMA_XBAR_FSI1_RX_DMA_EVT CDD_DMA_XBAR_FSI1_DMA_TRIG1 CDD_DMA_XBAR_FSI1_DMA_TRIG2 CDD_DMA_XBAR_FSI2_RX_DMA_EVT CDD_DMA_XBAR_FSI2_DMA_TRIG1 CDD_DMA_XBAR_FSI2_DMA_TRIG2 CDD_DMA_XBAR_FSI3_RX_DMA_EVT CDD_DMA_XBAR_FSI3_DMA_TRIG1 CDD_DMA_XBAR_FSI3_DMA_TRIG2 CDD_DMA_XBAR_FSI0_TX_DMA_EVT CDD_DMA_XBAR_FSI1_TX_DMA_EVT CDD_DMA_XBAR_FSI2_TX_DMA_EVT CDD_DMA_XBAR_FSI3_TX_DMA_EVT CDD_DMA_XBAR_SD0_FILT0_DRINT CDD_DMA_XBAR_SD0_FILT1_DRINT CDD_DMA_XBAR_SD0_FILT2_DRINT CDD_DMA_XBAR_SD0_FILT3_DRINT CDD_DMA_XBAR_SD1_FILT0_DRINT CDD_DMA_XBAR_SD1_FILT1_DRINT CDD_DMA_XBAR_SD1_FILT2_DRINT CDD_DMA_XBAR_SD1_FILT3_DRINT CDD_DMA_XBAR_ECAP0_DMA_INT CDD_DMA_XBAR_ECAP1_DMA_INT CDD_DMA_XBAR_ECAP2_DMA_INT CDD_DMA_XBAR_ECAP3_DMA_INT CDD_DMA_XBAR_ECAP4_DMA_INT CDD_DMA_XBAR_ECAP5_DMA_INT CDD_DMA_XBAR_ECAP6_DMA_INT CDD_DMA_XBAR_ECAP7_DMA_INT CDD_DMA_XBAR_ECAP8_DMA_INT CDD_DMA_XBAR_ECAP9_DMA_INT |
ENUMERATION |
Below parameters are applicable for AM263Px device only
Parameter “CddDmaDmaChannelModule” represents the Cdd_Dma channel of EDMA module i.e., from 0 to 63.
Parameter “CddDmaChannelTriggerSource” represents the Cdd_Dma trigger source from external module (such as UART, SPI , Cross Bar etc)
Parameter “CddDmaDmaChannelXbar” represents the cross bar triggers that are represented in Parameter “CddDmaChannelTriggerSource” ( from “DMA_TRIG_XBAR_DMA_XBAR_OUT_0” to “DMA_TRIG_XBAR_DMA_XBAR_OUT_15”).
Parameter “CddDmaDmaChannelXbarMap” represents the trigger source, where cross bar triggers are mapped to particular interrupt trigger source from external modules (such as ADC, EPWM, FSI etc.., )
4.3.9.2. Symbolic Names deviations
None
4.3.9.3. Configuration rules and constraints to enable plausibility checks
None
4.3.10. Examples
4.3.10.1. Overview
Will be updated in the next release
4.3.10.2. Hardware Software Setup and Tools
None
4.3.10.3. Steps to build and run example
Cdd_Dma example applications demonstrates the MCAL CDD_DMA driver features, which is referred from folder <MCAL_ROOT>/examples/Dma.
There are 4 example applications provided to verify all the features of the module.
These applications can be built from the build folder by giving :
“gmake –s dma_pollingmode_app PLATFORM=am263px” for polling mode example
“gmake –s dma_interruptmode_app PLATFORM=am263px” for interrupt mode example
“gmake –s dma_linkingmode_app PLATFORM=am263px” for linking mode example
“gmake –s dma_chainingmode_app PLATFORM=am263px” for chaining mode example
In case of linking mode example multiple params are configured within the channel and once the execution gets completed with first paramSet then automatically second paramSet data will be loaded.
In case of chaining mode example multiple channels are chained together so in this case once the trigger for first channel happen for transmission it will internally trigger for second channel as well.So in this way with less number of trigger transmission happens.
Once the build is completed we get a binary file,which is loaded in our controller and executed.
4.3.10.4. Example Logs
Will be updated in next release
4.3.10.5. File Structure
📦AM263Px
┣ 📂build
┣ 📂mcal
┃ ┣ 📂examples
┃ ┃ ┣ 📂Dma
┃ ┃ ┃ ┣ 📂Dma_ChainingMode
┃ ┃ ┃ ┃ ┣ 📂soc
┃ ┃ ┃ ┃ ┣ 📜DmaChainingModeApp.c : Contains DMA test example.
┃ ┃ ┃ ┃ ┣ 📜DmaChainingModeApp.h : Contains DMA test example header.
┃ ┃ ┃ ┃ ┣ 📜Makefile
┃ ┃ ┃ ┣ 📂Dma_InterruptMode
┃ ┃ ┃ ┃ ┣ 📂soc
┃ ┃ ┃ ┃ ┣ 📜DmaInterruptModeApp.c : Contains DMA test example.
┃ ┃ ┃ ┃ ┣ 📜DmaInterruptModeApp.h : Contains DMA test example header.
┃ ┃ ┃ ┃ ┣ 📜Makefile
┃ ┃ ┃ ┣ 📂Dma_LinkingMode
┃ ┃ ┃ ┃ ┣ 📂soc
┃ ┃ ┃ ┃ ┣ 📜DmaLinkingModeApp.c : Contains DMA test example.
┃ ┃ ┃ ┃ ┣ 📜DmaLinkingModeApp.h : Contains DMA test example header.
┃ ┃ ┃ ┃ ┣ 📜Makefile
┃ ┃ ┃ ┣ 📂Dma_PollingMode
┃ ┃ ┃ ┃ ┣ 📂soc
┃ ┃ ┃ ┃ ┣ 📜DmaPollingModeApp.c : Contains DMA test example.
┃ ┃ ┃ ┃ ┣ 📜DmaPollingModeApp.h : Contains DMA test example header.
┃ ┃ ┃ ┃ ┣ 📜Makefile
┃ ┣ 📂examples_config
┃ ┃ ┣ 📂Dma_Demo_Cfg
┃ ┃ ┃ ┣ 📂soc
┃ ┃ ┃ ┃ ┣ 📂am263px
┃ ┃ ┃ ┃ ┃ ┣ 📂r5f0_0
┃ ┃ ┃ ┃ ┃ ┃ ┣ 📂include
┃ ┃ ┃ ┃ ┃ ┃ ┃ ┣ 📜Cdd_Dma_Cfg.h : Contains the Precompile switches, Symbolic names.
┃ ┃ ┃ ┃ ┃ ┃ ┣ 📂src
┃ ┃ ┃ ┃ ┃ ┃ ┃ ┣ 📜Cdd_Dma_Cfg.c : Contains all Pre-Compile Configured parameters
┃ 📂mcal_config
┃ 📂mcal_docs
┣ 📜README.txt
4.3.11. FAQ’s
None
4.3.12. Test Report
Please refer AM26x CDD DMA Driver Test Case Report as part of CSP provided in the release package.
