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Macros | |
#define | TISCI_HOST_ID_DMSC (0U) |
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#define | TISCI_HOST_ID_MAIN_0_R5_0 (3U) |
#define | TISCI_HOST_ID_R5_1 (4U) |
#define | TISCI_HOST_ID_R5_2 (5U) |
#define | TISCI_HOST_ID_R5_3 (6U) |
#define | TISCI_HOST_ID_A53_0 (10U) |
#define | TISCI_HOST_ID_A53_1 (11U) |
#define | TISCI_HOST_ID_A53_2 (12U) |
#define | TISCI_HOST_ID_A53_3 (13U) |
#define | TISCI_HOST_ID_A53_4 (14U) |
#define | TISCI_HOST_ID_A53_5 (15U) |
#define | TISCI_HOST_ID_A53_6 (16U) |
#define | TISCI_HOST_ID_A53_7 (17U) |
#define | TISCI_HOST_ID_GPU_0 (30U) |
#define | TISCI_HOST_ID_GPU_1 (31U) |
#define | TISCI_HOST_ID_ICSSG_0 (50U) |
#define | TISCI_HOST_ID_ICSSG_1 (51U) |
#define | TISCI_HOST_ID_ICSSG_2 (52U) |
#define | TISCI_HOST_ID_ALL (128U) |
#define | TISCI_HOST_ID_CNT (19U) |