AM65x MCU+ SDK  09.01.00
tisci_hosts.h
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59 #ifndef TISCI_HOSTS_H
60 #define TISCI_HOSTS_H
61 
62 /* Host IDs for AM6 Device */
63 
65 #define TISCI_HOST_ID_DMSC (0U)
66 
67 #define TISCI_HOST_ID_MAIN_0_R5_0 (3U)
68 
69 #define TISCI_HOST_ID_R5_1 (4U)
70 
71 #define TISCI_HOST_ID_R5_2 (5U)
72 
73 #define TISCI_HOST_ID_R5_3 (6U)
74 
75 #define TISCI_HOST_ID_A53_0 (10U)
76 
77 #define TISCI_HOST_ID_A53_1 (11U)
78 
79 #define TISCI_HOST_ID_A53_2 (12U)
80 
81 #define TISCI_HOST_ID_A53_3 (13U)
82 
83 #define TISCI_HOST_ID_A53_4 (14U)
84 
85 #define TISCI_HOST_ID_A53_5 (15U)
86 
87 #define TISCI_HOST_ID_A53_6 (16U)
88 
89 #define TISCI_HOST_ID_A53_7 (17U)
90 
91 #define TISCI_HOST_ID_GPU_0 (30U)
92 
93 #define TISCI_HOST_ID_GPU_1 (31U)
94 
95 #define TISCI_HOST_ID_ICSSG_0 (50U)
96 
97 #define TISCI_HOST_ID_ICSSG_1 (51U)
98 
99 #define TISCI_HOST_ID_ICSSG_2 (52U)
100 
105 #define TISCI_HOST_ID_ALL (128U)
106 
108 #define TISCI_HOST_ID_CNT (19U)
109 
110 #endif /* TISCI_HOSTS_H */
111