Introduction

DMSC controls the power management, security and resource management of the device.

Macros
#define	TISCI_HOST_ID_DMSC (0U)
	This file contains: More...

#define	TISCI_HOST_ID_MAIN_0_R5_0 (3U)

#define	TISCI_HOST_ID_R5_1 (4U)

#define	TISCI_HOST_ID_R5_2 (5U)

#define	TISCI_HOST_ID_R5_3 (6U)

#define	TISCI_HOST_ID_A53_0 (10U)

#define	TISCI_HOST_ID_A53_1 (11U)

#define	TISCI_HOST_ID_A53_2 (12U)

#define	TISCI_HOST_ID_A53_3 (13U)

#define	TISCI_HOST_ID_A53_4 (14U)

#define	TISCI_HOST_ID_A53_5 (15U)

#define	TISCI_HOST_ID_A53_6 (16U)

#define	TISCI_HOST_ID_A53_7 (17U)

#define	TISCI_HOST_ID_GPU_0 (30U)

#define	TISCI_HOST_ID_GPU_1 (31U)

#define	TISCI_HOST_ID_ICSSG_0 (50U)

#define	TISCI_HOST_ID_ICSSG_1 (51U)

#define	TISCI_HOST_ID_ICSSG_2 (52U)

#define	TISCI_HOST_ID_ALL (128U)

#define	TISCI_HOST_ID_CNT (19U)

Macro Definition Documentation

◆ TISCI_HOST_ID_DMSC

#define TISCI_HOST_ID_DMSC (0U)

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

System Firmware Source File

Host IDs for AM6 device

Host IDs for AM6 device DMSC(Secure): Device Management and Security Control

◆ TISCI_HOST_ID_MAIN_0_R5_0

#define TISCI_HOST_ID_MAIN_0_R5_0 (3U)

r5_0(Non Secure): Cortex R5 Context 0 on MCU island

◆ TISCI_HOST_ID_R5_1

#define TISCI_HOST_ID_R5_1 (4U)

r5_1(Secure): Cortex R5 Context 1 on MCU island(Boot)

◆ TISCI_HOST_ID_R5_2

#define TISCI_HOST_ID_R5_2 (5U)

r5_2(Non Secure): Cortex R5 Context 2 on MCU island

◆ TISCI_HOST_ID_R5_3

#define TISCI_HOST_ID_R5_3 (6U)

r5_3(Secure): Cortex R5 Context 3 on MCU island

◆ TISCI_HOST_ID_A53_0

#define TISCI_HOST_ID_A53_0 (10U)

a53_0(Secure): Cortex A53 context 0 on Main island

◆ TISCI_HOST_ID_A53_1

#define TISCI_HOST_ID_A53_1 (11U)

a53_1(Secure): Cortex A53 context 1 on Main island

◆ TISCI_HOST_ID_A53_2

#define TISCI_HOST_ID_A53_2 (12U)

a53_2(Non Secure): Cortex A53 context 2 on Main island

◆ TISCI_HOST_ID_A53_3

#define TISCI_HOST_ID_A53_3 (13U)

a53_3(Non Secure): Cortex A53 context 3 on Main island

◆ TISCI_HOST_ID_A53_4

#define TISCI_HOST_ID_A53_4 (14U)

a53_4(Non Secure): Cortex A53 context 4 on Main island

◆ TISCI_HOST_ID_A53_5

#define TISCI_HOST_ID_A53_5 (15U)

a53_5(Non Secure): Cortex A53 context 5 on Main island

◆ TISCI_HOST_ID_A53_6

#define TISCI_HOST_ID_A53_6 (16U)

a53_6(Non Secure): Cortex A53 context 6 on Main island

◆ TISCI_HOST_ID_A53_7

#define TISCI_HOST_ID_A53_7 (17U)

a53_7(Non Secure): Cortex A53 context 7 on Main island

◆ TISCI_HOST_ID_GPU_0

#define TISCI_HOST_ID_GPU_0 (30U)

gpu_0(Non Secure): SGX544 Context 0 on Main island

◆ TISCI_HOST_ID_GPU_1

#define TISCI_HOST_ID_GPU_1 (31U)

gpu_1(Non Secure): SGX544 Context 1 on Main island

◆ TISCI_HOST_ID_ICSSG_0

#define TISCI_HOST_ID_ICSSG_0 (50U)

icssg_0(Non Secure): ICSS Context 0 on Main island

◆ TISCI_HOST_ID_ICSSG_1

#define TISCI_HOST_ID_ICSSG_1 (51U)

icssg_1(Non Secure): ICSS Context 1 on Main island

◆ TISCI_HOST_ID_ICSSG_2

#define TISCI_HOST_ID_ICSSG_2 (52U)

icssg_2(Non Secure): ICSS Context 2 on Main island

◆ TISCI_HOST_ID_ALL

#define TISCI_HOST_ID_ALL (128U)

Host catch all. Used in board configuration resource assignments to define resource ranges useable by all hosts. Cannot be used

◆ TISCI_HOST_ID_CNT

#define TISCI_HOST_ID_CNT (19U)

Number of unique hosts on the SoC