soc.h

Go to the documentation of this file.

/*
 *  Copyright (C) 2021-2026 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef SOC_AM64X_H_
#define SOC_AM64X_H_
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
#include <drivers/sciclient.h>
#include <kernel/dpl/CpuIdP.h>
#include <drivers/hw_include/cslr_soc.h>
 
#define SOC_DOMAIN_ID_MAIN     (0U)
#define SOC_DOMAIN_ID_MCU      (1U)
 
/* PSC Instances */
#define SOC_PSC_DOMAIN_ID_MAIN      (0U)
#define SOC_PSC_DOMAIN_ID_MCU       (1U)
 
/* PSC (Power Sleep Controller) Module states */
#define SOC_PSC_SYNCRESETDISABLE        (0x0U)
#define SOC_PSC_SYNCRESET               (0x1U)
#define SOC_PSC_DISABLE                 (0x2U)
#define SOC_PSC_ENABLE                  (0x3U)
 
#define SOC_PSC_DOMAIN_OFF              (0x0U)
#define SOC_PSC_DOMAIN_ON               (0x1U)
 
#define SOC_BOOTMODE_MMCSD      (0X36C3)
 
#define SOC_H_IO_DRVSTRNGTH0    (0x40C0U)
#define SOC_H_IO_DRVSTRNGTH1    (0x40C4U)
#define SOC_V_IO_DRVSTRNGTH0    (0x40D0U)
#define SOC_V_IO_DRVSTRNGTH1    (0x40D4U)
 
#define SOC_IO_DRVSTRNGTH_MASK  CSL_MCU_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_DRV_STR_MASK
#define SOC_IO_DRVSTRNGTH_MAX   CSL_MCU_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_DRV_STR_MAX
 
#define SOC_FWL_OPEN_MAGIC_NUM  (0XFEDCBA98u)
 
/* MCU Base address to be used after Adress translation in MCU Domain. */
#define MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE   (CSL_MCU_MCSPI0_CFG_BASE + 0x80000000)
#define MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE   (CSL_MCU_MCSPI1_CFG_BASE + 0x80000000)
#define MCU_UART0_BASE_AFTER_ADDR_TRANSLATE        (CSL_MCU_UART0_BASE + 0x80000000)
#define MCU_UART1_BASE_AFTER_ADDR_TRANSLATE        (CSL_MCU_UART1_BASE + 0x80000000)
#define MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE     (CSL_MCU_I2C0_CFG_BASE + 0x80000000)
#define MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE     (CSL_MCU_I2C1_CFG_BASE + 0x80000000)
 
static inline int32_t I2C_lld_isBaseAddrValid(uint32_t baseAddr)
{
    /* Set status to invalid Param */
    int32_t status = (int32_t)(-3);
 
    if (    (baseAddr == CSL_I2C0_CFG_BASE) ||  \
            (baseAddr == CSL_I2C1_CFG_BASE) ||  \
            (baseAddr == CSL_I2C2_CFG_BASE) ||  \
            (baseAddr == CSL_I2C3_CFG_BASE) ||  \
            (baseAddr == CSL_MCU_I2C0_CFG_BASE) ||  \
            (baseAddr == CSL_MCU_I2C1_CFG_BASE) ||  \
            (baseAddr == MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE) ||  \
            (baseAddr == MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE) )
    {
        /* Set status to success */
        status = 0;
    }
 
    return status;
}
 
static inline int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
{
    int32_t status = (int32_t)-3;
 
    if ((baseAddr == CSL_MCSPI0_CFG_BASE) || \
        (baseAddr == CSL_MCSPI1_CFG_BASE) || \
        (baseAddr == CSL_MCSPI2_CFG_BASE) || \
        (baseAddr == CSL_MCSPI3_CFG_BASE) || \
        (baseAddr == CSL_MCSPI4_CFG_BASE) || \
        (baseAddr == CSL_MCU_MCSPI0_CFG_BASE) || \
        (baseAddr == CSL_MCU_MCSPI1_CFG_BASE) || \
        (baseAddr == MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE) || \
        (baseAddr == MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE))
    {
        status = 0;
    }
 
    return status;
}
 
static inline int32_t UART_IsBaseAddrValid(uint32_t baseAddr)
{
    int32_t status = (int32_t)-3;
 
    if ((baseAddr == CSL_UART0_BASE) ||
        (baseAddr == CSL_UART1_BASE) ||
        (baseAddr == CSL_UART2_BASE) ||
        (baseAddr == CSL_UART3_BASE) ||
        (baseAddr == CSL_UART4_BASE) ||
        (baseAddr == CSL_UART5_BASE) ||
        (baseAddr == CSL_UART6_BASE) ||
        (baseAddr == CSL_MCU_UART0_BASE) ||
        (baseAddr == CSL_MCU_UART1_BASE) ||
        (baseAddr == MCU_UART0_BASE_AFTER_ADDR_TRANSLATE) ||
        (baseAddr == MCU_UART1_BASE_AFTER_ADDR_TRANSLATE))
 
    {
        status = 0;
    }
 
    return status;
}
 
static inline int32_t MMCSD_lld_isBaseAddrValid(uint32_t ctrlBaseAddr,
                                                uint32_t ssBaseAddr)
{
    /* Set status to invalid Param */
    int32_t status = (int32_t)(-3);
 
    if ((   (ctrlBaseAddr == CSL_MMCSD1_CTL_CFG_BASE)  &&
            (ssBaseAddr == CSL_MMCSD1_SS_CFG_BASE))    ||
        (   (ctrlBaseAddr == CSL_MMCSD0_CTL_CFG_BASE) &&
            (ssBaseAddr == CSL_MMCSD0_SS_CFG_BASE)))
    {
        /* Set status to success */
        status = 0;
    }
 
    return status;
}
#define IS_OSPI_BASE_ADDR_VALID(baseAddr)    (baseAddr == CSL_FSS0_OSPI0_CTRL_BASE)
 
#define IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr)    (baseAddr == CSL_FSS0_DAT_REG1_BASE)
 
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
 
int32_t SOC_moduleSetClockFrequencyWithParent(uint32_t moduleId, uint32_t clkId, uint32_t clkParent, uint64_t clkRate);
 
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
 
int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate);
 
const char *SOC_getCoreName(uint16_t coreId);
 
uint64_t SOC_getSelfCpuClk(void);
 
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
 
void SOC_allowEpwmTzReg(uint32_t epwmInstance, uint32_t enable);
 
uint64_t SOC_virtToPhy(void *virtAddr);
 
void *SOC_phyToVirt(uint64_t phyAddr);
 
void SOC_unlockAllMMR(void);
 
void SOC_setDevStat(uint32_t bootMode);
 
uint32_t SOC_isR5FDualCoreMode(CSL_ArmR5CPUInfo *cpuInfo);
 
void SOC_generateSwWarmResetMainDomain(void);
 
void SOC_generateSwPORResetMainDomain(void);
 
uint32_t SOC_getWarmResetCauseMainDomain(void);
 
void SOC_generateSwWarmResetMcuDomain(void);
 
void SOC_generateSwWarmResetMainDomainFromMcuDomain(void);
 
void SOC_generateSwPORResetMainDomainFromMcuDomain(void);
 
uint32_t SOC_getWarmResetCauseMcuDomain(void);
 
void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause);
 
int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, \
                        uint32_t debugIsolationEnable);
 
void SOC_setMCUResetIsolationDone(uint32_t value);
 
void SOC_waitMainDomainReset(void);
 
int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum,
                    uint32_t *domainState, uint32_t *moduleState);
 
int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState);
 
void SOC_waitForFwlUnlock(void);
 
int32_t SOC_isHsDevice(void);
 
uint32_t SOC_getFlashDataBaseAddr(void);
 
void SOC_fixFastDriveStrength(void);
 
#ifdef __cplusplus
}
#endif
 
#endif