AM64x MCU+ SDK  10.01.00
soc.h
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32 
33 #ifndef SOC_AM64X_H_
34 #define SOC_AM64X_H_
35 
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 
50 #include <kernel/dpl/SystemP.h>
51 #include <drivers/sciclient.h>
52 #include <kernel/dpl/CpuIdP.h>
53 #include <drivers/hw_include/am64x_am243x/cslr_soc_baseaddress.h>
54 
60 #define SOC_DOMAIN_ID_MAIN (0U)
61 #define SOC_DOMAIN_ID_MCU (1U)
62 
69 /* PSC Instances */
70 #define SOC_PSC_DOMAIN_ID_MAIN (0U)
71 #define SOC_PSC_DOMAIN_ID_MCU (1U)
72 
79 /* PSC (Power Sleep Controller) Module states */
80 #define SOC_PSC_SYNCRESETDISABLE (0x0U)
81 #define SOC_PSC_SYNCRESET (0x1U)
82 #define SOC_PSC_DISABLE (0x2U)
83 #define SOC_PSC_ENABLE (0x3U)
84 
91 #define SOC_PSC_DOMAIN_OFF (0x0U)
92 #define SOC_PSC_DOMAIN_ON (0x1U)
93 
98 #define SOC_BOOTMODE_MMCSD (0X36C3)
99 
103 #define SOC_FWL_OPEN_MAGIC_NUM (0XFEDCBA98u)
104 
105 /* MCU Base address to be used after Adress translation in MCU Domain. */
106 #define MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI0_CFG_BASE + 0x80000000)
107 #define MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI1_CFG_BASE + 0x80000000)
108 #define MCU_UART0_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART0_BASE + 0x80000000)
109 #define MCU_UART1_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART1_BASE + 0x80000000)
110 #define MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C0_CFG_BASE + 0x80000000)
111 #define MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C1_CFG_BASE + 0x80000000)
112 
114 static inline int32_t I2C_lld_isBaseAddrValid(uint32_t baseAddr)
115 {
116  /* Set status to invalid Param */
117  int32_t status = (int32_t)(-3);
118 
119  if ( (baseAddr == CSL_I2C0_CFG_BASE) || \
120  (baseAddr == CSL_I2C1_CFG_BASE) || \
121  (baseAddr == CSL_I2C2_CFG_BASE) || \
122  (baseAddr == CSL_I2C3_CFG_BASE) || \
123  (baseAddr == CSL_MCU_I2C0_CFG_BASE) || \
124  (baseAddr == CSL_MCU_I2C0_CFG_BASE) || \
125  (baseAddr == MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE) || \
127  {
128  /* Set status to success */
129  status = 0;
130  }
131 
132  return status;
133 }
134 
136 static inline int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
137 {
138  int32_t status = (int32_t)-3;
139 
140  if ((baseAddr == CSL_MCSPI0_CFG_BASE) || \
141  (baseAddr == CSL_MCSPI1_CFG_BASE) || \
142  (baseAddr == CSL_MCSPI2_CFG_BASE) || \
143  (baseAddr == CSL_MCSPI3_CFG_BASE) || \
144  (baseAddr == CSL_MCSPI4_CFG_BASE) || \
145  (baseAddr == CSL_MCU_MCSPI0_CFG_BASE) || \
146  (baseAddr == CSL_MCU_MCSPI1_CFG_BASE) || \
149  {
150  status = 0;
151  }
152 
153  return status;
154 }
155 
157 static inline int32_t UART_IsBaseAddrValid(uint32_t baseAddr)
158 {
159  int32_t status = (int32_t)-3;
160 
161  if ((baseAddr == CSL_UART0_BASE) ||
162  (baseAddr == CSL_UART1_BASE) ||
163  (baseAddr == CSL_UART2_BASE) ||
164  (baseAddr == CSL_UART3_BASE) ||
165  (baseAddr == CSL_UART4_BASE) ||
166  (baseAddr == CSL_UART5_BASE) ||
167  (baseAddr == CSL_UART6_BASE) ||
168  (baseAddr == CSL_MCU_UART0_BASE) ||
169  (baseAddr == CSL_MCU_UART1_BASE) ||
170  (baseAddr == MCU_UART0_BASE_AFTER_ADDR_TRANSLATE) ||
172 
173  {
174  status = 0;
175  }
176 
177  return status;
178 }
179 
181 static inline int32_t MMCSD_lld_isBaseAddrValid(uint32_t ctrlBaseAddr,
182  uint32_t ssBaseAddr)
183 {
184  /* Set status to invalid Param */
185  int32_t status = (int32_t)(-3);
186 
187  if (( (ctrlBaseAddr == CSL_MMCSD1_CTL_CFG_BASE) &&
188  (ssBaseAddr == CSL_MMCSD1_SS_CFG_BASE)) ||
189  ( (ctrlBaseAddr == CSL_MMCSD0_CTL_CFG_BASE) &&
190  (ssBaseAddr == CSL_MMCSD0_SS_CFG_BASE)))
191  {
192  /* Set status to success */
193  status = 0;
194  }
195 
196  return status;
197 }
199 #define IS_OSPI_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_FSS0_OSPI0_CTRL_BASE)
200 
202 #define IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_FSS0_DAT_REG1_BASE)
203 
213 int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
214 
226 int32_t SOC_moduleSetClockFrequencyWithParent(uint32_t moduleId, uint32_t clkId, uint32_t clkParent, uint64_t clkRate);
227 
238 int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
239 
249 int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate);
250 
258 const char *SOC_getCoreName(uint16_t coreId);
259 
265 uint64_t SOC_getSelfCpuClk(void);
266 
273 void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
274 
281 void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
282 
289 void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
290 
297 void SOC_allowEpwmTzReg(uint32_t epwmInstance, uint32_t enable);
298 
306 uint64_t SOC_virtToPhy(void *virtAddr);
307 
315 void *SOC_phyToVirt(uint64_t phyAddr);
316 
320 void SOC_unlockAllMMR(void);
321 
327 void SOC_setDevStat(uint32_t bootMode);
328 
337 
342 
347 
354 
359 
364 
369 
376 
385 void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause);
386 
399 int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, \
400  uint32_t debugIsolationEnable);
401 
409 
414 
426 int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum,
427  uint32_t *domainState, uint32_t *moduleState);
428 
439 int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState);
440 
446 
452 int32_t SOC_isHsDevice(void);
453 
460 
463 #ifdef __cplusplus
464 }
465 #endif
466 
467 #endif
sciclient.h
This file contains prototypes for APIs contained as a part of SCICLIENT as well as the structures of ...
SOC_moduleSetClockFrequency
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
Set module clock to specified frequency.
SOC_moduleSetClockFrequencyWithParent
int32_t SOC_moduleSetClockFrequencyWithParent(uint32_t moduleId, uint32_t clkId, uint32_t clkParent, uint64_t clkRate)
Set module clock to specified frequency and with a specific parent.
SOC_controlModuleUnlockMMR
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)
Unlock control module partition to allow writes into control MMRs.
SOC_virtToPhy
uint64_t SOC_virtToPhy(void *virtAddr)
SOC Virtual (CPU) to Physical address translation function.
MCU_UART1_BASE_AFTER_ADDR_TRANSLATE
#define MCU_UART1_BASE_AFTER_ADDR_TRANSLATE
Definition: soc.h:109
SOC_generateSwWarmResetMainDomainFromMcuDomain
void SOC_generateSwWarmResetMainDomainFromMcuDomain(void)
Generate SW WARM Reset Main Domain from Mcu Domain.
SOC_generateSwPORResetMainDomainFromMcuDomain
void SOC_generateSwPORResetMainDomainFromMcuDomain(void)
Generate SW POR Reset Main Domain from Mcu Domain.
SystemP.h
SOC_getFlashDataBaseAddr
uint32_t SOC_getFlashDataBaseAddr(void)
This function gets the SOC mapped data base address of the flash.
SOC_clearResetCauseMainMcuDomain
void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause)
Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLM...
MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE
#define MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE
Definition: soc.h:106
SOC_unlockAllMMR
void SOC_unlockAllMMR(void)
Unlocks all the control MMRs.
MMCSD_lld_isBaseAddrValid
static int32_t MMCSD_lld_isBaseAddrValid(uint32_t ctrlBaseAddr, uint32_t ssBaseAddr)
API to validate MMCSD base addresses.
Definition: soc.h:181
MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE
#define MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE
Definition: soc.h:111
SOC_setMCUResetIsolationDone
void SOC_setMCUResetIsolationDone(uint32_t value)
Set MCU reset isolation done flag.
SOC_generateSwWarmResetMcuDomain
void SOC_generateSwWarmResetMcuDomain(void)
Generate SW WARM Reset Mcu Domain.
SOC_waitForFwlUnlock
void SOC_waitForFwlUnlock(void)
Wait for Firewall unlock from SBL. The function polls for a Software defined Magic number at the PSRA...
SOC_moduleGetClockFrequency
int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
Get module clock frequency.
SOC_getWarmResetCauseMainDomain
uint32_t SOC_getWarmResetCauseMainDomain(void)
Get the reset reason source for Main Domain.
MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE
#define MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE
Definition: soc.h:110
SOC_isHsDevice
int32_t SOC_isHsDevice(void)
Check the device is HS or not.
SOC_waitMainDomainReset
void SOC_waitMainDomainReset(void)
Wait for main domain reset to complete.
SOC_phyToVirt
void * SOC_phyToVirt(uint64_t phyAddr)
Physical to Virtual (CPU) address translation function.
CSL_ArmR5CPUInfo
Structure containing the CPU Info such as CPU ID and Cluster Group ID.
Definition: CpuIdP.h:57
MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE
#define MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE
Definition: soc.h:107
value
uint32_t value
Definition: tisci_otp_revision.h:2
SOC_setPSCState
int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)
Set PSC (Power Sleep Controller) state.
SOC_getSelfCpuClk
uint64_t SOC_getSelfCpuClk(void)
Get the clock frequency in Hz of the CPU on which the driver is running.
SOC_enableResetIsolation
int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t debugIsolationEnable)
Enable reset isolation of MCU domain for safety applications.
UART_IsBaseAddrValid
static int32_t UART_IsBaseAddrValid(uint32_t baseAddr)
API to validate UART base address.
Definition: soc.h:157
SOC_generateSwWarmResetMainDomain
void SOC_generateSwWarmResetMainDomain(void)
Generate SW Warm Reset Main Domain.
SOC_allowEpwmTzReg
void SOC_allowEpwmTzReg(uint32_t epwmInstance, uint32_t enable)
Enable or disable writes to the EPWM tripZone registers.
I2C_lld_isBaseAddrValid
static int32_t I2C_lld_isBaseAddrValid(uint32_t baseAddr)
API to validate I2C base address.
Definition: soc.h:114
MCSPI_lld_isBaseAddrValid
static int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
API to validate MCSPI base address.
Definition: soc.h:136
SOC_generateSwPORResetMainDomain
void SOC_generateSwPORResetMainDomain(void)
Generate SW POR Reset Main Domain.
CpuIdP.h
SOC_controlModuleLockMMR
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)
Lock control module partition to prevent writes into control MMRs.
SOC_moduleClockEnable
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)
Enable clock to specified module.
SOC_setDevStat
void SOC_setDevStat(uint32_t bootMode)
Change boot mode by setting devstat register.
SOC_getPSCState
int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t *domainState, uint32_t *moduleState)
Get PSC (Power Sleep Controller) state.
SOC_getCoreName
const char * SOC_getCoreName(uint16_t coreId)
Convert a core ID to a user readable name.
SOC_isR5FDualCoreMode
uint32_t SOC_isR5FDualCoreMode(CSL_ArmR5CPUInfo *cpuInfo)
Return R5SS supporting single or dual core mode.
SOC_setEpwmTbClk
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)
Enable or disable ePWM time base clock from Control MMR.
MCU_UART0_BASE_AFTER_ADDR_TRANSLATE
#define MCU_UART0_BASE_AFTER_ADDR_TRANSLATE
Definition: soc.h:108
SOC_getWarmResetCauseMcuDomain
uint32_t SOC_getWarmResetCauseMcuDomain(void)
Get the reset reason source for Mcu Domain.