Introduction

For more details and example usage, see SOC

Functions
static int32_t	I2C_lld_isBaseAddrValid (uint32_t baseAddr)
	API to validate I2C base address. More...

static int32_t	MCSPI_lld_isBaseAddrValid (uint32_t baseAddr)
	API to validate MCSPI base address. More...

static int32_t	UART_IsBaseAddrValid (uint32_t baseAddr)
	API to validate UART base address. More...

static int32_t	MMCSD_lld_isBaseAddrValid (uint32_t ctrlBaseAddr, uint32_t ssBaseAddr)
	API to validate MMCSD base addresses. More...

int32_t	SOC_moduleClockEnable (uint32_t moduleId, uint32_t enable)
	Enable clock to specified module. More...

int32_t	SOC_moduleSetClockFrequencyWithParent (uint32_t moduleId, uint32_t clkId, uint32_t clkParent, uint64_t clkRate)
	Set module clock to specified frequency and with a specific parent. More...

int32_t	SOC_moduleSetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
	Set module clock to specified frequency. More...

int32_t	SOC_moduleGetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
	Get module clock frequency. More...

const char *	SOC_getCoreName (uint16_t coreId)
	Convert a core ID to a user readable name. More...

uint64_t	SOC_getSelfCpuClk (void)
	Get the clock frequency in Hz of the CPU on which the driver is running. More...

void	SOC_controlModuleLockMMR (uint32_t domainId, uint32_t partition)
	Lock control module partition to prevent writes into control MMRs. More...

void	SOC_controlModuleUnlockMMR (uint32_t domainId, uint32_t partition)
	Unlock control module partition to allow writes into control MMRs. More...

void	SOC_setEpwmTbClk (uint32_t epwmInstance, uint32_t enable)
	Enable or disable ePWM time base clock from Control MMR. More...

void	SOC_allowEpwmTzReg (uint32_t epwmInstance, uint32_t enable)
	Enable or disable writes to the EPWM tripZone registers. More...

uint64_t	SOC_virtToPhy (void *virtAddr)
	SOC Virtual (CPU) to Physical address translation function. More...

void *	SOC_phyToVirt (uint64_t phyAddr)
	Physical to Virtual (CPU) address translation function. More...

void	SOC_unlockAllMMR (void)
	Unlocks all the control MMRs. More...

void	SOC_setDevStat (uint32_t bootMode)
	Change boot mode by setting devstat register. More...

uint32_t	SOC_isR5FDualCoreMode (CSL_ArmR5CPUInfo *cpuInfo)
	Return R5SS supporting single or dual core mode. More...

void	SOC_generateSwWarmResetMainDomain (void)
	Generate SW Warm Reset Main Domain. More...

void	SOC_generateSwPORResetMainDomain (void)
	Generate SW POR Reset Main Domain. More...

uint32_t	SOC_getWarmResetCauseMainDomain (void)
	Get the reset reason source for Main Domain. More...

void	SOC_generateSwWarmResetMcuDomain (void)
	Generate SW WARM Reset Mcu Domain. More...

void	SOC_generateSwWarmResetMainDomainFromMcuDomain (void)
	Generate SW WARM Reset Main Domain from Mcu Domain. More...

void	SOC_generateSwPORResetMainDomainFromMcuDomain (void)
	Generate SW POR Reset Main Domain from Mcu Domain. More...

uint32_t	SOC_getWarmResetCauseMcuDomain (void)
	Get the reset reason source for Mcu Domain. More...

void	SOC_clearResetCauseMainMcuDomain (uint32_t resetCause)
	Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLMMR_MCU_RST_SRC register. It is read only. So we need to write 1 to CTRLMMR_MCU_RST_SRC to clear the reset reason. More...

int32_t	SOC_enableResetIsolation (uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t debugIsolationEnable)
	Enable reset isolation of MCU domain for safety applications. More...

void	SOC_setMCUResetIsolationDone (uint32_t value)
	Set MCU reset isolation done flag. More...

void	SOC_waitMainDomainReset (void)
	Wait for main domain reset to complete. More...

int32_t	SOC_getPSCState (uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t domainState, uint32_t moduleState)
	Get PSC (Power Sleep Controller) state. More...

int32_t	SOC_setPSCState (uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)
	Set PSC (Power Sleep Controller) state. More...

void	SOC_waitForFwlUnlock (void)
	Wait for Firewall unlock from SBL. The function polls for a Software defined Magic number at the PSRAM location (Software defined) More...

int32_t	SOC_isHsDevice (void)
	Check the device is HS or not. More...

uint32_t	SOC_getFlashDataBaseAddr (void)
	This function gets the SOC mapped data base address of the flash. More...

void	SOC_fixFastDriveStrength (void)
	Fix fast mode drive strength. More...

Macros
#define	SOC_BOOTMODE_MMCSD (0X36C3)
	Switch value for SD card boot mode. More...

#define	SOC_H_IO_DRVSTRNGTH0 (0x40C0U)
	IO Drive Strength Register offsets. More...

#define	SOC_H_IO_DRVSTRNGTH1 (0x40C4U)

#define	SOC_V_IO_DRVSTRNGTH0 (0x40D0U)

#define	SOC_V_IO_DRVSTRNGTH1 (0x40D4U)

#define	SOC_IO_DRVSTRNGTH_MASK CSL_MCU_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_DRV_STR_MASK
	IO Drive Strength field definitions. More...

#define	SOC_IO_DRVSTRNGTH_MAX CSL_MCU_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_DRV_STR_MAX

#define	SOC_FWL_OPEN_MAGIC_NUM (0XFEDCBA98u)
	Software defined MAGIC number to indicate SRAM firewall open by SBL. More...

#define	MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI0_CFG_BASE + 0x80000000)

#define	MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI1_CFG_BASE + 0x80000000)

#define	MCU_UART0_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART0_BASE + 0x80000000)

#define	MCU_UART1_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART1_BASE + 0x80000000)

#define	MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C0_CFG_BASE + 0x80000000)

#define	MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C1_CFG_BASE + 0x80000000)

#define	IS_OSPI_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_FSS0_OSPI0_CTRL_BASE)
	Macro to check if the OSPI base address is valid. More...

#define	IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_FSS0_DAT_REG1_BASE)
	Macro to check if the OSPI base address is valid. More...

SOC Domain ID

#define	SOC_DOMAIN_ID_MAIN (0U)

#define	SOC_DOMAIN_ID_MCU (1U)

#define	SOC_PSC_DOMAIN_ID_MAIN (0U)

#define	SOC_PSC_DOMAIN_ID_MCU (1U)

SOC PSC Module State

#define	SOC_PSC_SYNCRESETDISABLE (0x0U)

#define	SOC_PSC_SYNCRESET (0x1U)

#define	SOC_PSC_DISABLE (0x2U)

#define	SOC_PSC_ENABLE (0x3U)

SOC PSC Domain State

#define	SOC_PSC_DOMAIN_OFF (0x0U)

#define	SOC_PSC_DOMAIN_ON (0x1U)

Macro Definition Documentation

◆ SOC_DOMAIN_ID_MAIN

#define SOC_DOMAIN_ID_MAIN (0U)

◆ SOC_DOMAIN_ID_MCU

#define SOC_DOMAIN_ID_MCU (1U)

◆ SOC_PSC_DOMAIN_ID_MAIN

#define SOC_PSC_DOMAIN_ID_MAIN (0U)

\ SOC PSC Domain ID

◆ SOC_PSC_DOMAIN_ID_MCU

#define SOC_PSC_DOMAIN_ID_MCU (1U)

◆ SOC_PSC_SYNCRESETDISABLE

#define SOC_PSC_SYNCRESETDISABLE (0x0U)

◆ SOC_PSC_SYNCRESET

#define SOC_PSC_SYNCRESET (0x1U)

◆ SOC_PSC_DISABLE

#define SOC_PSC_DISABLE (0x2U)

◆ SOC_PSC_ENABLE

#define SOC_PSC_ENABLE (0x3U)

◆ SOC_PSC_DOMAIN_OFF

#define SOC_PSC_DOMAIN_OFF (0x0U)

◆ SOC_PSC_DOMAIN_ON

#define SOC_PSC_DOMAIN_ON (0x1U)

◆ SOC_BOOTMODE_MMCSD

#define SOC_BOOTMODE_MMCSD (0X36C3)

Switch value for SD card boot mode.

◆ SOC_H_IO_DRVSTRNGTH0

#define SOC_H_IO_DRVSTRNGTH0 (0x40C0U)

IO Drive Strength Register offsets.

◆ SOC_H_IO_DRVSTRNGTH1

#define SOC_H_IO_DRVSTRNGTH1 (0x40C4U)

◆ SOC_V_IO_DRVSTRNGTH0

#define SOC_V_IO_DRVSTRNGTH0 (0x40D0U)

◆ SOC_V_IO_DRVSTRNGTH1

#define SOC_V_IO_DRVSTRNGTH1 (0x40D4U)

◆ SOC_IO_DRVSTRNGTH_MASK

#define SOC_IO_DRVSTRNGTH_MASK CSL_MCU_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_DRV_STR_MASK

IO Drive Strength field definitions.

◆ SOC_IO_DRVSTRNGTH_MAX

#define SOC_IO_DRVSTRNGTH_MAX CSL_MCU_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_DRV_STR_MAX

◆ SOC_FWL_OPEN_MAGIC_NUM

#define SOC_FWL_OPEN_MAGIC_NUM (0XFEDCBA98u)

Software defined MAGIC number to indicate SRAM firewall open by SBL.

◆ MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE

#define MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI0_CFG_BASE + 0x80000000)

◆ MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE

#define MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI1_CFG_BASE + 0x80000000)

◆ MCU_UART0_BASE_AFTER_ADDR_TRANSLATE

#define MCU_UART0_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART0_BASE + 0x80000000)

◆ MCU_UART1_BASE_AFTER_ADDR_TRANSLATE

#define MCU_UART1_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART1_BASE + 0x80000000)

◆ MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE

#define MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C0_CFG_BASE + 0x80000000)

◆ MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE

#define MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C1_CFG_BASE + 0x80000000)

◆ IS_OSPI_BASE_ADDR_VALID

#define IS_OSPI_BASE_ADDR_VALID ( baseAddr ) (baseAddr == CSL_FSS0_OSPI0_CTRL_BASE)

Macro to check if the OSPI base address is valid.

◆ IS_OSPI_DATA_BASE_ADDR_VALID

#define IS_OSPI_DATA_BASE_ADDR_VALID ( baseAddr ) (baseAddr == CSL_FSS0_DAT_REG1_BASE)

Macro to check if the OSPI base address is valid.

Function Documentation

◆ I2C_lld_isBaseAddrValid()

static int32_t I2C_lld_isBaseAddrValid ( uint32_t baseAddr )

inlinestatic

API to validate I2C base address.

◆ MCSPI_lld_isBaseAddrValid()

static int32_t MCSPI_lld_isBaseAddrValid ( uint32_t baseAddr )

inlinestatic

API to validate MCSPI base address.

◆ UART_IsBaseAddrValid()

static int32_t UART_IsBaseAddrValid ( uint32_t baseAddr )

inlinestatic

API to validate UART base address.

◆ MMCSD_lld_isBaseAddrValid()

static int32_t MMCSD_lld_isBaseAddrValid	(	uint32_t	ctrlBaseAddr,
		uint32_t	ssBaseAddr
	)

inlinestatic

API to validate MMCSD base addresses.

◆ SOC_moduleClockEnable()

int32_t SOC_moduleClockEnable	(	uint32_t	moduleId,
		uint32_t	enable
	)

Enable clock to specified module.

Parameters

moduleId	[in] see tisci_devices for list of device ID's
enable	[in] 1: enable clock to the module, 0: disable clock to the module

Returns: SystemP_SUCCESS Module clock is enabled; SystemP_FAILURE Module clock could not be enabled

◆ SOC_moduleSetClockFrequencyWithParent()

int32_t SOC_moduleSetClockFrequencyWithParent	(	uint32_t	moduleId,
		uint32_t	clkId,
		uint32_t	clkParent,
		uint64_t	clkRate
	)

Set module clock to specified frequency and with a specific parent.

Parameters

moduleId	[in] see tisci_devices for list of module ID's
clkId	[in] see tisci_clocks for list of clocks associated with the specified module ID
clkParent	[in] see tisci_clocks for list of clock parents associated with the specified module ID
clkRate	[in] Frequency to set in Hz

Returns: SystemP_SUCCESS Module clock is enabled; SystemP_FAILURE Module clock could not be enabled

◆ SOC_moduleSetClockFrequency()

int32_t SOC_moduleSetClockFrequency	(	uint32_t	moduleId,
		uint32_t	clkId,
		uint64_t	clkRate
	)

Set module clock to specified frequency.

Parameters

moduleId	[in] see tisci_devices for list of module ID's
clkId	[in] see tisci_clocks for list of clocks associated with the specified module ID
clkRate	[in] Frequency to set in Hz

Returns: SystemP_SUCCESS Module clock is enabled; SystemP_FAILURE Module clock could not be enabled

◆ SOC_moduleGetClockFrequency()

int32_t SOC_moduleGetClockFrequency	(	uint32_t	moduleId,
		uint32_t	clkId,
		uint64_t *	clkRate
	)

Get module clock frequency.

Parameters

moduleId	[in] see tisci_devices for list of module ID's
clkId	[in] see tisci_clocks for list of clocks associated with the specified module ID
clkRate	[out] Frequency of the clock

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_getCoreName()

const char* SOC_getCoreName ( uint16_t coreId )

Convert a core ID to a user readable name.

Parameters

coreId [in] see CSL_CoreID

Returns: name as a string

◆ SOC_getSelfCpuClk()

uint64_t SOC_getSelfCpuClk ( void )

Get the clock frequency in Hz of the CPU on which the driver is running.

Returns: Clock frequency in Hz

◆ SOC_controlModuleLockMMR()

void SOC_controlModuleLockMMR	(	uint32_t	domainId,
		uint32_t	partition
	)

Lock control module partition to prevent writes into control MMRs.

Parameters

domainId	[in] See SOC_DomainId_t
partition	[in] Partition number to unlock

◆ SOC_controlModuleUnlockMMR()

void SOC_controlModuleUnlockMMR	(	uint32_t	domainId,
		uint32_t	partition
	)

Unlock control module partition to allow writes into control MMRs.

Parameters

domainId	[in] See SOC_DomainId_t
partition	[in] Partition number to unlock

◆ SOC_setEpwmTbClk()

void SOC_setEpwmTbClk	(	uint32_t	epwmInstance,
		uint32_t	enable
	)

Enable or disable ePWM time base clock from Control MMR.

Parameters

epwmInstance	[in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)]
enable	[in] TRUE to enable and FALSE to disable

◆ SOC_allowEpwmTzReg()

void SOC_allowEpwmTzReg	(	uint32_t	epwmInstance,
		uint32_t	enable
	)

Enable or disable writes to the EPWM tripZone registers.

Parameters

epwmInstance	[in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)]
enable	[in] TRUE to enable and FALSE to disable

◆ SOC_virtToPhy()

uint64_t SOC_virtToPhy ( void * virtAddr )

SOC Virtual (CPU) to Physical address translation function.

Parameters

virtAddr [IN] Virtual/CPU address

Returns: Corresponding SOC physical address

◆ SOC_phyToVirt()

void* SOC_phyToVirt ( uint64_t phyAddr )

Physical to Virtual (CPU) address translation function.

Parameters

phyAddr [IN] Physical address

Returns: Corresponding virtual/CPU address

◆ SOC_unlockAllMMR()

void SOC_unlockAllMMR ( void )

Unlocks all the control MMRs.

◆ SOC_setDevStat()

void SOC_setDevStat ( uint32_t bootMode )

Change boot mode by setting devstat register.

Parameters

bootMode [IN] Boot mode switch value

◆ SOC_isR5FDualCoreMode()

uint32_t SOC_isR5FDualCoreMode ( CSL_ArmR5CPUInfo * cpuInfo )

Return R5SS supporting single or dual core mode.

Parameters

cpuInfo [in] Pointer to the CSL_ArmR5CPUInfo struct.

Returns: TRUE if it is Dual Core mode else FALSE.

◆ SOC_generateSwWarmResetMainDomain()

void SOC_generateSwWarmResetMainDomain ( void )

Generate SW Warm Reset Main Domain.

◆ SOC_generateSwPORResetMainDomain()

void SOC_generateSwPORResetMainDomain ( void )

Generate SW POR Reset Main Domain.

◆ SOC_getWarmResetCauseMainDomain()

uint32_t SOC_getWarmResetCauseMainDomain ( void )

Get the reset reason source for Main Domain.

Returns: Reset Reason Source Main Domain

◆ SOC_generateSwWarmResetMcuDomain()

void SOC_generateSwWarmResetMcuDomain ( void )

Generate SW WARM Reset Mcu Domain.

◆ SOC_generateSwWarmResetMainDomainFromMcuDomain()

void SOC_generateSwWarmResetMainDomainFromMcuDomain ( void )

Generate SW WARM Reset Main Domain from Mcu Domain.

◆ SOC_generateSwPORResetMainDomainFromMcuDomain()

void SOC_generateSwPORResetMainDomainFromMcuDomain ( void )

Generate SW POR Reset Main Domain from Mcu Domain.

◆ SOC_getWarmResetCauseMcuDomain()

uint32_t SOC_getWarmResetCauseMcuDomain ( void )

Get the reset reason source for Mcu Domain.

Returns: Reset Reason Source Mcu Domain

◆ SOC_clearResetCauseMainMcuDomain()

void SOC_clearResetCauseMainMcuDomain ( uint32_t resetCause )

Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLMMR_MCU_RST_SRC register. It is read only. So we need to write 1 to CTRLMMR_MCU_RST_SRC to clear the reset reason.

Parameters

resetCause [IN] Reset reason value to clear.

◆ SOC_enableResetIsolation()

int32_t SOC_enableResetIsolation	(	uint32_t	main2McuIsolation,
		uint32_t	mcu2MainIsolation,
		uint32_t	debugIsolationEnable
	)

Enable reset isolation of MCU domain for safety applications.

Parameters

main2McuIsolation	[IN] Flag to enable isolation of mcu domain from main domain Setting this flag restricts the access of MCU resources by main domain
mcu2MainIsolation	[IN] Flag to enable isolation of main domain from mcu domain Setting this flag restricts the access of MCU resources by main domain
debugIsolationEnable	[IN] Enable debug isolation. Setting this would restrict JTAG access to MCU domain

◆ SOC_setMCUResetIsolationDone()

void SOC_setMCUResetIsolationDone ( uint32_t value )

Set MCU reset isolation done flag.

Parameters

value [IN] : 0 - Allow main domain reset to propogate : 1 - Do not allow main domain reset to propogate

◆ SOC_waitMainDomainReset()

void SOC_waitMainDomainReset ( void )

Wait for main domain reset to complete.

◆ SOC_getPSCState()

int32_t SOC_getPSCState	(	uint32_t	instNum,
		uint32_t	domainNum,
		uint32_t	moduleNum,
		uint32_t *	domainState,
		uint32_t *	moduleState
	)

Get PSC (Power Sleep Controller) state.

Parameters

instNum	[IN] : PSC Instance. See SOC_PSCDomainId_t
domainNum	[IN] : Power domain number
moduleNum	[IN] : Module number
domainState	[OUT] : Domain state (1 : ON, 0 : OFF)
moduleState	[OUT] : Module State. See SOC_PSCModuleState_t

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_setPSCState()

int32_t SOC_setPSCState	(	uint32_t	instNum,
		uint32_t	domainNum,
		uint32_t	moduleNum,
		uint32_t	pscState
	)

Set PSC (Power Sleep Controller) state.

Parameters

instNum	[IN] : PSC Instance. See SOC_PSCDomainId_t
domainNum	[IN] : Power domain number
moduleNum	[IN] : Module number
pscState	[IN] : PSC module state. See SOC_PSCModuleState_t

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_waitForFwlUnlock()

void SOC_waitForFwlUnlock ( void )

Wait for Firewall unlock from SBL. The function polls for a Software defined Magic number at the PSRAM location (Software defined)

◆ SOC_isHsDevice()

int32_t SOC_isHsDevice ( void )

Check the device is HS or not.

Returns: TRUE on success, else failure

◆ SOC_getFlashDataBaseAddr()

uint32_t SOC_getFlashDataBaseAddr ( void )

This function gets the SOC mapped data base address of the flash.

Returns: Data BaseAddress of the flash

◆ SOC_fixFastDriveStrength()

void SOC_fixFastDriveStrength ( void )

Fix fast mode drive strength.

Some devices have all drive strengths hardcoded to the nominal value. This function updates the drive strength registers on boot to the right values for fast drive strength. Only fast mode is supported and fixed.

Introduction

Functions

Macros

SOC Domain ID

SOC PSC Module State

SOC PSC Domain State

Macro Definition Documentation

◆ SOC_DOMAIN_ID_MAIN

◆ SOC_DOMAIN_ID_MCU

◆ SOC_PSC_DOMAIN_ID_MAIN

◆ SOC_PSC_DOMAIN_ID_MCU

◆ SOC_PSC_SYNCRESETDISABLE

◆ SOC_PSC_SYNCRESET

◆ SOC_PSC_DISABLE

◆ SOC_PSC_ENABLE

◆ SOC_PSC_DOMAIN_OFF

◆ SOC_PSC_DOMAIN_ON

◆ SOC_BOOTMODE_MMCSD

◆ SOC_H_IO_DRVSTRNGTH0

◆ SOC_H_IO_DRVSTRNGTH1

◆ SOC_V_IO_DRVSTRNGTH0

◆ SOC_V_IO_DRVSTRNGTH1

◆ SOC_IO_DRVSTRNGTH_MASK

◆ SOC_IO_DRVSTRNGTH_MAX

◆ SOC_FWL_OPEN_MAGIC_NUM

◆ MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE

◆ MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE

◆ MCU_UART0_BASE_AFTER_ADDR_TRANSLATE

◆ MCU_UART1_BASE_AFTER_ADDR_TRANSLATE

◆ MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE

◆ MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE

◆ IS_OSPI_BASE_ADDR_VALID

◆ IS_OSPI_DATA_BASE_ADDR_VALID

Function Documentation

◆ I2C_lld_isBaseAddrValid()

◆ MCSPI_lld_isBaseAddrValid()

◆ UART_IsBaseAddrValid()

◆ MMCSD_lld_isBaseAddrValid()

◆ SOC_moduleClockEnable()

◆ SOC_moduleSetClockFrequencyWithParent()

◆ SOC_moduleSetClockFrequency()

◆ SOC_moduleGetClockFrequency()

◆ SOC_getCoreName()

◆ SOC_getSelfCpuClk()

◆ SOC_controlModuleLockMMR()

◆ SOC_controlModuleUnlockMMR()

◆ SOC_setEpwmTbClk()

◆ SOC_allowEpwmTzReg()

◆ SOC_virtToPhy()

◆ SOC_phyToVirt()

◆ SOC_unlockAllMMR()

◆ SOC_setDevStat()

◆ SOC_isR5FDualCoreMode()

◆ SOC_generateSwWarmResetMainDomain()

◆ SOC_generateSwPORResetMainDomain()

◆ SOC_getWarmResetCauseMainDomain()

◆ SOC_generateSwWarmResetMcuDomain()

◆ SOC_generateSwWarmResetMainDomainFromMcuDomain()

◆ SOC_generateSwPORResetMainDomainFromMcuDomain()

◆ SOC_getWarmResetCauseMcuDomain()

◆ SOC_clearResetCauseMainMcuDomain()

◆ SOC_enableResetIsolation()

◆ SOC_setMCUResetIsolationDone()

◆ SOC_waitMainDomainReset()

◆ SOC_getPSCState()

◆ SOC_setPSCState()

◆ SOC_waitForFwlUnlock()

◆ SOC_isHsDevice()

◆ SOC_getFlashDataBaseAddr()

◆ SOC_fixFastDriveStrength()