Macros
#define	CSL_EPWM_PER_CNT (9U)
	Number of ePWM instances. More...

#define	CSL_CORE_R5F_INTR_MAX (256U)
	Maximum number of interrupts for r5f interrupts for this device. More...

#define	MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
	MCAN Maximum Message RAM words. More...

#define	MCAN_MAX_RX_DMA_BUFFERS (3U)
	Maximum number of Rx Dma buffers. More...

#define	MCAN_MAX_TX_DMA_BUFFERS (3U)
	Maximum number of Tx Dma buffers. More...

#define	MCSPI_DMA_IS_FIFO_SUPPORTED (0U)
	Whether FIFO is supported in MCSPI DMA MODE. More...

Core ID's of core or CPUs present on this SOC

#define	CSL_CORE_ID_M4FSS0_0 (0U)

#define	CSL_CORE_ID_R5FSS0_0 (1U)

#define	CSL_CORE_ID_R5FSS0_1 (2U)

#define	CSL_CORE_ID_R5FSS1_0 (3U)

#define	CSL_CORE_ID_R5FSS1_1 (4U)

#define	CSL_CORE_ID_A53SS0_0 (5U)

#define	CSL_CORE_ID_A53SS0_1 (6U)

#define	CSL_CORE_ID_MAX (7U)

R5 Cluster Group IDs

#define	CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
	R5 Cluster Group ID0. More...

#define	CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
	R5 Cluster Group ID1. More...

R5 Core IDs

#define	CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
	R5 Core ID0. More...

#define	CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
	R5 Core ID1. More...

Macro Definition Documentation

◆ CSL_CORE_ID_M4FSS0_0

#define CSL_CORE_ID_M4FSS0_0 (0U)

◆ CSL_CORE_ID_R5FSS0_0

#define CSL_CORE_ID_R5FSS0_0 (1U)

◆ CSL_CORE_ID_R5FSS0_1

#define CSL_CORE_ID_R5FSS0_1 (2U)

◆ CSL_CORE_ID_R5FSS1_0

#define CSL_CORE_ID_R5FSS1_0 (3U)

◆ CSL_CORE_ID_R5FSS1_1

#define CSL_CORE_ID_R5FSS1_1 (4U)

◆ CSL_CORE_ID_A53SS0_0

#define CSL_CORE_ID_A53SS0_0 (5U)

◆ CSL_CORE_ID_A53SS0_1

#define CSL_CORE_ID_A53SS0_1 (6U)

◆ CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX (7U)

◆ CSL_ARM_R5_CLUSTER_GROUP_ID_0

#define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)

R5 Cluster Group ID0.

◆ CSL_ARM_R5_CLUSTER_GROUP_ID_1

#define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)

R5 Cluster Group ID1.

◆ CSL_ARM_R5_CPU_ID_0

#define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)

R5 Core ID0.

◆ CSL_ARM_R5_CPU_ID_1

#define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)

R5 Core ID1.

◆ CSL_EPWM_PER_CNT

#define CSL_EPWM_PER_CNT (9U)

Number of ePWM instances.

◆ CSL_CORE_R5F_INTR_MAX

#define CSL_CORE_R5F_INTR_MAX (256U)

Maximum number of interrupts for r5f interrupts for this device.

◆ MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)

MCAN Maximum Message RAM words.

◆ MCAN_MAX_RX_DMA_BUFFERS

#define MCAN_MAX_RX_DMA_BUFFERS (3U)

Maximum number of Rx Dma buffers.

◆ MCAN_MAX_TX_DMA_BUFFERS

#define MCAN_MAX_TX_DMA_BUFFERS (3U)

Maximum number of Tx Dma buffers.

◆ MCSPI_DMA_IS_FIFO_SUPPORTED

#define MCSPI_DMA_IS_FIFO_SUPPORTED (0U)

Whether FIFO is supported in MCSPI DMA MODE.

Macros