Introduction

PCIE Driver API/interface file.

Data Structures
struct	Pcie_DeviceCfgBaseAddr
	The Pcie_DeviceCfg is used to specify device level configuration of the driver instance. More...

struct	Pcie_ObAtuCfg
	Pcie_ObAtuCfg specifies the Outbound ATU configurations for PCIe. More...

struct	Pcie_IbAtuCfg
	Pcie_IbAtuCfg specifies the Inbound ATU configurations for PCIe. More...

struct	Pcie_RegisterMsiIsrParams
	Pcie_RegisterMsiIsrParams specifies the parameters to register an ISR for MSI. More...

struct	Pcie_RegisterMsixIsrParams
	Pcie_RegisterMsixIsrParams specifies the parameters to register an ISR for MSIX. More...

struct	Pcie_MsiIsrCtrl
	PCIe MSI Isr control structure. More...

struct	Pcie_MsixIsrCtrl
	ISR and arguement list for MSIx. More...

struct	Pcie_MsixTblEntry
	PCIe MSIx table entry. More...

struct	Pcie_MsixTbl

struct	Pcie_Attrs
	PCIe atributes. More...

struct	Pcie_Object
	PCIe driver object. More...

struct	Pcie_DeviceCfg
	PCIe device configuration. More...

struct	Pcie_InitCfg
	PCIe configuration for initalization. More...

struct	Pcie_Config
	PCIE global configuration array. More...

struct	Pcie_BarCfg
	PCIe BAR configuration info. More...

struct	Pcie_IbTransCfg
	Inbound traslation configuration info The Pcie_IbTransCfg is used to configure the Inbound Translation Registers. More...

struct	Pcie_AtuRegionParams
	This Structure defines the ATU region parameters. More...

Macros
#define	PCIE_MAX_PERIPHS (4U)
	Maximum PCIe devices supported by the driver. More...

#define	PCIE_MAX_MSI_IRQ (32U)
	Maximum PCIe MSI interrupts supported. More...

#define	PCIE_MAX_MSIX_IRQ (2048U)
	Maxmium number of MSIx interrupts supported. More...

#define	PCIE_MAX_NUM_IBATU (6U)
	Maximum number of configurable Inbound ATUs. More...

Typedefs
typedef void *	Pcie_Handle
	Driver handle returned by Pcie_open() call. More...

typedef void(*	Pcie_MsiIsr) (void *arg, uint32_t msiData)
	Function pointer for the PCIe MSI ISR. More...

typedef void(*	Pcie_MsixIsr) (void *arg, uint32_t msixData)
	Function pointer for the PCIe MSIx ISR. More...

Enumerations
enum	Pcie_Mode { PCIE_EP_MODE = 0, PCIE_LEGACY_EP_MODE, PCIE_RC_MODE }
	These are the possible values for PCIe mode. More...

enum	Pcie_Gen { PCIE_GEN1 = 1, PCIE_GEN2 = 2, PCIE_GEN3 = 3 }
	Enumeration for PCIE generations. More...

enum	Pcie_RefClk_Mode { PCIE_REFCLK_MODE_INT_NOSSC_OUTDIS = 1, PCIE_REFCLK_MODE_INT_SSC_OUTDIS = 2, PCIE_REFCLK_MODE_INT_NOSSC_OUTEN = 3, PCIE_REFCLK_MODE_INT_SSC_OUTEN = 4, PCIE_REFCLK_MODE_EXT_NOSSC = 5, PCIE_REFCLK_MODE_EXT_SSC = 6 }
	Enumeration for PCIe Reference Clock mode. More...

enum	Pcie_SRIS_Mode { PCIE_REFCLK_SRIS_DISABLED = 0, PCIE_REFCLK_SRIS_ENABLED = 1 }
	Enumeration for PCIe SRIS mode. More...

enum	Pcie_PwrState { PCIE_PWR_STATE_D0 = 0, PCIE_PWR_STATE_D1 = 1, PCIE_PWR_STATE_D3hot = 2 }
	Enumeration for PCIE Power State. More...

enum	Pcie_IntPin { PCIE_INT_PINNONE = 0, PCIE_INT_PINA = 1, PCIE_INT_PINB = 2, PCIE_INT_PINC = 3, PCIE_INT_PIND = 4 }
	Enumeration for PCIE Legacy Interrupt Pin. More...

enum	Pcie_BarPref { PCIE_BAR_NON_PREF = 0, PCIE_BAR_PREF }
	These are the possible values for Prefetch BAR configuration. More...

enum	Pcie_BarType { PCIE_BAR_TYPE32 = 0, PCIE_BAR_RSVD, PCIE_BAR_TYPE64 }
	These are the possible values for Type BAR configuration. More...

enum	Pcie_BarMem { PCIE_BAR_MEM_MEM = 0, PCIE_BAR_MEM_IO }
	These are the possible values for Memory BAR configuration. More...

enum	Pcie_AtuRegionDir { PCIE_ATU_REGION_DIR_OUTBOUND, PCIE_ATU_REGION_DIR_INBOUND }
	Enum to select PCIe ATU(Address translation unit) region direction(Inbound or Outbound). This enum is used while configuring inbound or outbound region. More...

enum	Pcie_TlpType { PCIE_TLP_TYPE_MEM, PCIE_TLP_TYPE_IO, PCIE_TLP_TYPE_CFG }
	This enum is used to select PCIe TLP(Transaction layer packet) type while configuring inbound or outbound region. More...

enum	Pcie_AtuRegionMatchMode { PCIE_ATU_REGION_MATCH_MODE_ADDR, PCIE_ATU_REGION_MATCH_MODE_BAR }
	Enum to select address or BAR match mode. More...

enum	Pcie_Location { PCIE_LOCATION_LOCAL, PCIE_LOCATION_REMOTE }
	Enumeration for PCIe access type remote/local. More...

enum	Pcie_LtssmState { PCIE_LTSSM_DETECT_QUIET =0, PCIE_LTSSM_DETECT_ACT, PCIE_LTSSM_POLL_ACTIVE, PCIE_LTSSM_POLL_COMPLIANCE, PCIE_LTSSM_POLL_CONFIG, PCIE_LTSSM_PRE_DETECT_QUIET, PCIE_LTSSM_DETECT_WAIT, PCIE_LTSSM_CFG_LINKWD_START, PCIE_LTSSM_CFG_LINKWD_ACEPT, PCIE_LTSSM_CFG_LANENUM_WAIT, PCIE_LTSSM_CFG_LANENUM_ACEPT, PCIE_LTSSM_CFG_COMPLETE, PCIE_LTSSM_CFG_IDLE, PCIE_LTSSM_RCVRY_LOCK, PCIE_LTSSM_RCVRY_SPEED, PCIE_LTSSM_RCVRY_RCVRCFG, PCIE_LTSSM_RCVRY_IDLE, PCIE_LTSSM_L0, PCIE_LTSSM_L0S, PCIE_LTSSM_L123_SEND_EIDLE, PCIE_LTSSM_L1_IDLE, PCIE_LTSSM_L2_IDLE, PCIE_LTSSM_L2_WAKE, PCIE_LTSSM_DISABLED_ENTRY, PCIE_LTSSM_DISABLED_IDLE, PCIE_LTSSM_DISABLED, PCIE_LTSSM_LPBK_ENTRY, PCIE_LTSSM_LPBK_ACTIVE, PCIE_LTSSM_LPBK_EXIT, PCIE_LTSSM_LPBK_EXIT_TIMEOUT, PCIE_LTSSM_HOT_RESET_ENTRY, PCIE_LTSSM_HOT_RESET, PCIE_LTSSM_RCVRY_EQ0, PCIE_LTSSM_RCVRY_EQ1, PCIE_LTSSM_RCVRY_EQ2, PCIE_LTSSM_RCVRY_EQ3 }
	Enumeration for possible values for encoding LTSSM state. More...

Functions
void	Pcie_init (void)
	This function initializes the PCIe module. More...

Pcie_Handle	Pcie_open (uint32_t index)
	This function opens a given PCIe peripheral. More...

void	Pcie_close (Pcie_Handle handle)
	Function to close PCIe peripheral specified by PCIe handle. More...

Pcie_DeviceCfgBaseAddr *	Pcie_handleGetBases (Pcie_Handle handle)
	Get the device base address info for the PCIe peripheral. More...

int32_t	Pcie_setInterfaceMode (Pcie_Handle handle, Pcie_Mode mode, Pcie_Gen gen)
	Set interfac mode (RC/EP) More...

int32_t	Pcie_getMemSpaceReserved (Pcie_Handle handle, uint32_t *resSize)
	Pcie_getMemSpaceReserved returns amount of reserved space between beginning of hardware's data area and the base returned by Pcie_getMemSpaceRange. More...

int32_t	Pcie_getMemSpaceRange (Pcie_Handle handle, void *base, uint32_t size)
	Returns the PCIe Internal Address Range for the memory space. This range is used for accessing memory. More...

int32_t	Pcie_cfgBar (Pcie_Handle handle, const Pcie_BarCfg *barCfg)
	Configure a BAR Register (32 bits) More...

int32_t	Pcie_atuRegionConfig (Pcie_Handle handle, Pcie_Location location, uint32_t atuRegionIndex, const Pcie_AtuRegionParams *atuRegionParams)
	Configure address translation registers. More...

int32_t	Pcie_getVendorId (Pcie_Handle handle, Pcie_Location location, uint32_t vendorId, uint32_t deviceId)
	Get vendor ID and device ID of Pcie Device. More...

int32_t	Pcie_getPwrState (Pcie_Handle handle, Pcie_PwrState *pwrState)
	Get current PCIe Power State. More...

int32_t	Pcie_getLinkParams (Pcie_Handle handle, Pcie_Gen gen, uint32_t numLanes)
	Get current PCIe Link Parameter. More...

int32_t	Pcie_isLinkUp (Pcie_Handle handle)
	Check if PCIe link training completed. More...

int32_t	Pcie_waitLinkUp (Pcie_Handle handle)
	Wait for PCIe link training to complete. More...

int32_t	Pcie_checkLinkParams (Pcie_Handle handle)
	Verify if the link parameters is established as configured. More...

int32_t	Pcie_LtssmCtrl (Pcie_Handle handle, uint8_t enable)
	Enable/disable PCIe link training. More...

int32_t	Pcie_setLanes (Pcie_Handle handle)
	Set number of PCIe lanes as configured. More...

int32_t	Pcie_cfgEP (Pcie_Handle handle)
	Configure Pcie for EP (End Point) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMode) More...

int32_t	Pcie_cfgRC (Pcie_Handle handle)
	Configure Pcie for RC (Root Complex) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMode) More...

int32_t	Pcie_setCfgEn (Pcie_Handle handle, int enable)
	Set CONFIG_ENABLE to signal RC that the local EP configuration is completed. More...

int32_t	Pcie_setSlotClockCnfg (Pcie_Handle handle, int enable)
	Set slot clock configuration bit in Link Status Register. More...

int32_t	Pcie_setDwnStrIrq (Pcie_Handle handle, int enable)
	Enable downstream interrupt in PCIE Controller. More...

int32_t	Pcie_setLnkDwnStateIrq (Pcie_Handle handle, int enable)
	Enable link down status interrupt in PCIE Controller. More...

int32_t	Pcie_setPwrStateIrq (Pcie_Handle handle, int enable)
	Enable power management state interrupt in PCIE Controller. More...

int32_t	Pcie_setHotResetIrq (Pcie_Handle handle, int enable)
	Enable hot reset interrupt in PCIE Controller. More...

int32_t	Pcie_ackDwnStrIrq (Pcie_Handle handle)
	Acknowledge downstream interrupt. More...

int32_t	Pcie_ackLnkDwnStateIrq (Pcie_Handle handle)
	Acknowledge link down status interrupt. More...

int32_t	Pcie_ackPwrStateIrq (Pcie_Handle handle)
	Acknowledge power management state interrupt. More...

Variables
Pcie_Config	gPcieConfig []
	Externally defined driver configuration array. More...

uint32_t	gPcieConfigNum
	Externally defined driver configuration array size. More...

Introduction

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables