Introduction

This module contains APIs to program and use the PCIE module. The APIs can be used by other drivers to get access to PCIE and also by applications

Files
file	pcie/pcie.h
	PCIE Driver API/interface file.

Data Structures
struct	Pcie_DeviceCfgBaseAddr
	The Pcie_DeviceCfg is used to specify device level configuration of the driver instance. More...

struct	Pcie_ObAtuCfg
	Pcie_ObAtuCfg specifies the Outbound ATU configurations for PCIe. More...

struct	Pcie_IbAtuCfg
	Pcie_IbAtuCfg specifies the Inbound ATU configurations for PCIe. More...

struct	Pcie_RegisterMsiIsrParams
	Pcie_RegisterMsiIsrParams specifies the parameters to register an ISR for MSI. More...

struct	Pcie_RegisterMsixIsrParams
	Pcie_RegisterMsixIsrParams specifies the parameters to register an ISR for MSIX. More...

struct	Pcie_MsiIsrCtrl
	PCIe MSI Isr control structure. More...

struct	Pcie_MsixIsrCtrl
	ISR and arguement list for MSIx. More...

struct	Pcie_MsixTblEntry
	PCIe MSIx table entry. More...

struct	Pcie_MsixTbl

struct	Pcie_Attrs
	PCIe atributes. More...

struct	Pcie_Object
	PCIe driver object. More...

struct	Pcie_DeviceCfg
	PCIe device configuration. More...

struct	Pcie_InitCfg
	PCIe configuration for initalization. More...

struct	Pcie_Config
	PCIE global configuration array. More...

struct	Pcie_BarCfg
	PCIe BAR configuration info. More...

struct	Pcie_IbTransCfg
	Inbound traslation configuration info The Pcie_IbTransCfg is used to configure the Inbound Translation Registers. More...

struct	Pcie_AtuRegionParams
	This Structure defines the ATU region parameters. More...

Functions
void	Pcie_init (void)
	This function initializes the PCIe module. More...

Pcie_Handle	Pcie_open (uint32_t index)
	This function opens a given PCIe peripheral. More...

void	Pcie_close (Pcie_Handle handle)
	Function to close PCIe peripheral specified by PCIe handle. More...

Pcie_DeviceCfgBaseAddr *	Pcie_handleGetBases (Pcie_Handle handle)
	Get the device base address info for the PCIe peripheral. More...

int32_t	Pcie_setInterfaceMode (Pcie_Handle handle, Pcie_Mode mode, Pcie_Gen gen)
	Set interfac mode (RC/EP) More...

int32_t	Pcie_getMemSpaceReserved (Pcie_Handle handle, uint32_t *resSize)
	Pcie_getMemSpaceReserved returns amount of reserved space between beginning of hardware's data area and the base returned by Pcie_getMemSpaceRange. More...

int32_t	Pcie_getMemSpaceRange (Pcie_Handle handle, void *base, uint32_t size)
	Returns the PCIe Internal Address Range for the memory space. This range is used for accessing memory. More...

int32_t	Pcie_cfgBar (Pcie_Handle handle, const Pcie_BarCfg *barCfg)
	Configure a BAR Register (32 bits) More...

int32_t	Pcie_atuRegionConfig (Pcie_Handle handle, Pcie_Location location, uint32_t atuRegionIndex, const Pcie_AtuRegionParams *atuRegionParams)
	Configure address translation registers. More...

int32_t	Pcie_getVendorId (Pcie_Handle handle, Pcie_Location location, uint32_t vendorId, uint32_t deviceId)
	Get vendor ID and device ID of Pcie Device. More...

int32_t	Pcie_getPwrState (Pcie_Handle handle, Pcie_PwrState *pwrState)
	Get current PCIe Power State. More...

int32_t	Pcie_getLinkParams (Pcie_Handle handle, Pcie_Gen gen, uint32_t numLanes)
	Get current PCIe Link Parameter. More...

int32_t	Pcie_isLinkUp (Pcie_Handle handle)
	Check if PCIe link training completed. More...

int32_t	Pcie_waitLinkUp (Pcie_Handle handle)
	Wait for PCIe link training to complete. More...

int32_t	Pcie_checkLinkParams (Pcie_Handle handle)
	Verify if the link parameters is established as configured. More...

int32_t	Pcie_LtssmCtrl (Pcie_Handle handle, uint8_t enable)
	Enable/disable PCIe link training. More...

int32_t	Pcie_setLanes (Pcie_Handle handle)
	Set number of PCIe lanes as configured. More...

int32_t	Pcie_cfgEP (Pcie_Handle handle)
	Configure Pcie for EP (End Point) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMode) More...

int32_t	Pcie_cfgRC (Pcie_Handle handle)
	Configure Pcie for RC (Root Complex) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMode) More...

int32_t	Pcie_setCfgEn (Pcie_Handle handle, int enable)
	Set CONFIG_ENABLE to signal RC that the local EP configuration is completed. More...

int32_t	Pcie_setSlotClockCnfg (Pcie_Handle handle, int enable)
	Set slot clock configuration bit in Link Status Register. More...

int32_t	Pcie_setDwnStrIrq (Pcie_Handle handle, int enable)
	Enable downstream interrupt in PCIE Controller. More...

int32_t	Pcie_setLnkDwnStateIrq (Pcie_Handle handle, int enable)
	Enable link down status interrupt in PCIE Controller. More...

int32_t	Pcie_setPwrStateIrq (Pcie_Handle handle, int enable)
	Enable power management state interrupt in PCIE Controller. More...

int32_t	Pcie_setHotResetIrq (Pcie_Handle handle, int enable)
	Enable hot reset interrupt in PCIE Controller. More...

int32_t	Pcie_ackDwnStrIrq (Pcie_Handle handle)
	Acknowledge downstream interrupt. More...

int32_t	Pcie_ackLnkDwnStateIrq (Pcie_Handle handle)
	Acknowledge link down status interrupt. More...

int32_t	Pcie_ackPwrStateIrq (Pcie_Handle handle)
	Acknowledge power management state interrupt. More...

Typedefs
typedef void *	Pcie_Handle
	Driver handle returned by Pcie_open() call. More...

typedef void(*	Pcie_MsiIsr) (void *arg, uint32_t msiData)
	Function pointer for the PCIe MSI ISR. More...

typedef void(*	Pcie_MsixIsr) (void *arg, uint32_t msixData)
	Function pointer for the PCIe MSIx ISR. More...

Enumerations
enum	Pcie_Mode { PCIE_EP_MODE = 0, PCIE_LEGACY_EP_MODE, PCIE_RC_MODE }
	These are the possible values for PCIe mode. More...

enum	Pcie_Gen { PCIE_GEN1 = 1, PCIE_GEN2 = 2, PCIE_GEN3 = 3 }
	Enumeration for PCIE generations. More...

enum	Pcie_RefClk_Mode { PCIE_REFCLK_MODE_INT_NOSSC_OUTDIS = 1, PCIE_REFCLK_MODE_INT_SSC_OUTDIS = 2, PCIE_REFCLK_MODE_INT_NOSSC_OUTEN = 3, PCIE_REFCLK_MODE_INT_SSC_OUTEN = 4, PCIE_REFCLK_MODE_EXT_NOSSC = 5, PCIE_REFCLK_MODE_EXT_SSC = 6 }
	Enumeration for PCIe Reference Clock mode. More...

enum	Pcie_SRIS_Mode { PCIE_REFCLK_SRIS_DISABLED = 0, PCIE_REFCLK_SRIS_ENABLED = 1 }
	Enumeration for PCIe SRIS mode. More...

enum	Pcie_PwrState { PCIE_PWR_STATE_D0 = 0, PCIE_PWR_STATE_D1 = 1, PCIE_PWR_STATE_D3hot = 2 }
	Enumeration for PCIE Power State. More...

enum	Pcie_IntPin { PCIE_INT_PINNONE = 0, PCIE_INT_PINA = 1, PCIE_INT_PINB = 2, PCIE_INT_PINC = 3, PCIE_INT_PIND = 4 }
	Enumeration for PCIE Legacy Interrupt Pin. More...

enum	Pcie_BarPref { PCIE_BAR_NON_PREF = 0, PCIE_BAR_PREF }
	These are the possible values for Prefetch BAR configuration. More...

enum	Pcie_BarType { PCIE_BAR_TYPE32 = 0, PCIE_BAR_RSVD, PCIE_BAR_TYPE64 }
	These are the possible values for Type BAR configuration. More...

enum	Pcie_BarMem { PCIE_BAR_MEM_MEM = 0, PCIE_BAR_MEM_IO }
	These are the possible values for Memory BAR configuration. More...

enum	Pcie_AtuRegionDir { PCIE_ATU_REGION_DIR_OUTBOUND, PCIE_ATU_REGION_DIR_INBOUND }
	Enum to select PCIe ATU(Address translation unit) region direction(Inbound or Outbound). This enum is used while configuring inbound or outbound region. More...

enum	Pcie_TlpType { PCIE_TLP_TYPE_MEM, PCIE_TLP_TYPE_IO, PCIE_TLP_TYPE_CFG }
	This enum is used to select PCIe TLP(Transaction layer packet) type while configuring inbound or outbound region. More...

enum	Pcie_AtuRegionMatchMode { PCIE_ATU_REGION_MATCH_MODE_ADDR, PCIE_ATU_REGION_MATCH_MODE_BAR }
	Enum to select address or BAR match mode. More...

enum	Pcie_Location { PCIE_LOCATION_LOCAL, PCIE_LOCATION_REMOTE }
	Enumeration for PCIe access type remote/local. More...

enum	Pcie_LtssmState { PCIE_LTSSM_DETECT_QUIET =0, PCIE_LTSSM_DETECT_ACT, PCIE_LTSSM_POLL_ACTIVE, PCIE_LTSSM_POLL_COMPLIANCE, PCIE_LTSSM_POLL_CONFIG, PCIE_LTSSM_PRE_DETECT_QUIET, PCIE_LTSSM_DETECT_WAIT, PCIE_LTSSM_CFG_LINKWD_START, PCIE_LTSSM_CFG_LINKWD_ACEPT, PCIE_LTSSM_CFG_LANENUM_WAIT, PCIE_LTSSM_CFG_LANENUM_ACEPT, PCIE_LTSSM_CFG_COMPLETE, PCIE_LTSSM_CFG_IDLE, PCIE_LTSSM_RCVRY_LOCK, PCIE_LTSSM_RCVRY_SPEED, PCIE_LTSSM_RCVRY_RCVRCFG, PCIE_LTSSM_RCVRY_IDLE, PCIE_LTSSM_L0, PCIE_LTSSM_L0S, PCIE_LTSSM_L123_SEND_EIDLE, PCIE_LTSSM_L1_IDLE, PCIE_LTSSM_L2_IDLE, PCIE_LTSSM_L2_WAKE, PCIE_LTSSM_DISABLED_ENTRY, PCIE_LTSSM_DISABLED_IDLE, PCIE_LTSSM_DISABLED, PCIE_LTSSM_LPBK_ENTRY, PCIE_LTSSM_LPBK_ACTIVE, PCIE_LTSSM_LPBK_EXIT, PCIE_LTSSM_LPBK_EXIT_TIMEOUT, PCIE_LTSSM_HOT_RESET_ENTRY, PCIE_LTSSM_HOT_RESET, PCIE_LTSSM_RCVRY_EQ0, PCIE_LTSSM_RCVRY_EQ1, PCIE_LTSSM_RCVRY_EQ2, PCIE_LTSSM_RCVRY_EQ3 }
	Enumeration for possible values for encoding LTSSM state. More...

Macros
#define	PCIE_MAX_PERIPHS (4U)
	Maximum PCIe devices supported by the driver. More...

#define	PCIE_MAX_MSI_IRQ (32U)
	Maximum PCIe MSI interrupts supported. More...

#define	PCIE_MAX_MSIX_IRQ (2048U)
	Maxmium number of MSIx interrupts supported. More...

#define	PCIE_MAX_NUM_IBATU (6U)
	Maximum number of configurable Inbound ATUs. More...

Macro Definition Documentation

◆ PCIE_MAX_PERIPHS

#define PCIE_MAX_PERIPHS (4U)

Maximum PCIe devices supported by the driver.

◆ PCIE_MAX_MSI_IRQ

#define PCIE_MAX_MSI_IRQ (32U)

Maximum PCIe MSI interrupts supported.

◆ PCIE_MAX_MSIX_IRQ

#define PCIE_MAX_MSIX_IRQ (2048U)

Maxmium number of MSIx interrupts supported.

◆ PCIE_MAX_NUM_IBATU

#define PCIE_MAX_NUM_IBATU (6U)

Maximum number of configurable Inbound ATUs.

Typedef Documentation

◆ Pcie_Handle

typedef void* Pcie_Handle

Driver handle returned by Pcie_open() call.

◆ Pcie_MsiIsr

typedef void(* Pcie_MsiIsr) (void *arg, uint32_t msiData)

Function pointer for the PCIe MSI ISR.

◆ Pcie_MsixIsr

typedef void(* Pcie_MsixIsr) (void *arg, uint32_t msixData)

Function pointer for the PCIe MSIx ISR.

Enumeration Type Documentation

◆ Pcie_Mode

enum Pcie_Mode

These are the possible values for PCIe mode.

Enumerator
PCIE_EP_MODE	Required when setting the PCIe Mode to End Point using the Pcie_setInterfaceMode function
PCIE_LEGACY_EP_MODE	Required when setting the PCIe Mode to Legacy End Point using the Pcie_setInterfaceMode function
PCIE_RC_MODE	Required when setting the PCIe Mode to Root Complex using the Pcie_setInterfaceMode function

◆ Pcie_Gen

enum Pcie_Gen

Enumeration for PCIE generations.

Enumerator
PCIE_GEN1	PCIe Gen1 for 2.5 GT/s speed
PCIE_GEN2	PCIe Gen2 for 5.0 GT/s speed
PCIE_GEN3	PCIe Gen3 for 8.0 GT/s speed

◆ Pcie_RefClk_Mode

enum Pcie_RefClk_Mode

Enumeration for PCIe Reference Clock mode.

Enumerator
PCIE_REFCLK_MODE_INT_NOSSC_OUTDIS
PCIE_REFCLK_MODE_INT_SSC_OUTDIS	Internal Reference Clock with no SSC and Output disabled
PCIE_REFCLK_MODE_INT_NOSSC_OUTEN	Internal Reference Clock with SSC and Output disabled
PCIE_REFCLK_MODE_INT_SSC_OUTEN	Internal Reference Clock with no SSC and Output enabled
PCIE_REFCLK_MODE_EXT_NOSSC	Internal Reference Clock with SSC and Output enabled
PCIE_REFCLK_MODE_EXT_SSC	External Reference Clock with no SSC

◆ Pcie_SRIS_Mode

enum Pcie_SRIS_Mode

Enumeration for PCIe SRIS mode.

Enumerator
PCIE_REFCLK_SRIS_DISABLED
PCIE_REFCLK_SRIS_ENABLED	SRIS disabled

◆ Pcie_PwrState

enum Pcie_PwrState

Enumeration for PCIE Power State.

Enumerator
PCIE_PWR_STATE_D0	PCIe Power State D0
PCIE_PWR_STATE_D1	PCIe Power State D1
PCIE_PWR_STATE_D3hot	PCIe Power State D3hot

◆ Pcie_IntPin

enum Pcie_IntPin

Enumeration for PCIE Legacy Interrupt Pin.

Enumerator
PCIE_INT_PINNONE	Pcie Legacy Interrupt Pin None
PCIE_INT_PINA	Pcie Legacy Interrupt Pin A
PCIE_INT_PINB	Pcie Legacy Interrupt Pin B
PCIE_INT_PINC	Pcie Legacy Interrupt Pin C
PCIE_INT_PIND	Pcie Legacy Interrupt Pin D

◆ Pcie_BarPref

enum Pcie_BarPref

These are the possible values for Prefetch BAR configuration.

Enumerator
PCIE_BAR_NON_PREF	Non Prefetchable Region
PCIE_BAR_PREF	Prefetchable Region

◆ Pcie_BarType

enum Pcie_BarType

These are the possible values for Type BAR configuration.

Enumerator
PCIE_BAR_TYPE32	32 bits BAR
PCIE_BAR_RSVD	Reserved
PCIE_BAR_TYPE64	64 bits BAR

◆ Pcie_BarMem

enum Pcie_BarMem

These are the possible values for Memory BAR configuration.

Enumerator
PCIE_BAR_MEM_MEM	Memory BAR
PCIE_BAR_MEM_IO	IO BAR

◆ Pcie_AtuRegionDir

enum Pcie_AtuRegionDir

Enum to select PCIe ATU(Address translation unit) region direction(Inbound or Outbound). This enum is used while configuring inbound or outbound region.

Enumerator
PCIE_ATU_REGION_DIR_OUTBOUND	Select PCIe outbound region.
PCIE_ATU_REGION_DIR_INBOUND	Select PCIe inbound region.

◆ Pcie_TlpType

enum Pcie_TlpType

This enum is used to select PCIe TLP(Transaction layer packet) type while configuring inbound or outbound region.

Enumerator
PCIE_TLP_TYPE_MEM	MEM type is selected while doing memory transfer
PCIE_TLP_TYPE_IO	IO type is selected while doing I/O transfer
PCIE_TLP_TYPE_CFG	CFG type is selected while doing configuration access

◆ Pcie_AtuRegionMatchMode

enum Pcie_AtuRegionMatchMode

Enum to select address or BAR match mode.

Enumerator
PCIE_ATU_REGION_MATCH_MODE_ADDR	Inbound packets are filtered by address match mode
PCIE_ATU_REGION_MATCH_MODE_BAR	Inbound packets are filtered by BAR match mode

◆ Pcie_Location

enum Pcie_Location

Enumeration for PCIe access type remote/local.

Selects whether to read/write local or remote PCIe registers. PCIe configuration registers are accessible locally and remotely

For PCIe application registers the access is always local

Enumerator
PCIE_LOCATION_LOCAL	Access the local PCIe peripheral
PCIE_LOCATION_REMOTE	Access the remote PCIe peripheral

◆ Pcie_LtssmState

enum Pcie_LtssmState

Enumeration for possible values for encoding LTSSM state.

Enumerator
PCIE_LTSSM_DETECT_QUIET	0x00
PCIE_LTSSM_DETECT_ACT	0x01
PCIE_LTSSM_POLL_ACTIVE	0x02
PCIE_LTSSM_POLL_COMPLIANCE	0x03
PCIE_LTSSM_POLL_CONFIG	0x04
PCIE_LTSSM_PRE_DETECT_QUIET	0x05
PCIE_LTSSM_DETECT_WAIT	0x06
PCIE_LTSSM_CFG_LINKWD_START	0x07
PCIE_LTSSM_CFG_LINKWD_ACEPT	0x08
PCIE_LTSSM_CFG_LANENUM_WAIT	0x09
PCIE_LTSSM_CFG_LANENUM_ACEPT	0x0a
PCIE_LTSSM_CFG_COMPLETE	0x0b
PCIE_LTSSM_CFG_IDLE	0x0c
PCIE_LTSSM_RCVRY_LOCK	0x0d
PCIE_LTSSM_RCVRY_SPEED	0x0e
PCIE_LTSSM_RCVRY_RCVRCFG	0x0f
PCIE_LTSSM_RCVRY_IDLE	0x10
PCIE_LTSSM_L0	0x11
PCIE_LTSSM_L0S	0x12
PCIE_LTSSM_L123_SEND_EIDLE	0x13
PCIE_LTSSM_L1_IDLE	0x14
PCIE_LTSSM_L2_IDLE	0x15
PCIE_LTSSM_L2_WAKE	0x16
PCIE_LTSSM_DISABLED_ENTRY	0x17
PCIE_LTSSM_DISABLED_IDLE	0x18
PCIE_LTSSM_DISABLED	0x19
PCIE_LTSSM_LPBK_ENTRY	0x1a
PCIE_LTSSM_LPBK_ACTIVE	0x1b
PCIE_LTSSM_LPBK_EXIT	0x1c
PCIE_LTSSM_LPBK_EXIT_TIMEOUT	0x1d
PCIE_LTSSM_HOT_RESET_ENTRY	0x1e
PCIE_LTSSM_HOT_RESET	0x1f
PCIE_LTSSM_RCVRY_EQ0	0x20
PCIE_LTSSM_RCVRY_EQ1	0x21
PCIE_LTSSM_RCVRY_EQ2	0x22
PCIE_LTSSM_RCVRY_EQ3	0x23

Function Documentation

◆ Pcie_init()

void Pcie_init ( void )

This function initializes the PCIe module.

◆ Pcie_open()

Pcie_Handle Pcie_open ( uint32_t index )

This function opens a given PCIe peripheral.

Precondition: PCIe controlled has been initialized using Pcie_init()

Parameters

index Index of config to use in the Pcie_config array

Returns: A Pcie_Handle on success or a NULL on an error or if it has been opened already

◆ Pcie_close()

void Pcie_close ( Pcie_Handle handle )

Function to close PCIe peripheral specified by PCIe handle.

Precondition: Pcie_open() has to be called first

Parameters

handle Pcie_Handle retuned from Pcie_open()

◆ Pcie_handleGetBases()

Pcie_DeviceCfgBaseAddr* Pcie_handleGetBases ( Pcie_Handle handle )

Get the device base address info for the PCIe peripheral.

Parameters

handle Pcie_Handle returned from Pcie_open()

Returns: Pointer to the base address info structure if success, else returns NULL

◆ Pcie_setInterfaceMode()

int32_t Pcie_setInterfaceMode	(	Pcie_Handle	handle,
		Pcie_Mode	mode,
		Pcie_Gen	gen
	)

Set interfac mode (RC/EP)

Parameters

handle	Pcie_Handle for the instance
mode	Interface mode (EP/EC)
gen	PCIe operation speed

Returns: SystemP_SUCCESS on successful; else error on failure

◆ Pcie_getMemSpaceReserved()

int32_t Pcie_getMemSpaceReserved	(	Pcie_Handle	handle,
		uint32_t *	resSize
	)

Pcie_getMemSpaceReserved returns amount of reserved space between beginning of hardware's data area and the base returned by Pcie_getMemSpaceRange.

Parameters

handle	Pcie_Handle for the instance
resSize	Pointer to return reserved space

Return values

SystemP_SUCCESS on successful; else error on failure

◆ Pcie_getMemSpaceRange()

int32_t Pcie_getMemSpaceRange	(	Pcie_Handle	handle,
		void **	base,
		uint32_t *	size
	)

Returns the PCIe Internal Address Range for the memory space. This range is used for accessing memory.

Parameters

handle	Pcie_Handle for the instance
base	Pointer to return base address
size	Pointer to return size

Returns: SystemP_SUCCESS on successful; else error on failure

◆ Pcie_cfgBar()

int32_t Pcie_cfgBar	(	Pcie_Handle	handle,
		const Pcie_BarCfg *	barCfg
	)

Configure a BAR Register (32 bits)

Parameters

handle	Pcie_Handle for the instance
barCfg	Bar configuration parameters

Returns: SystemP_SUCCESS on successful; else error on failure

◆ Pcie_atuRegionConfig()

int32_t Pcie_atuRegionConfig	(	Pcie_Handle	handle,
		Pcie_Location	location,
		uint32_t	atuRegionIndex,
		const Pcie_AtuRegionParams *	atuRegionParams
	)

Configure address translation registers.

Parameters

handle	Pcie_Handle for the instance
location	Local or remote configuration space
atuRegionIndex	Address translation region index
atuRegionParams	Address translation region parameters

Returns: SystemP_SUCCESS on successful; else error on failure

◆ Pcie_getVendorId()

int32_t Pcie_getVendorId	(	Pcie_Handle	handle,
		Pcie_Location	location,
		uint32_t *	vendorId,
		uint32_t *	deviceId
	)

Get vendor ID and device ID of Pcie Device.

Parameters

handle	Pcie_Handle returned by Pcie_open()
location	Local or remote configuration space
vendorId	Pointer to return vendor ID
deviceId	Pointer to return device ID

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_getPwrState()

int32_t Pcie_getPwrState	(	Pcie_Handle	handle,
		Pcie_PwrState *	pwrState
	)

Get current PCIe Power State.

Parameters

handle	Pcie_Handle returned by Pcie_open()
pwrState	Pointer to return PCIe Power State

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_getLinkParams()

int32_t Pcie_getLinkParams	(	Pcie_Handle	handle,
		Pcie_Gen *	gen,
		uint32_t *	numLanes
	)

Get current PCIe Link Parameter.

Parameters

handle	Pcie_Handle returned by Pcie_open()
gen	Pointer to return PCIe operation speed
numLanes	Pointer to return Number of lanes for the instance

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_isLinkUp()

int32_t Pcie_isLinkUp ( Pcie_Handle handle )

Check if PCIe link training completed.

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_waitLinkUp()

int32_t Pcie_waitLinkUp ( Pcie_Handle handle )

Wait for PCIe link training to complete.

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_checkLinkParams()

int32_t Pcie_checkLinkParams ( Pcie_Handle handle )

Verify if the link parameters is established as configured.

Precondition: Link training needs to be completed

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_LtssmCtrl()

int32_t Pcie_LtssmCtrl	(	Pcie_Handle	handle,
		uint8_t	enable
	)

Enable/disable PCIe link training.

Parameters

handle	Pcie_Handle returned by Pcie_open()
enable	Enable(1) / disable (0) link training

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setLanes()

int32_t Pcie_setLanes ( Pcie_Handle handle )

Set number of PCIe lanes as configured.

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_cfgEP()

int32_t Pcie_cfgEP ( Pcie_Handle handle )

Configure Pcie for EP (End Point) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMode)

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_cfgRC()

int32_t Pcie_cfgRC ( Pcie_Handle handle )

Configure Pcie for RC (Root Complex) operation. PCIe mode setting is NOT done here (Pcie_setInterfaceMode)

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setCfgEn()

int32_t Pcie_setCfgEn	(	Pcie_Handle	handle,
		int	enable
	)

Set CONFIG_ENABLE to signal RC that the local EP configuration is completed.

setting CONFIG_ENABLE to '0' will generate a Configuration Request Retry Status (CRS) on Configuration Requests

setting CONFIG_ENABLE to '1' will generate a Succesful Completion/Unsupported Request (SC/UR) on Configuration Requests

Parameters

handle	Pcie_Handle returned from Pcie_open()
enable	Set (1) / Reset (0) CONFIG_ENABLE bit

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setSlotClockCnfg()

int32_t Pcie_setSlotClockCnfg	(	Pcie_Handle	handle,
		int	enable
	)

Set slot clock configuration bit in Link Status Register.

If set indicates the EP uses the reference clock provided on the connector, else the EP uses a independent clock

Parameters

handle	Pcie_Handle returned by Pcie_open()
enable	Enable(1) / disable (0) slot clock configuration

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setDwnStrIrq()

int32_t Pcie_setDwnStrIrq	(	Pcie_Handle	handle,
		int	enable
	)

Enable downstream interrupt in PCIE Controller.

Parameters

handle	Pcie_Handle returned by Pcie_open()
enable	Enable(1) / disable (0) downstream IRQ

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setLnkDwnStateIrq()

int32_t Pcie_setLnkDwnStateIrq	(	Pcie_Handle	handle,
		int	enable
	)

Enable link down status interrupt in PCIE Controller.

Parameters

handle	Pcie_Handle returned by Pcie_open()
enable	Enable(1) / disable (0) Linkdown State IRQ

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setPwrStateIrq()

int32_t Pcie_setPwrStateIrq	(	Pcie_Handle	handle,
		int	enable
	)

Enable power management state interrupt in PCIE Controller.

Parameters

handle	Pcie_Handle returned by Pcie_open()
enable	Enable(1) / disable (0) Power State IRQ

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_setHotResetIrq()

int32_t Pcie_setHotResetIrq	(	Pcie_Handle	handle,
		int	enable
	)

Enable hot reset interrupt in PCIE Controller.

Parameters

handle	Pcie_Handle returned by Pcie_open()
enable	Enable(1) / disable (0) Power State IRQ

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_ackDwnStrIrq()

int32_t Pcie_ackDwnStrIrq ( Pcie_Handle handle )

Acknowledge downstream interrupt.

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_ackLnkDwnStateIrq()

int32_t Pcie_ackLnkDwnStateIrq ( Pcie_Handle handle )

Acknowledge link down status interrupt.

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

◆ Pcie_ackPwrStateIrq()

int32_t Pcie_ackPwrStateIrq ( Pcie_Handle handle )

Acknowledge power management state interrupt.

Parameters

handle Pcie_Handle returned by Pcie_open()

Returns: SystemP_SUCCESS if successful; else error on failure

Variable Documentation

◆ gPcieConfig

Pcie_Config gPcieConfig[]

extern

Externally defined driver configuration array.

◆ gPcieConfigNum

uint32_t gPcieConfigNum

extern

Externally defined driver configuration array size.

Introduction

Files

Data Structures

Functions

Typedefs

Enumerations

Macros

Macro Definition Documentation

◆ PCIE_MAX_PERIPHS

◆ PCIE_MAX_MSI_IRQ

◆ PCIE_MAX_MSIX_IRQ

◆ PCIE_MAX_NUM_IBATU

Typedef Documentation

◆ Pcie_Handle

◆ Pcie_MsiIsr

◆ Pcie_MsixIsr

Enumeration Type Documentation

◆ Pcie_Mode

◆ Pcie_Gen

◆ Pcie_RefClk_Mode

◆ Pcie_SRIS_Mode

◆ Pcie_PwrState

◆ Pcie_IntPin

◆ Pcie_BarPref

◆ Pcie_BarType

◆ Pcie_BarMem

◆ Pcie_AtuRegionDir

◆ Pcie_TlpType

◆ Pcie_AtuRegionMatchMode

◆ Pcie_Location

◆ Pcie_LtssmState

Function Documentation

◆ Pcie_init()

◆ Pcie_open()

◆ Pcie_close()

◆ Pcie_handleGetBases()

◆ Pcie_setInterfaceMode()

◆ Pcie_getMemSpaceReserved()

◆ Pcie_getMemSpaceRange()

◆ Pcie_cfgBar()

◆ Pcie_atuRegionConfig()

◆ Pcie_getVendorId()

◆ Pcie_getPwrState()

◆ Pcie_getLinkParams()

◆ Pcie_isLinkUp()

◆ Pcie_waitLinkUp()

◆ Pcie_checkLinkParams()

◆ Pcie_LtssmCtrl()

◆ Pcie_setLanes()

◆ Pcie_cfgEP()

◆ Pcie_cfgRC()

◆ Pcie_setCfgEn()

◆ Pcie_setSlotClockCnfg()

◆ Pcie_setDwnStrIrq()

◆ Pcie_setLnkDwnStateIrq()

◆ Pcie_setPwrStateIrq()

◆ Pcie_setHotResetIrq()

◆ Pcie_ackDwnStrIrq()

◆ Pcie_ackLnkDwnStateIrq()

◆ Pcie_ackPwrStateIrq()

Variable Documentation

◆ gPcieConfig

◆ gPcieConfigNum