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AM62x MCU+ SDK
09.02.01
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AM62x MCU+ SDK
09.02.01
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Header file contains MemEntries, RamIdTables, aggrTables and aggrBaseAddressTable.
Go to the source code of this file.
Variables | |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_groupEntries [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries [SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_MemEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_MemEntries [SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries [SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries [SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries [SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_MemEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_MemEntries [SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_DMASS0_DMSS_AM62_ECCAGGR_MemEntries [SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_MemEntries [SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries [SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries [SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries [SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries [SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_SMS0_SMS_HSM_ECC_MemEntries [SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_SMS0_SMS_TIFS_ECC_MemEntries [SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_MemEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries [SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries [SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries [SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_MemConfig_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS] |
| static const SDL_GrpChkConfig_t | SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] |
| static const SDL_MemConfig_t | SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] |
| static const SDL_GrpChkConfig_t | SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] |
| static const SDL_RAMIdEntry_t | SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RamIdTable [SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable [SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RamIdTable [SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RamIdTable [SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable [SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable [SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable [SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RamIdTable [SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RamIdTable [SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_DMASS0_DMSS_AM62_ECCAGGR_RamIdTable [SDL_DMASS0_DMSS_AM62_ECCAGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RamIdTable [SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable [SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable [SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable [SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_SMS0_SMS_HSM_ECC_RamIdTable [SDL_SMS0_SMS_HSM_ECC_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_SMS0_SMS_TIFS_ECC_RamIdTable [SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RamIdTable [SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable [SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable [SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RamIdTable [SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable [SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable [SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] |
| static const SDL_RAMIdEntry_t | SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] |
| static SDL_ecc_aggrRegs *const | SDL_ECC_aggrBaseAddressTable [SDL_ECC_Base_Address_TOTAL_ENTRIES] |
| SDL_ecc_aggrRegs * | SDL_ECC_aggrTransBaseAddressTable [SDL_ECC_MEMTYPE_MAX] |
| static const SDL_EccAggrEntry_t | SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX] |
1.8.20