SDL_ECC_memEntries

Introduction

Macros
#define	SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (3U)
#define	SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (16U)
#define	SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES   (24U)
#define	SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (37U)
#define	SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS   (20U)
#define	SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)

Macro Definition Documentation

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)

SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (3U)

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (16U)

SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)

SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)

SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES   (27U)

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES   (27U)

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES   (27U)

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES   (27U)

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES   (24U)

SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_ECC_Base_Address_TOTAL_ENTRIES

#define SDL_ECC_Base_Address_TOTAL_ENTRIES   (37U)

SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS

#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS   (20U)

SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION

#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)

---

This structure holds the memory config for each memory subtype SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR

Variable Documentation

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC RAM ID

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC RAM ID

SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_MemEntries[SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_RAM_ID, 0x30040000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_RAM_ID, 0x30042000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x30074000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x30078000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_RAM_ID, 0x30050000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR

SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR

SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR

SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID, 0x3F004000u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)true) },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)true) },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_GICSS0_GIC500SS_1_4_ECC_AGGR

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR

SDL_DMASS0_DMSS_AM62_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_DMASS0_DMSS_AM62_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_DMASS0_DMSS_AM62_ECCAGGR

SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_MemEntries[SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_RAM_ID, 0x70000000u,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0 RAM ID

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

SDL_SMS0_SMS_HSM_ECC_MemEntries

const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_SMS0_SMS_HSM_ECC

SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL RAM ID

SDL_SMS0_SMS_TIFS_ECC_MemEntries

const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_SMS0_SMS_TIFS_ECC

SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_MemEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_14_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_16_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL RAM ID

SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC RAM ID

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL RAM ID

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20708000u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_18_WIDTH },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_M4FSS0_BLAZAR_ECC

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_18_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_15_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_15_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_15_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0 RAM ID

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL RAM ID

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x04E00000u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x04E10000u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    {  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR

SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RamIdTable[SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR

SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR

SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR

SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_GICSS0_GIC500SS_1_4_ECC_AGGR

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR

SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR

SDL_DMASS0_DMSS_AM62_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM62_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM62_ECCAGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DMASS0_DMSS_AM62_ECCAGGR

SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR

SDL_SMS0_SMS_HSM_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SMS0_SMS_HSM_ECC

SDL_SMS0_SMS_TIFS_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SMS0_SMS_TIFS_ECC

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR

SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC

SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable[SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_M4FSS0_BLAZAR_ECC

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR